From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C150C5CFEB for ; Wed, 11 Jul 2018 17:31:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1F79420C0E for ; Wed, 11 Jul 2018 17:31:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1F79420C0E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733012AbeGKRhR (ORCPT ); Wed, 11 Jul 2018 13:37:17 -0400 Received: from mga03.intel.com ([134.134.136.65]:20438 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732677AbeGKRhR (ORCPT ); Wed, 11 Jul 2018 13:37:17 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Jul 2018 10:31:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,338,1526367600"; d="scan'208";a="74003160" Received: from 2b52.sc.intel.com ([143.183.136.52]) by orsmga002.jf.intel.com with ESMTP; 11 Jul 2018 10:31:53 -0700 Message-ID: <1531330096.15351.10.camel@intel.com> Subject: Re: [RFC PATCH v2 12/27] x86/mm: Shadow stack page fault error checking From: Yu-cheng Yu To: Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Cyrill Gorcunov , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , "Ravi V. Shankar" , Vedvyas Shanbhogue Date: Wed, 11 Jul 2018 10:28:16 -0700 In-Reply-To: <61793360-f37c-ec19-c390-abe3c76a5f5c@linux.intel.com> References: <20180710222639.8241-1-yu-cheng.yu@intel.com> <20180710222639.8241-13-yu-cheng.yu@intel.com> <61793360-f37c-ec19-c390-abe3c76a5f5c@linux.intel.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.18.5.2-0ubuntu3.2 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2018-07-10 at 15:52 -0700, Dave Hansen wrote: > On 07/10/2018 03:26 PM, Yu-cheng Yu wrote: > > > > +++ b/arch/x86/include/asm/traps.h > > @@ -157,6 +157,7 @@ enum { > >   *   bit 3 == 1: use of reserved > > bit detected > >   *   bit 4 == 1: fault was an > > instruction fetch > >   *   bit 5 == 1: protection keys > > block access > > + *   bit 6 == 1: shadow stack > > access fault > >   */ > Could we document this bit better? > > Is this a fault where the *processor* thought it should be a shadow > stack fault?  Or is it also set on faults to valid shadow stack PTEs > that just happen to fault for other reasons, say protection keys? Thanks Vedvyas for explaining this to me. I will add this to comments: This flag is 1 if (1) CR4.CET = 1; and (2) the access causing the page- fault exception was a shadow-stack data access. So this bit does not report the reason for the fault. It reports the type of access; i.e. it was a shadow-stack-load or a shadow-stack-store that took the page fault. The fault could have been caused by any variety of reasons including protection keys.