From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7115ECDFBB for ; Tue, 24 Jul 2018 14:34:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6CC0B20852 for ; Tue, 24 Jul 2018 14:34:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6CC0B20852 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388617AbeGXPl0 (ORCPT ); Tue, 24 Jul 2018 11:41:26 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:2792 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388373AbeGXPlZ (ORCPT ); Tue, 24 Jul 2018 11:41:25 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Tue, 24 Jul 2018 07:34:42 -0700 Received: from HQMAIL108.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 24 Jul 2018 07:34:35 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 24 Jul 2018 07:34:35 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 24 Jul 2018 14:34:39 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 24 Jul 2018 14:34:38 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Tue, 24 Jul 2018 14:34:38 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 24 Jul 2018 07:34:38 -0700 From: Aapo Vienamo To: Ulf Hansson , Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , "Adrian Hunter" , Mikko Perttunen CC: , , , , Aapo Vienamo Subject: [PATCH 05/10] dt-bindings: Add Tegra SDHCI pad pdpu offset bindings Date: Tue, 24 Jul 2018 17:34:21 +0300 Message-ID: <1532442865-6391-4-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532442865-6391-1-git-send-email-avienamo@nvidia.com> References: <1532442591-5640-1-git-send-email-avienamo@nvidia.com> <1532442865-6391-1-git-send-email-avienamo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add bindings documentation for pad pull up and pull down offset values to be programmed before executing automatic pad drive strength calibration. Signed-off-by: Aapo Vienamo --- .../bindings/mmc/nvidia,tegra20-sdhci.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt index 90c214d..949f616 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt @@ -24,6 +24,7 @@ Required properties: Optional properties: - power-gpios : Specify GPIOs for power control +Optional properties for Tegra210 and Tegra186: Example: sdhci@c8000200 { @@ -45,6 +46,33 @@ Optional properties for Tegra210 and Tegra186: for controllers supporting multiple voltage levels. The order of names should correspond to the pin configuration states in pinctrl-0 and pinctrl-1. +- pad-autocal-pull-up-offset-3v3, pad-autocal-pull-down-offset-3v3 : + Specify drive strength calibration offsets for 3.3 V signaling modes. +- pad-autocal-pull-up-offset-1v8, pad-autocal-pull-down-offset-1v8 : + Specify drive strength calibration offsets for 1.8 V signaling modes. +- pad-autocal-pull-up-offset-3v3-timeout, + pad-autocal-pull-down-offset-3v3-timeout : Specify drive strength + used as a fallback in case the automatic calibration times out on a + 3.3 V signaling mode. +- pad-autocal-pull-up-offset-1v8-timeout, + pad-autocal-pull-down-offset-1v8-timeout : Specify drive strength + used as a fallback in case the automatic calibration times out on a + 1.8 V signaling mode. +- pad-autocal-pull-up-offset-sdr104, + pad-autocal-pull-down-offset-sdr104 : Specify drive strength + calibration offsets for SDR104 mode. +- pad-autocal-pull-up-offset-hs400, + pad-autocal-pull-down-offset-hs400 : Specify drive strength + calibration offsets for HS400 mode. + + Notes on the pad calibration pull up and pulldown offset values: + - The property values are drive codes which are programmed into the + PD_OFFSET and PU_OFFSET sections of the + SDHCI_TEGRA_AUTO_CAL_CONFIG register. + - A higher value corresponds to higher drive strength. Please refer + to the reference manual of the SoC for correct values. + - The SDR104 and HS400 timing specific values are used in + corresponding modes if specified. Example: sdhci@700b0000 { @@ -58,5 +86,9 @@ sdhci@700b0000 { pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; pinctrl-0 = <&sdmmc1_3v3>; pinctrl-1 = <&sdmmc1_1v8>; + pad-autocal-pull-up-offset-3v3 = <0x00>; + pad-autocal-pull-down-offset-3v3 = <0x7d>; + pad-autocal-pull-up-offset-1v8 = <0x7b>; + pad-autocal-pull-down-offset-1v8 = <0x7b>; status = "disabled"; }; -- 2.7.4