From: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
To: evgreen@chromium.org, robh@kernel.org, mchehab@kernel.org,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
andy.gross@linaro.org, david.brown@linaro.org,
linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
robh+dt@kernel.org, mark.rutland@arm.com,
devicetree@vger.kernel.org, tsoni@codeaurora.org,
ckadabi@codeaurora.org, rishabhb@codeaurora.org, bp@alien8.de
Cc: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Subject: [PATCH v1 4/4] dt-bindigs: Update documentation of qcom,llcc
Date: Wed, 1 Aug 2018 13:33:35 -0700 [thread overview]
Message-ID: <1533155615-27929-5-git-send-email-vnkgutta@codeaurora.org> (raw)
In-Reply-To: <1533155615-27929-1-git-send-email-vnkgutta@codeaurora.org>
Add reg-names and interrupts for LLCC documentation and the usage
examples. llcc broadcast base is added in addition to llcc base,
which is used for llcc broadcast writes.
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
---
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
index 5e85749..b4b1c86 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
@@ -18,9 +18,22 @@ Properties:
Value Type: <prop-encoded-array>
Definition: Start address and the the size of the register region.
+- reg-names:
+ Usage: required
+ Value Type: <stringlist>
+ Definition: Register region names. Must be "llcc_base", "llcc_bcast_base".
+
+- interrupts:
+ Usage: required
+ Definition: The interrupt is associated with the llcc edac device.
+ It's used for llcc cache single and double bit error detection
+ and reporting.
+
Example:
cache-controller@1100000 {
compatible = "qcom,sdm845-llcc";
- reg = <0x1100000 0x250000>;
+ reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
+ reg-names = "llcc_base", "llcc_bcast_base";
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
prev parent reply other threads:[~2018-08-01 20:34 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-01 20:33 [PATCH v1 0/4] Add EDAC driver for QCOM SoCs Venkata Narendra Kumar Gutta
2018-08-01 20:33 ` [PATCH v1 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC) Venkata Narendra Kumar Gutta
2018-08-01 20:33 ` [PATCH v1 2/4] drivers: soc: Add support to register LLCC EDAC driver Venkata Narendra Kumar Gutta
2018-08-10 17:21 ` Evan Green
2018-08-10 23:04 ` vnkgutta
2018-08-01 20:33 ` [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs Venkata Narendra Kumar Gutta
2018-08-08 23:11 ` vnkgutta
2018-08-10 3:59 ` Borislav Petkov
2018-08-10 23:03 ` vnkgutta
2018-08-10 17:23 ` Evan Green
2018-08-10 23:13 ` vnkgutta
2018-08-11 0:14 ` Evan Green
2018-08-01 20:33 ` Venkata Narendra Kumar Gutta [this message]
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