From: Zong Li <zong@andestech.com>
To: <palmer@sifive.com>, <aou@eecs.berkeley.edu>, <hch@infradead.org>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<greentime@andestech.com>
Cc: Zong Li <zong@andestech.com>
Subject: [PATCH v2] RISC-V: Add the directive for alignment of stvec's value
Date: Thu, 2 Aug 2018 23:21:56 +0800 [thread overview]
Message-ID: <1533223316-9942-1-git-send-email-zong@andestech.com> (raw)
The stvec's value must be 4 byte alignment by specification definition.
These directives avoid to stvec be set the non-alignment value.
Signed-off-by: Zong Li <zong@andestech.com>
---
arch/riscv/kernel/head.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 3b6293f..11066d5 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -94,6 +94,7 @@ relocate:
or a0, a0, a1
sfence.vma
csrw sptbr, a0
+.align 2
1:
/* Set trap vector to spin forever to help debug */
la a0, .Lsecondary_park
@@ -143,6 +144,7 @@ relocate:
tail smp_callin
#endif
+.align 2
.Lsecondary_park:
/* We lack SMP support or have too many harts, so park this hart */
wfi
--
2.7.4
next reply other threads:[~2018-08-02 15:23 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-02 15:21 Zong Li [this message]
[not found] ` <3AB16BFE6992A349B44EA6D8F29BFB476B1EA2CC@ATCPCS16.andestech.com>
2018-08-10 0:37 ` FW: [PATCH v2] RISC-V: Add the directive for alignment of stvec's value Zong Li
2018-08-10 1:50 ` Palmer Dabbelt
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