[PATCH v3 00/13] Add RDMA memory mode support for mediatek SOC MT2712

[PATCH v3 00/13] Add RDMA memory mode support for mediatek SOC MT2712

[Stu Hsieh]

This patch series add RDMA memory mode support for mediatek SOC MT2712.
MT2712 has three display data path, including three HW engine,
two OVL and one RDMA.

The RDMA used in third ddp and it need to be set memory mode,
then RDMA could read data from memory and output to panel.

Change in v3:
- Merge patch
  "drm/mediatek: add memory mode for RDMA" and
  "drm/mediatek: add layer config to set RDMA for plane setting"
  to "drm/mediatek: add memory mode and layer_config for RDMA"
- Move the "RDMA memory mode setting" from rdma_config to
  rdma_layer_config in patch
  "drm/mediatek: add memory mode and layer_config for RDMA"
- Remove the pathch
  "drm/mediatek: add RDMA memory mode for crtc created"
- add the return statement in patch
  "drm/mediatek: add function to get layer number for component"
  to abvoid warning message in build time
- Return layer_nr is 4 in patch
  "drm/mediatek: add callback function to return OVL layer number"
- Return layer_nr is 1 in patch
  "drm/mediatek: add callback function to return RDMA layer number"
- Dynamaic define the size of planes by layer_nr in patch
  "drm/mediatek: use layer_nr function to get layer number to init plane"
- Use ?: to init crtc for OVL or RDMA in patch
  "drm/mediatek: use layer_nr function to get layer number to init plane"

Stu Hsieh (13):
  drm/mediatek: add connection from RDMA0 to DPI1
  drm/mediatek: add connection from RDMA0 to DSI1
  drm/mediatek: add connection from RDMA1 to DSI0
  drm/mediatek: add connection from RDMA2 to DSI0
  drm/mediatek: add memory mode and layer_config for RDMA
  drm/mediatek: add RGB color format support for RDMA
  drm/mediatek: add YUYV/UYVY color format support for RDMA
  drm/mediatek: add function to get layer number for component
  drm/mediatek: add callback function to return OVL layer number
  drm/mediatek: add callback function to return RDMA layer number
  drm/mediatek: use layer_nr function to get layer number to init plane
  drm/mediatek: update some variable name from ovl to comp
  drm/mediatek: fix connection from RDMA2 to DSI1

 drivers/gpu/drm/mediatek/mtk_disp_ovl.c     |  6 +++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c    | 83 +++++++++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c     | 63 +++++++++++++---------
 drivers/gpu/drm/mediatek/mtk_drm_crtc.h     |  3 +-
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c      | 18 ++++++-
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  9 ++++
 6 files changed, 153 insertions(+), 29 deletions(-)

-- 
2.12.5.2.gbdf23ab

[PATCH v3 01/13] drm/mediatek: add connection from RDMA0 to DPI1

[Stu Hsieh]

This patch add connection from RDMA0 to DPI1

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 87e4191c250e..03e3628b5b0d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -106,6 +106,7 @@
 #define OVL1_MOUT_EN_COLOR1		0x1
 #define GAMMA_MOUT_EN_RDMA1		0x1
 #define RDMA0_SOUT_DPI0			0x2
+#define RDMA0_SOUT_DPI1			0x3
 #define RDMA0_SOUT_DSI2			0x4
 #define RDMA0_SOUT_DSI3			0x5
 #define RDMA1_SOUT_DPI0			0x2
@@ -224,6 +225,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
 	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
 		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
 		value = RDMA0_SOUT_DPI0;
+	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
+		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+		value = RDMA0_SOUT_DPI1;
 	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
 		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
 		value = RDMA0_SOUT_DSI2;
-- 
2.12.5.2.gbdf23ab

[PATCH v3 02/13] drm/mediatek: add connection from RDMA0 to DSI1

[Stu Hsieh]

This patch add connection from RDMA0 to DSI1

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 03e3628b5b0d..310d8482d5a0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -107,6 +107,7 @@
 #define GAMMA_MOUT_EN_RDMA1		0x1
 #define RDMA0_SOUT_DPI0			0x2
 #define RDMA0_SOUT_DPI1			0x3
+#define RDMA0_SOUT_DSI1			0x1
 #define RDMA0_SOUT_DSI2			0x4
 #define RDMA0_SOUT_DSI3			0x5
 #define RDMA1_SOUT_DPI0			0x2
@@ -228,6 +229,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
 	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
 		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
 		value = RDMA0_SOUT_DPI1;
+	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
+		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+		value = RDMA0_SOUT_DSI1;
 	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
 		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
 		value = RDMA0_SOUT_DSI2;
-- 
2.12.5.2.gbdf23ab

[PATCH v3 03/13] drm/mediatek: add connection from RDMA1 to DSI0

[Stu Hsieh]

This patch add connection from RDMA1 to DSI0

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 310d8482d5a0..31189fad8d4e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -124,6 +124,7 @@
 #define DPI0_SEL_IN_RDMA2		0x3
 #define DPI1_SEL_IN_RDMA1		(0x1 << 8)
 #define DPI1_SEL_IN_RDMA2		(0x3 << 8)
+#define DSI0_SEL_IN_RDMA1		0x1
 #define DSI1_SEL_IN_RDMA1		0x1
 #define DSI1_SEL_IN_RDMA2		0x4
 #define DSI2_SEL_IN_RDMA1		(0x1 << 16)
@@ -290,6 +291,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
 	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
 		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
 		value = DPI1_SEL_IN_RDMA1;
+	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
+		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+		value = DSI0_SEL_IN_RDMA1;
 	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
 		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
 		value = DSI1_SEL_IN_RDMA1;
-- 
2.12.5.2.gbdf23ab

[PATCH v3 04/13] drm/mediatek: add connection from RDMA2 to DSI0

[Stu Hsieh]

This patch add connection from RDMA2 to DSI0

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 31189fad8d4e..3239f22785fd 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -125,6 +125,7 @@
 #define DPI1_SEL_IN_RDMA1		(0x1 << 8)
 #define DPI1_SEL_IN_RDMA2		(0x3 << 8)
 #define DSI0_SEL_IN_RDMA1		0x1
+#define DSI0_SEL_IN_RDMA2		0x4
 #define DSI1_SEL_IN_RDMA1		0x1
 #define DSI1_SEL_IN_RDMA2		0x4
 #define DSI2_SEL_IN_RDMA1		(0x1 << 16)
@@ -309,6 +310,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
 	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
 		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
 		value = DPI1_SEL_IN_RDMA2;
+	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
+		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+		value = DSI0_SEL_IN_RDMA2;
 	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
 		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
 		value = DSI1_SEL_IN_RDMA2;
-- 
2.12.5.2.gbdf23ab

[PATCH v3 05/13] drm/mediatek: add memory mode and layer_config for RDMA

[Stu Hsieh]

This patch add memory mode for RDMA and layer_config for RDMA

If use RDMA to read data from memory, it should set memory mode to RDMA

Layer config set the data address and pitch to RDMA from plane setting.

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 585943c81e1f..08866550740f 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -31,14 +31,20 @@
 #define RDMA_REG_UPDATE_INT				BIT(0)
 #define DISP_REG_RDMA_GLOBAL_CON		0x0010
 #define RDMA_ENGINE_EN					BIT(0)
+#define RDMA_MODE_MEMORY				BIT(1)
 #define DISP_REG_RDMA_SIZE_CON_0		0x0014
 #define DISP_REG_RDMA_SIZE_CON_1		0x0018
 #define DISP_REG_RDMA_TARGET_LINE		0x001c
+#define DISP_RDMA_MEM_SRC_PITCH			0x002c
+#define DISP_RDMA_MEM_GMC_SETTING_0		0x0030
 #define DISP_REG_RDMA_FIFO_CON			0x0040
 #define RDMA_FIFO_UNDERFLOW_EN				BIT(31)
 #define RDMA_FIFO_PSEUDO_SIZE(bytes)			(((bytes) / 16) << 16)
 #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes)		((bytes) / 16)
 #define RDMA_FIFO_SIZE(rdma)			((rdma)->data->fifo_size)
+#define DISP_RDMA_MEM_START_ADDR		0x0f00
+
+#define RDMA_MEM_GMC				0x40402020
 
 struct mtk_disp_rdma_data {
 	unsigned int fifo_size;
@@ -138,12 +144,27 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
 	writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
 }
 
+static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
+				  struct mtk_plane_state *state)
+{
+	struct mtk_plane_pending_state *pending = &state->pending;
+	unsigned int addr = pending->addr;
+	unsigned int pitch = pending->pitch & 0xffff;
+
+	writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
+	writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);
+	writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0);
+	rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
+			 RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
+}
+
 static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = {
 	.config = mtk_rdma_config,
 	.start = mtk_rdma_start,
 	.stop = mtk_rdma_stop,
 	.enable_vblank = mtk_rdma_enable_vblank,
 	.disable_vblank = mtk_rdma_disable_vblank,
+	.layer_config = mtk_rdma_layer_config,
 };
 
 static int mtk_disp_rdma_bind(struct device *dev, struct device *master,
-- 
2.12.5.2.gbdf23ab

[PATCH v3 06/13] drm/mediatek: add RGB color format support for RDMA

[Stu Hsieh]

This patch add RGB color format support for RDMA,
including RGB565, RGB888, RGBA8888 and ARGB8888.

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 41 ++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 08866550740f..ba72d392dc27 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -35,6 +35,8 @@
 #define DISP_REG_RDMA_SIZE_CON_0		0x0014
 #define DISP_REG_RDMA_SIZE_CON_1		0x0018
 #define DISP_REG_RDMA_TARGET_LINE		0x001c
+#define DISP_RDMA_MEM_CON			0x0024
+#define MEM_MODE_INPUT_SWAP				BIT(8)
 #define DISP_RDMA_MEM_SRC_PITCH			0x002c
 #define DISP_RDMA_MEM_GMC_SETTING_0		0x0030
 #define DISP_REG_RDMA_FIFO_CON			0x0040
@@ -46,6 +48,11 @@
 
 #define RDMA_MEM_GMC				0x40402020
 
+#define MEM_MODE_INPUT_FORMAT_RGB565		0x0
+#define MEM_MODE_INPUT_FORMAT_RGB888		(0x001 << 4)
+#define MEM_MODE_INPUT_FORMAT_RGBA8888		(0x002 << 4)
+#define MEM_MODE_INPUT_FORMAT_ARGB8888		(0x003 << 4)
+
 struct mtk_disp_rdma_data {
 	unsigned int fifo_size;
 };
@@ -144,12 +151,46 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
 	writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
 }
 
+static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
+				     unsigned int fmt)
+{
+	switch (fmt) {
+	default:
+	case DRM_FORMAT_RGB565:
+		return MEM_MODE_INPUT_FORMAT_RGB565;
+	case DRM_FORMAT_BGR565:
+		return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP;
+	case DRM_FORMAT_RGB888:
+		return MEM_MODE_INPUT_FORMAT_RGB888;
+	case DRM_FORMAT_BGR888:
+		return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP;
+	case DRM_FORMAT_RGBX8888:
+	case DRM_FORMAT_RGBA8888:
+		return MEM_MODE_INPUT_FORMAT_ARGB8888;
+	case DRM_FORMAT_BGRX8888:
+	case DRM_FORMAT_BGRA8888:
+		return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP;
+	case DRM_FORMAT_XRGB8888:
+	case DRM_FORMAT_ARGB8888:
+		return MEM_MODE_INPUT_FORMAT_RGBA8888;
+	case DRM_FORMAT_XBGR8888:
+	case DRM_FORMAT_ABGR8888:
+		return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP;
+	}
+}
+
 static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
 				  struct mtk_plane_state *state)
 {
+	struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
 	struct mtk_plane_pending_state *pending = &state->pending;
 	unsigned int addr = pending->addr;
 	unsigned int pitch = pending->pitch & 0xffff;
+	unsigned int fmt = pending->format;
+	unsigned int con;
+
+	con = rdma_fmt_convert(rdma, fmt);
+	writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON);
 
 	writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
 	writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);
-- 
2.12.5.2.gbdf23ab

[PATCH v3 07/13] drm/mediatek: add YUYV/UYVY color format support for RDMA

[Stu Hsieh]

This patch add YUYV/UYVY color format support for RDMA
and transform matrix for YUYV/UYVY.

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index ba72d392dc27..91a8b6e27d39 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -33,6 +33,8 @@
 #define RDMA_ENGINE_EN					BIT(0)
 #define RDMA_MODE_MEMORY				BIT(1)
 #define DISP_REG_RDMA_SIZE_CON_0		0x0014
+#define RDMA_MATRIX_ENABLE				BIT(17)
+#define RDMA_MATRIX_INT_MTX_SEL				(7UL << 20)
 #define DISP_REG_RDMA_SIZE_CON_1		0x0018
 #define DISP_REG_RDMA_TARGET_LINE		0x001c
 #define DISP_RDMA_MEM_CON			0x0024
@@ -46,12 +48,15 @@
 #define RDMA_FIFO_SIZE(rdma)			((rdma)->data->fifo_size)
 #define DISP_RDMA_MEM_START_ADDR		0x0f00
 
+#define MATRIX_INT_MTX_SEL_DEFAULT		0xb00000
 #define RDMA_MEM_GMC				0x40402020
 
 #define MEM_MODE_INPUT_FORMAT_RGB565		0x0
 #define MEM_MODE_INPUT_FORMAT_RGB888		(0x001 << 4)
 #define MEM_MODE_INPUT_FORMAT_RGBA8888		(0x002 << 4)
 #define MEM_MODE_INPUT_FORMAT_ARGB8888		(0x003 << 4)
+#define MEM_MODE_INPUT_FORMAT_UYVY		(0x004 << 4)
+#define MEM_MODE_INPUT_FORMAT_YUYV		(0x005 << 4)
 
 struct mtk_disp_rdma_data {
 	unsigned int fifo_size;
@@ -176,6 +181,10 @@ static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
 	case DRM_FORMAT_XBGR8888:
 	case DRM_FORMAT_ABGR8888:
 		return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP;
+	case DRM_FORMAT_UYVY:
+		return MEM_MODE_INPUT_FORMAT_UYVY;
+	case DRM_FORMAT_YUYV:
+		return MEM_MODE_INPUT_FORMAT_YUYV;
 	}
 }
 
@@ -191,6 +200,12 @@ static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
 
 	con = rdma_fmt_convert(rdma, fmt);
 	writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON);
+	if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV)
+		rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
+				 RDMA_MATRIX_ENABLE | RDMA_MATRIX_INT_MTX_SEL);
+	else
+		rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
+				 MATRIX_INT_MTX_SEL_DEFAULT);
 
 	writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
 	writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);
-- 
2.12.5.2.gbdf23ab

[PATCH v3 08/13] drm/mediatek: add function to get layer number for component

[Stu Hsieh]

This patch add function to get layer number for component

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 7413ffeb3c9d..8399229e6ad2 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -78,6 +78,7 @@ struct mtk_ddp_comp_funcs {
 	void (*stop)(struct mtk_ddp_comp *comp);
 	void (*enable_vblank)(struct mtk_ddp_comp *comp, struct drm_crtc *crtc);
 	void (*disable_vblank)(struct mtk_ddp_comp *comp);
+	unsigned int (*layer_nr)(struct mtk_ddp_comp *comp);
 	void (*layer_on)(struct mtk_ddp_comp *comp, unsigned int idx);
 	void (*layer_off)(struct mtk_ddp_comp *comp, unsigned int idx);
 	void (*layer_config)(struct mtk_ddp_comp *comp, unsigned int idx,
@@ -128,6 +129,14 @@ static inline void mtk_ddp_comp_disable_vblank(struct mtk_ddp_comp *comp)
 		comp->funcs->disable_vblank(comp);
 }
 
+static inline unsigned int mtk_ddp_comp_layer_nr(struct mtk_ddp_comp *comp)
+{
+	if (comp->funcs && comp->funcs->layer_nr)
+		return comp->funcs->layer_nr(comp);
+
+	return 0;
+}
+
 static inline void mtk_ddp_comp_layer_on(struct mtk_ddp_comp *comp,
 					 unsigned int idx)
 {
-- 
2.12.5.2.gbdf23ab

[PATCH v3 09/13] drm/mediatek: add callback function to return OVL layer number

[Stu Hsieh]

This patch add callback function to return OVL layer number

For now, MT8173, MT2712, MT2701 OVL all has 4 layer.

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 978782a77629..66060e79afbc 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -132,6 +132,11 @@ static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w,
 	writel(0x0, comp->regs + DISP_REG_OVL_RST);
 }
 
+static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp)
+{
+	return 4;
+}
+
 static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)
 {
 	unsigned int reg;
@@ -221,6 +226,7 @@ static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = {
 	.stop = mtk_ovl_stop,
 	.enable_vblank = mtk_ovl_enable_vblank,
 	.disable_vblank = mtk_ovl_disable_vblank,
+	.layer_nr = mtk_ovl_layer_nr,
 	.layer_on = mtk_ovl_layer_on,
 	.layer_off = mtk_ovl_layer_off,
 	.layer_config = mtk_ovl_layer_config,
-- 
2.12.5.2.gbdf23ab

[PATCH v3 10/13] drm/mediatek: add callback function to return RDMA layer number

[Stu Hsieh]

This patch add callback function to return RDMA layer number

RDMA always has one layer.

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 91a8b6e27d39..68c99253285b 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -188,6 +188,11 @@ static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
 	}
 }
 
+static unsigned int mtk_rdma_layer_nr(struct mtk_ddp_comp *comp)
+{
+	return 1;
+}
+
 static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
 				  struct mtk_plane_state *state)
 {
@@ -220,6 +225,7 @@ static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = {
 	.stop = mtk_rdma_stop,
 	.enable_vblank = mtk_rdma_enable_vblank,
 	.disable_vblank = mtk_rdma_disable_vblank,
+	.layer_nr = mtk_rdma_layer_nr,
 	.layer_config = mtk_rdma_layer_config,
 };
 
-- 
2.12.5.2.gbdf23ab

[PATCH v3 11/13] drm/mediatek: use layer_nr function to get layer number to init plane

[Stu Hsieh]

This patch use layer_nr function to get layer number to init plane

When plane init in crtc create,
it use the number of OVL layer to init plane.
That's OVL can read 4 memory address.

For mt2712 third ddp, it use RDMA to read memory.
RDMA can read 1 memory address, so it just init one plane.

For compatibility, this patch use mtk_ddp_comp_layer_nr function
to get layer number from their HW component in ddp for plane init.

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 37 +++++++++++++++++++++------------
 drivers/gpu/drm/mediatek/mtk_drm_crtc.h |  1 -
 2 files changed, 24 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 2d6aa150a9ff..1a8685fbbf57 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -45,7 +45,8 @@ struct mtk_drm_crtc {
 	bool				pending_needs_vblank;
 	struct drm_pending_vblank_event	*event;
 
-	struct drm_plane		planes[OVL_LAYER_NR];
+	struct drm_plane		**planes;
+	unsigned int			layer_nr;
 	bool				pending_planes;
 
 	void __iomem			*config_regs;
@@ -286,8 +287,8 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
 	}
 
 	/* Initially configure all planes */
-	for (i = 0; i < OVL_LAYER_NR; i++) {
-		struct drm_plane *plane = &mtk_crtc->planes[i];
+	for (i = 0; i < mtk_crtc->layer_nr; i++) {
+		struct drm_plane *plane = mtk_crtc->planes[i];
 		struct mtk_plane_state *plane_state;
 
 		plane_state = to_mtk_plane_state(plane->state);
@@ -351,8 +352,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
 	}
 
 	if (mtk_crtc->pending_planes) {
-		for (i = 0; i < OVL_LAYER_NR; i++) {
-			struct drm_plane *plane = &mtk_crtc->planes[i];
+		for (i = 0; i < mtk_crtc->layer_nr; i++) {
+			struct drm_plane *plane = mtk_crtc->planes[i];
 			struct mtk_plane_state *plane_state;
 
 			plane_state = to_mtk_plane_state(plane->state);
@@ -403,8 +404,8 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
 		return;
 
 	/* Set all pending plane state to disabled */
-	for (i = 0; i < OVL_LAYER_NR; i++) {
-		struct drm_plane *plane = &mtk_crtc->planes[i];
+	for (i = 0; i < mtk_crtc->layer_nr; i++) {
+		struct drm_plane *plane = mtk_crtc->planes[i];
 		struct mtk_plane_state *plane_state;
 
 		plane_state = to_mtk_plane_state(plane->state);
@@ -450,8 +451,8 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
 
 	if (mtk_crtc->event)
 		mtk_crtc->pending_needs_vblank = true;
-	for (i = 0; i < OVL_LAYER_NR; i++) {
-		struct drm_plane *plane = &mtk_crtc->planes[i];
+	for (i = 0; i < mtk_crtc->layer_nr; i++) {
+		struct drm_plane *plane = mtk_crtc->planes[i];
 		struct mtk_plane_state *plane_state;
 
 		plane_state = to_mtk_plane_state(plane->state);
@@ -598,18 +599,28 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
 		mtk_crtc->ddp_comp[i] = comp;
 	}
 
-	for (zpos = 0; zpos < OVL_LAYER_NR; zpos++) {
+	mtk_crtc->layer_nr = mtk_ddp_comp_layer_nr(mtk_crtc->ddp_comp[0]);
+	mtk_crtc->planes = devm_kmalloc_array(dev, mtk_crtc->layer_nr,
+					      sizeof(*mtk_crtc->planes),
+					      GFP_KERNEL);
+
+	for (zpos = 0; zpos < mtk_crtc->layer_nr; zpos++) {
+		mtk_crtc->planes[zpos] = devm_kzalloc(dev,
+						sizeof(*mtk_crtc->planes[zpos]),
+						GFP_KERNEL);
+
 		type = (zpos == 0) ? DRM_PLANE_TYPE_PRIMARY :
 				(zpos == 1) ? DRM_PLANE_TYPE_CURSOR :
 						DRM_PLANE_TYPE_OVERLAY;
-		ret = mtk_plane_init(drm_dev, &mtk_crtc->planes[zpos],
+		ret = mtk_plane_init(drm_dev, mtk_crtc->planes[zpos],
 				     BIT(pipe), type);
 		if (ret)
 			goto unprepare;
 	}
 
-	ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0],
-				&mtk_crtc->planes[1], pipe);
+	ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, mtk_crtc->planes[0],
+				mtk_crtc->layer_nr > 1 ? mtk_crtc->planes[1] :
+				NULL, pipe);
 	if (ret < 0)
 		goto unprepare;
 	drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index 9d9410c67ae9..60bcc8aba8e3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -18,7 +18,6 @@
 #include "mtk_drm_ddp_comp.h"
 #include "mtk_drm_plane.h"
 
-#define OVL_LAYER_NR	4
 #define MTK_LUT_SIZE	512
 #define MTK_MAX_BPC	10
 #define MTK_MIN_BPC	3
-- 
2.12.5.2.gbdf23ab

[PATCH v3 12/13] drm/mediatek: update some variable name from ovl to comp

[Stu Hsieh]

This patch update some variable name from ovl to comp

Because RDMA would be first HW in ddp, the naming ovl
should be change to comp.

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 26 +++++++++++++-------------
 drivers/gpu/drm/mediatek/mtk_drm_crtc.h |  2 +-
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 1a8685fbbf57..e31722db3184 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -172,9 +172,9 @@ static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
 {
 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
-	struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 
-	mtk_ddp_comp_enable_vblank(ovl, &mtk_crtc->base);
+	mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base);
 
 	return 0;
 }
@@ -182,9 +182,9 @@ static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
 {
 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
-	struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 
-	mtk_ddp_comp_disable_vblank(ovl);
+	mtk_ddp_comp_disable_vblank(comp);
 }
 
 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
@@ -335,7 +335,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
 {
 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 	struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
-	struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 	unsigned int i;
 
 	/*
@@ -344,7 +344,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
 	 * queue update module registers on vblank.
 	 */
 	if (state->pending_config) {
-		mtk_ddp_comp_config(ovl, state->pending_width,
+		mtk_ddp_comp_config(comp, state->pending_width,
 				    state->pending_height,
 				    state->pending_vrefresh, 0);
 
@@ -359,7 +359,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
 			plane_state = to_mtk_plane_state(plane->state);
 
 			if (plane_state->pending.config) {
-				mtk_ddp_comp_layer_config(ovl, i, plane_state);
+				mtk_ddp_comp_layer_config(comp, i, plane_state);
 				plane_state->pending.config = false;
 			}
 		}
@@ -371,12 +371,12 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
 				       struct drm_crtc_state *old_state)
 {
 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
-	struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 	int ret;
 
 	DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
 
-	ret = mtk_smi_larb_get(ovl->larb_dev);
+	ret = mtk_smi_larb_get(comp->larb_dev);
 	if (ret) {
 		DRM_ERROR("Failed to get larb: %d\n", ret);
 		return;
@@ -384,7 +384,7 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
 
 	ret = mtk_crtc_ddp_hw_init(mtk_crtc);
 	if (ret) {
-		mtk_smi_larb_put(ovl->larb_dev);
+		mtk_smi_larb_put(comp->larb_dev);
 		return;
 	}
 
@@ -396,7 +396,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
 					struct drm_crtc_state *old_state)
 {
 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
-	struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 	int i;
 
 	DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
@@ -419,7 +419,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
 
 	drm_crtc_vblank_off(crtc);
 	mtk_crtc_ddp_hw_fini(mtk_crtc);
-	mtk_smi_larb_put(ovl->larb_dev);
+	mtk_smi_larb_put(comp->larb_dev);
 
 	mtk_crtc->enabled = false;
 }
@@ -517,7 +517,7 @@ static int mtk_drm_crtc_init(struct drm_device *drm,
 	return ret;
 }
 
-void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl)
+void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp)
 {
 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 	struct mtk_drm_private *priv = crtc->dev->dev_private;
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index 60bcc8aba8e3..091adb2087eb 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -23,7 +23,7 @@
 #define MTK_MIN_BPC	3
 
 void mtk_drm_crtc_commit(struct drm_crtc *crtc);
-void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl);
+void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp);
 int mtk_drm_crtc_create(struct drm_device *drm_dev,
 			const enum mtk_ddp_comp_id *path,
 			unsigned int path_len);
-- 
2.12.5.2.gbdf23ab

[PATCH v3 13/13] drm/mediatek: fix connection from RDMA2 to DSI1

[Stu Hsieh]

This patch fix connection from RDMA2 to DSI1

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 3239f22785fd..546b3e3b300b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -314,7 +314,7 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
 		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
 		value = DSI0_SEL_IN_RDMA2;
 	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
-		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
 		value = DSI1_SEL_IN_RDMA2;
 	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
 		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
-- 
2.12.5.2.gbdf23ab

Re: [PATCH v3 05/13] drm/mediatek: add memory mode and layer_config for RDMA

[CK Hu]

Hi, Stu:

On Mon, 2018-08-06 at 19:58 +0800, Stu Hsieh wrote:
> This patch add memory mode for RDMA and layer_config for RDMA
> 
> If use RDMA to read data from memory, it should set memory mode to RDMA
> 
> Layer config set the data address and pitch to RDMA from plane setting.
> 
> Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> ---
>  drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 585943c81e1f..08866550740f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -31,14 +31,20 @@
>  #define RDMA_REG_UPDATE_INT				BIT(0)
>  #define DISP_REG_RDMA_GLOBAL_CON		0x0010
>  #define RDMA_ENGINE_EN					BIT(0)
> +#define RDMA_MODE_MEMORY				BIT(1)
>  #define DISP_REG_RDMA_SIZE_CON_0		0x0014
>  #define DISP_REG_RDMA_SIZE_CON_1		0x0018
>  #define DISP_REG_RDMA_TARGET_LINE		0x001c
> +#define DISP_RDMA_MEM_SRC_PITCH			0x002c
> +#define DISP_RDMA_MEM_GMC_SETTING_0		0x0030
>  #define DISP_REG_RDMA_FIFO_CON			0x0040
>  #define RDMA_FIFO_UNDERFLOW_EN				BIT(31)
>  #define RDMA_FIFO_PSEUDO_SIZE(bytes)			(((bytes) / 16) << 16)
>  #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes)		((bytes) / 16)
>  #define RDMA_FIFO_SIZE(rdma)			((rdma)->data->fifo_size)
> +#define DISP_RDMA_MEM_START_ADDR		0x0f00
> +
> +#define RDMA_MEM_GMC				0x40402020
>  
>  struct mtk_disp_rdma_data {
>  	unsigned int fifo_size;
> @@ -138,12 +144,27 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
>  	writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
>  }
>  
> +static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> +				  struct mtk_plane_state *state)
> +{
> +	struct mtk_plane_pending_state *pending = &state->pending;
> +	unsigned int addr = pending->addr;
> +	unsigned int pitch = pending->pitch & 0xffff;
> +
> +	writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
> +	writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);
> +	writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0);
> +	rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
> +			 RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
> +}
> +
>  static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = {
>  	.config = mtk_rdma_config,
>  	.start = mtk_rdma_start,
>  	.stop = mtk_rdma_stop,
>  	.enable_vblank = mtk_rdma_enable_vblank,
>  	.disable_vblank = mtk_rdma_disable_vblank,
> +	.layer_config = mtk_rdma_layer_config,
>  };
>  
>  static int mtk_disp_rdma_bind(struct device *dev, struct device *master,

Re: [PATCH v3 06/13] drm/mediatek: add RGB color format support for RDMA

[CK Hu]

Hi, Stu:

On Mon, 2018-08-06 at 19:58 +0800, Stu Hsieh wrote:
> This patch add RGB color format support for RDMA,
> including RGB565, RGB888, RGBA8888 and ARGB8888.
> 
> Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 41 ++++++++++++++++++++++++++++++++
>  1 file changed, 41 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 08866550740f..ba72d392dc27 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -35,6 +35,8 @@
>  #define DISP_REG_RDMA_SIZE_CON_0		0x0014
>  #define DISP_REG_RDMA_SIZE_CON_1		0x0018
>  #define DISP_REG_RDMA_TARGET_LINE		0x001c
> +#define DISP_RDMA_MEM_CON			0x0024
> +#define MEM_MODE_INPUT_SWAP				BIT(8)
>  #define DISP_RDMA_MEM_SRC_PITCH			0x002c
>  #define DISP_RDMA_MEM_GMC_SETTING_0		0x0030
>  #define DISP_REG_RDMA_FIFO_CON			0x0040
> @@ -46,6 +48,11 @@
>  
>  #define RDMA_MEM_GMC				0x40402020
>  
> +#define MEM_MODE_INPUT_FORMAT_RGB565		0x0
> +#define MEM_MODE_INPUT_FORMAT_RGB888		(0x001 << 4)
> +#define MEM_MODE_INPUT_FORMAT_RGBA8888		(0x002 << 4)
> +#define MEM_MODE_INPUT_FORMAT_ARGB8888		(0x003 << 4)
> +
>  struct mtk_disp_rdma_data {
>  	unsigned int fifo_size;
>  };
> @@ -144,12 +151,46 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
>  	writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
>  }
>  
> +static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
> +				     unsigned int fmt)
> +{
> +	switch (fmt) {
> +	default:
> +	case DRM_FORMAT_RGB565:
> +		return MEM_MODE_INPUT_FORMAT_RGB565;
> +	case DRM_FORMAT_BGR565:
> +		return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP;
> +	case DRM_FORMAT_RGB888:
> +		return MEM_MODE_INPUT_FORMAT_RGB888;
> +	case DRM_FORMAT_BGR888:
> +		return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP;
> +	case DRM_FORMAT_RGBX8888:
> +	case DRM_FORMAT_RGBA8888:
> +		return MEM_MODE_INPUT_FORMAT_ARGB8888;

I think the alphabet order of the naming reflect the dram order for each
color. Of course, big-endian and little-endian would result in reversed
naming order. I could not understand why RDMA use ARGB8888 naming for
DRM RGBA8888. If the typo is from data sheet, I could just accept this
typo and give an explain in driver because I want to align driver with
data sheet.

Regards,
CK

> +	case DRM_FORMAT_BGRX8888:
> +	case DRM_FORMAT_BGRA8888:
> +		return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP;
> +	case DRM_FORMAT_XRGB8888:
> +	case DRM_FORMAT_ARGB8888:
> +		return MEM_MODE_INPUT_FORMAT_RGBA8888;
> +	case DRM_FORMAT_XBGR8888:
> +	case DRM_FORMAT_ABGR8888:
> +		return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP;
> +	}
> +}
> +
>  static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
>  				  struct mtk_plane_state *state)
>  {
> +	struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
>  	struct mtk_plane_pending_state *pending = &state->pending;
>  	unsigned int addr = pending->addr;
>  	unsigned int pitch = pending->pitch & 0xffff;
> +	unsigned int fmt = pending->format;
> +	unsigned int con;
> +
> +	con = rdma_fmt_convert(rdma, fmt);
> +	writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON);
>  
>  	writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
>  	writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);

Re: [PATCH v3 07/13] drm/mediatek: add YUYV/UYVY color format support for RDMA

[CK Hu]

Hi, Stu:

On Mon, 2018-08-06 at 19:58 +0800, Stu Hsieh wrote:
> This patch add YUYV/UYVY color format support for RDMA
> and transform matrix for YUYV/UYVY.
> 
> Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index ba72d392dc27..91a8b6e27d39 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -33,6 +33,8 @@
>  #define RDMA_ENGINE_EN					BIT(0)
>  #define RDMA_MODE_MEMORY				BIT(1)
>  #define DISP_REG_RDMA_SIZE_CON_0		0x0014
> +#define RDMA_MATRIX_ENABLE				BIT(17)
> +#define RDMA_MATRIX_INT_MTX_SEL				(7UL << 20)
>  #define DISP_REG_RDMA_SIZE_CON_1		0x0018
>  #define DISP_REG_RDMA_TARGET_LINE		0x001c
>  #define DISP_RDMA_MEM_CON			0x0024
> @@ -46,12 +48,15 @@
>  #define RDMA_FIFO_SIZE(rdma)			((rdma)->data->fifo_size)
>  #define DISP_RDMA_MEM_START_ADDR		0x0f00
>  
> +#define MATRIX_INT_MTX_SEL_DEFAULT		0xb00000
>  #define RDMA_MEM_GMC				0x40402020
>  
>  #define MEM_MODE_INPUT_FORMAT_RGB565		0x0
>  #define MEM_MODE_INPUT_FORMAT_RGB888		(0x001 << 4)
>  #define MEM_MODE_INPUT_FORMAT_RGBA8888		(0x002 << 4)
>  #define MEM_MODE_INPUT_FORMAT_ARGB8888		(0x003 << 4)
> +#define MEM_MODE_INPUT_FORMAT_UYVY		(0x004 << 4)
> +#define MEM_MODE_INPUT_FORMAT_YUYV		(0x005 << 4)
>  
>  struct mtk_disp_rdma_data {
>  	unsigned int fifo_size;
> @@ -176,6 +181,10 @@ static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
>  	case DRM_FORMAT_XBGR8888:
>  	case DRM_FORMAT_ABGR8888:
>  		return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP;
> +	case DRM_FORMAT_UYVY:
> +		return MEM_MODE_INPUT_FORMAT_UYVY;
> +	case DRM_FORMAT_YUYV:
> +		return MEM_MODE_INPUT_FORMAT_YUYV;
>  	}
>  }
>  
> @@ -191,6 +200,12 @@ static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
>  
>  	con = rdma_fmt_convert(rdma, fmt);
>  	writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON);
> +	if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV)
> +		rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,

Symbolize 0xff0000. Maybe you should define as

#define RDMA_MATRIX_INT_MTX_SEL GENMASK(23, 20)
#define RDMA_MATRIX_INT_MTX_YUV_TO_RGB   0x7
#define RDMA_MATRIX_INT_MTX_RGB_TO_RGB   0xb

Correct the naming to align data sheet.

Regards,
CK

> +				 RDMA_MATRIX_ENABLE | RDMA_MATRIX_INT_MTX_SEL);
> +	else
> +		rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
> +				 MATRIX_INT_MTX_SEL_DEFAULT);
>  
>  	writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
>  	writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);

Re: [PATCH v3 08/13] drm/mediatek: add function to get layer number for component

[CK Hu]

Hi, Stu:

On Mon, 2018-08-06 at 19:58 +0800, Stu Hsieh wrote:
> This patch add function to get layer number for component
> 
> Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 7413ffeb3c9d..8399229e6ad2 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -78,6 +78,7 @@ struct mtk_ddp_comp_funcs {
>  	void (*stop)(struct mtk_ddp_comp *comp);
>  	void (*enable_vblank)(struct mtk_ddp_comp *comp, struct drm_crtc *crtc);
>  	void (*disable_vblank)(struct mtk_ddp_comp *comp);
> +	unsigned int (*layer_nr)(struct mtk_ddp_comp *comp);
>  	void (*layer_on)(struct mtk_ddp_comp *comp, unsigned int idx);
>  	void (*layer_off)(struct mtk_ddp_comp *comp, unsigned int idx);
>  	void (*layer_config)(struct mtk_ddp_comp *comp, unsigned int idx,
> @@ -128,6 +129,14 @@ static inline void mtk_ddp_comp_disable_vblank(struct mtk_ddp_comp *comp)
>  		comp->funcs->disable_vblank(comp);
>  }
>  
> +static inline unsigned int mtk_ddp_comp_layer_nr(struct mtk_ddp_comp *comp)
> +{
> +	if (comp->funcs && comp->funcs->layer_nr)
> +		return comp->funcs->layer_nr(comp);
> +
> +	return 0;
> +}
> +
>  static inline void mtk_ddp_comp_layer_on(struct mtk_ddp_comp *comp,
>  					 unsigned int idx)
>  {

Re: [PATCH v3 09/13] drm/mediatek: add callback function to return OVL layer number

[CK Hu]

Hi, Stu:

On Mon, 2018-08-06 at 19:58 +0800, Stu Hsieh wrote:
> This patch add callback function to return OVL layer number
> 
> For now, MT8173, MT2712, MT2701 OVL all has 4 layer.
> 
> Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>

I would like to remove the term 'callback' because this is just function
pointer rather than callback function. OVL does not register callback
function to crtc and crtc call OVL function directly. The modification
is good to me, so

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> ---
>  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 978782a77629..66060e79afbc 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -132,6 +132,11 @@ static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w,
>  	writel(0x0, comp->regs + DISP_REG_OVL_RST);
>  }
>  
> +static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp)
> +{
> +	return 4;
> +}
> +
>  static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)
>  {
>  	unsigned int reg;
> @@ -221,6 +226,7 @@ static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = {
>  	.stop = mtk_ovl_stop,
>  	.enable_vblank = mtk_ovl_enable_vblank,
>  	.disable_vblank = mtk_ovl_disable_vblank,
> +	.layer_nr = mtk_ovl_layer_nr,
>  	.layer_on = mtk_ovl_layer_on,
>  	.layer_off = mtk_ovl_layer_off,
>  	.layer_config = mtk_ovl_layer_config,

Re: [PATCH v3 10/13] drm/mediatek: add callback function to return RDMA layer number

[CK Hu]

Hi, Stu:

On Mon, 2018-08-06 at 19:58 +0800, Stu Hsieh wrote:
> This patch add callback function to return RDMA layer number
> 
> RDMA always has one layer.
> 
> Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>

I would like to remove the term 'callback' because this is just function
pointer rather than callback function. OVL does not register callback
function to crtc and crtc call OVL function directly. The modification
is good to me, so

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> ---
>  drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 91a8b6e27d39..68c99253285b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -188,6 +188,11 @@ static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
>  	}
>  }
>  
> +static unsigned int mtk_rdma_layer_nr(struct mtk_ddp_comp *comp)
> +{
> +	return 1;
> +}
> +
>  static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
>  				  struct mtk_plane_state *state)
>  {
> @@ -220,6 +225,7 @@ static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = {
>  	.stop = mtk_rdma_stop,
>  	.enable_vblank = mtk_rdma_enable_vblank,
>  	.disable_vblank = mtk_rdma_disable_vblank,
> +	.layer_nr = mtk_rdma_layer_nr,
>  	.layer_config = mtk_rdma_layer_config,
>  };
>  

Re: [PATCH v3 11/13] drm/mediatek: use layer_nr function to get layer number to init plane

[CK Hu]

Hi, Stu:

On Mon, 2018-08-06 at 19:58 +0800, Stu Hsieh wrote:
> This patch use layer_nr function to get layer number to init plane
> 
> When plane init in crtc create,
> it use the number of OVL layer to init plane.
> That's OVL can read 4 memory address.
> 
> For mt2712 third ddp, it use RDMA to read memory.
> RDMA can read 1 memory address, so it just init one plane.
> 
> For compatibility, this patch use mtk_ddp_comp_layer_nr function
> to get layer number from their HW component in ddp for plane init.
> 
> Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 37 +++++++++++++++++++++------------
>  drivers/gpu/drm/mediatek/mtk_drm_crtc.h |  1 -
>  2 files changed, 24 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 2d6aa150a9ff..1a8685fbbf57 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -45,7 +45,8 @@ struct mtk_drm_crtc {
>  	bool				pending_needs_vblank;
>  	struct drm_pending_vblank_event	*event;
>  
> -	struct drm_plane		planes[OVL_LAYER_NR];
> +	struct drm_plane		**planes;

Why double pointer? This make things more complicated.
Single pointer is equal to array, so you need not to modify so many
place.

Regards,
CK

> +	unsigned int			layer_nr;
>  	bool				pending_planes;
>  
>  	void __iomem			*config_regs;
> @@ -286,8 +287,8 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
>  	}
>  
>  	/* Initially configure all planes */
> -	for (i = 0; i < OVL_LAYER_NR; i++) {
> -		struct drm_plane *plane = &mtk_crtc->planes[i];
> +	for (i = 0; i < mtk_crtc->layer_nr; i++) {
> +		struct drm_plane *plane = mtk_crtc->planes[i];
>  		struct mtk_plane_state *plane_state;
>  
>  		plane_state = to_mtk_plane_state(plane->state);
> @@ -351,8 +352,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
>  	}
>  
>  	if (mtk_crtc->pending_planes) {
> -		for (i = 0; i < OVL_LAYER_NR; i++) {
> -			struct drm_plane *plane = &mtk_crtc->planes[i];
> +		for (i = 0; i < mtk_crtc->layer_nr; i++) {
> +			struct drm_plane *plane = mtk_crtc->planes[i];
>  			struct mtk_plane_state *plane_state;
>  
>  			plane_state = to_mtk_plane_state(plane->state);
> @@ -403,8 +404,8 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
>  		return;
>  
>  	/* Set all pending plane state to disabled */
> -	for (i = 0; i < OVL_LAYER_NR; i++) {
> -		struct drm_plane *plane = &mtk_crtc->planes[i];
> +	for (i = 0; i < mtk_crtc->layer_nr; i++) {
> +		struct drm_plane *plane = mtk_crtc->planes[i];
>  		struct mtk_plane_state *plane_state;
>  
>  		plane_state = to_mtk_plane_state(plane->state);
> @@ -450,8 +451,8 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
>  
>  	if (mtk_crtc->event)
>  		mtk_crtc->pending_needs_vblank = true;
> -	for (i = 0; i < OVL_LAYER_NR; i++) {
> -		struct drm_plane *plane = &mtk_crtc->planes[i];
> +	for (i = 0; i < mtk_crtc->layer_nr; i++) {
> +		struct drm_plane *plane = mtk_crtc->planes[i];
>  		struct mtk_plane_state *plane_state;
>  
>  		plane_state = to_mtk_plane_state(plane->state);
> @@ -598,18 +599,28 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
>  		mtk_crtc->ddp_comp[i] = comp;
>  	}
>  
> -	for (zpos = 0; zpos < OVL_LAYER_NR; zpos++) {
> +	mtk_crtc->layer_nr = mtk_ddp_comp_layer_nr(mtk_crtc->ddp_comp[0]);
> +	mtk_crtc->planes = devm_kmalloc_array(dev, mtk_crtc->layer_nr,
> +					      sizeof(*mtk_crtc->planes),
> +					      GFP_KERNEL);
> +
> +	for (zpos = 0; zpos < mtk_crtc->layer_nr; zpos++) {
> +		mtk_crtc->planes[zpos] = devm_kzalloc(dev,
> +						sizeof(*mtk_crtc->planes[zpos]),
> +						GFP_KERNEL);
> +
>  		type = (zpos == 0) ? DRM_PLANE_TYPE_PRIMARY :
>  				(zpos == 1) ? DRM_PLANE_TYPE_CURSOR :
>  						DRM_PLANE_TYPE_OVERLAY;
> -		ret = mtk_plane_init(drm_dev, &mtk_crtc->planes[zpos],
> +		ret = mtk_plane_init(drm_dev, mtk_crtc->planes[zpos],
>  				     BIT(pipe), type);
>  		if (ret)
>  			goto unprepare;
>  	}
>  
> -	ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0],
> -				&mtk_crtc->planes[1], pipe);
> +	ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, mtk_crtc->planes[0],
> +				mtk_crtc->layer_nr > 1 ? mtk_crtc->planes[1] :
> +				NULL, pipe);
>  	if (ret < 0)
>  		goto unprepare;
>  	drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> index 9d9410c67ae9..60bcc8aba8e3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> @@ -18,7 +18,6 @@
>  #include "mtk_drm_ddp_comp.h"
>  #include "mtk_drm_plane.h"
>  
> -#define OVL_LAYER_NR	4
>  #define MTK_LUT_SIZE	512
>  #define MTK_MAX_BPC	10
>  #define MTK_MIN_BPC	3

Re: [PATCH v3 07/13] drm/mediatek: add YUYV/UYVY color format support for RDMA

[Stu Hsieh]

Hi, CK:

On Tue, 2018-08-07 at 11:33 +0800, CK Hu wrote:
> Hi, Stu:
> 
> On Mon, 2018-08-06 at 19:58 +0800, Stu Hsieh wrote:
> > This patch add YUYV/UYVY color format support for RDMA
> > and transform matrix for YUYV/UYVY.
> > 
> > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 15 +++++++++++++++
> >  1 file changed, 15 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > index ba72d392dc27..91a8b6e27d39 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > @@ -33,6 +33,8 @@
> >  #define RDMA_ENGINE_EN					BIT(0)
> >  #define RDMA_MODE_MEMORY				BIT(1)
> >  #define DISP_REG_RDMA_SIZE_CON_0		0x0014
> > +#define RDMA_MATRIX_ENABLE				BIT(17)
> > +#define RDMA_MATRIX_INT_MTX_SEL				(7UL << 20)
> >  #define DISP_REG_RDMA_SIZE_CON_1		0x0018
> >  #define DISP_REG_RDMA_TARGET_LINE		0x001c
> >  #define DISP_RDMA_MEM_CON			0x0024
> > @@ -46,12 +48,15 @@
> >  #define RDMA_FIFO_SIZE(rdma)			((rdma)->data->fifo_size)
> >  #define DISP_RDMA_MEM_START_ADDR		0x0f00
> >  
> > +#define MATRIX_INT_MTX_SEL_DEFAULT		0xb00000
> >  #define RDMA_MEM_GMC				0x40402020
> >  
> >  #define MEM_MODE_INPUT_FORMAT_RGB565		0x0
> >  #define MEM_MODE_INPUT_FORMAT_RGB888		(0x001 << 4)
> >  #define MEM_MODE_INPUT_FORMAT_RGBA8888		(0x002 << 4)
> >  #define MEM_MODE_INPUT_FORMAT_ARGB8888		(0x003 << 4)
> > +#define MEM_MODE_INPUT_FORMAT_UYVY		(0x004 << 4)
> > +#define MEM_MODE_INPUT_FORMAT_YUYV		(0x005 << 4)
> >  
> >  struct mtk_disp_rdma_data {
> >  	unsigned int fifo_size;
> > @@ -176,6 +181,10 @@ static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
> >  	case DRM_FORMAT_XBGR8888:
> >  	case DRM_FORMAT_ABGR8888:
> >  		return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP;
> > +	case DRM_FORMAT_UYVY:
> > +		return MEM_MODE_INPUT_FORMAT_UYVY;
> > +	case DRM_FORMAT_YUYV:
> > +		return MEM_MODE_INPUT_FORMAT_YUYV;
> >  	}
> >  }
> >  
> > @@ -191,6 +200,12 @@ static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> >  
> >  	con = rdma_fmt_convert(rdma, fmt);
> >  	writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON);
> > +	if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV)
> > +		rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
> 
> Symbolize 0xff0000. Maybe you should define as
> 
> #define RDMA_MATRIX_INT_MTX_SEL GENMASK(23, 20)
> #define RDMA_MATRIX_INT_MTX_YUV_TO_RGB   0x7
> #define RDMA_MATRIX_INT_MTX_RGB_TO_RGB   0xb
> 
> Correct the naming to align data sheet.
> 
> Regards,
> CK
> 
OK

Regards,
Stu

> > +				 RDMA_MATRIX_ENABLE | RDMA_MATRIX_INT_MTX_SEL);
> > +	else
> > +		rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
> > +				 MATRIX_INT_MTX_SEL_DEFAULT);
> >  
> >  	writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
> >  	writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);
> 
> 

Re: [PATCH v3 06/13] drm/mediatek: add RGB color format support for RDMA

[Stu Hsieh]

Hi, CK:

On Tue, 2018-08-07 at 11:01 +0800, CK Hu wrote:
> Hi, Stu:
> 
> On Mon, 2018-08-06 at 19:58 +0800, Stu Hsieh wrote:
> > This patch add RGB color format support for RDMA,
> > including RGB565, RGB888, RGBA8888 and ARGB8888.
> > 
> > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 41 ++++++++++++++++++++++++++++++++
> >  1 file changed, 41 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > index 08866550740f..ba72d392dc27 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > @@ -35,6 +35,8 @@
> >  #define DISP_REG_RDMA_SIZE_CON_0		0x0014
> >  #define DISP_REG_RDMA_SIZE_CON_1		0x0018
> >  #define DISP_REG_RDMA_TARGET_LINE		0x001c
> > +#define DISP_RDMA_MEM_CON			0x0024
> > +#define MEM_MODE_INPUT_SWAP				BIT(8)
> >  #define DISP_RDMA_MEM_SRC_PITCH			0x002c
> >  #define DISP_RDMA_MEM_GMC_SETTING_0		0x0030
> >  #define DISP_REG_RDMA_FIFO_CON			0x0040
> > @@ -46,6 +48,11 @@
> >  
> >  #define RDMA_MEM_GMC				0x40402020
> >  
> > +#define MEM_MODE_INPUT_FORMAT_RGB565		0x0
> > +#define MEM_MODE_INPUT_FORMAT_RGB888		(0x001 << 4)
> > +#define MEM_MODE_INPUT_FORMAT_RGBA8888		(0x002 << 4)
> > +#define MEM_MODE_INPUT_FORMAT_ARGB8888		(0x003 << 4)
> > +
> >  struct mtk_disp_rdma_data {
> >  	unsigned int fifo_size;
> >  };
> > @@ -144,12 +151,46 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> >  	writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
> >  }
> >  
> > +static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
> > +				     unsigned int fmt)
> > +{
> > +	switch (fmt) {
> > +	default:
> > +	case DRM_FORMAT_RGB565:
> > +		return MEM_MODE_INPUT_FORMAT_RGB565;
> > +	case DRM_FORMAT_BGR565:
> > +		return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP;
> > +	case DRM_FORMAT_RGB888:
> > +		return MEM_MODE_INPUT_FORMAT_RGB888;
> > +	case DRM_FORMAT_BGR888:
> > +		return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP;
> > +	case DRM_FORMAT_RGBX8888:
> > +	case DRM_FORMAT_RGBA8888:
> > +		return MEM_MODE_INPUT_FORMAT_ARGB8888;
> 
> I think the alphabet order of the naming reflect the dram order for each
> color. Of course, big-endian and little-endian would result in reversed
> naming order. I could not understand why RDMA use ARGB8888 naming for
> DRM RGBA8888. If the typo is from data sheet, I could just accept this
> typo and give an explain in driver because I want to align driver with
> data sheet.
> 
> Regards,
> CK
> 
OK, I would add the comment about this naming in driver rdma.c and ovl.c

Regard,
Stu

> > +	case DRM_FORMAT_BGRX8888:
> > +	case DRM_FORMAT_BGRA8888:
> > +		return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP;
> > +	case DRM_FORMAT_XRGB8888:
> > +	case DRM_FORMAT_ARGB8888:
> > +		return MEM_MODE_INPUT_FORMAT_RGBA8888;
> > +	case DRM_FORMAT_XBGR8888:
> > +	case DRM_FORMAT_ABGR8888:
> > +		return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP;
> > +	}
> > +}
> > +
> >  static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> >  				  struct mtk_plane_state *state)
> >  {
> > +	struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
> >  	struct mtk_plane_pending_state *pending = &state->pending;
> >  	unsigned int addr = pending->addr;
> >  	unsigned int pitch = pending->pitch & 0xffff;
> > +	unsigned int fmt = pending->format;
> > +	unsigned int con;
> > +
> > +	con = rdma_fmt_convert(rdma, fmt);
> > +	writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON);
> >  
> >  	writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
> >  	writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);
> 
> 

Re: [PATCH v3 11/13] drm/mediatek: use layer_nr function to get layer number to init plane

[Stu Hsieh]

Hi,CK:

On Tue, 2018-08-07 at 12:32 +0800, CK Hu wrote:
> Hi, Stu:
> 
> On Mon, 2018-08-06 at 19:58 +0800, Stu Hsieh wrote:
> > This patch use layer_nr function to get layer number to init plane
> > 
> > When plane init in crtc create,
> > it use the number of OVL layer to init plane.
> > That's OVL can read 4 memory address.
> > 
> > For mt2712 third ddp, it use RDMA to read memory.
> > RDMA can read 1 memory address, so it just init one plane.
> > 
> > For compatibility, this patch use mtk_ddp_comp_layer_nr function
> > to get layer number from their HW component in ddp for plane init.
> > 
> > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 37 +++++++++++++++++++++------------
> >  drivers/gpu/drm/mediatek/mtk_drm_crtc.h |  1 -
> >  2 files changed, 24 insertions(+), 14 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > index 2d6aa150a9ff..1a8685fbbf57 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > @@ -45,7 +45,8 @@ struct mtk_drm_crtc {
> >  	bool				pending_needs_vblank;
> >  	struct drm_pending_vblank_event	*event;
> >  
> > -	struct drm_plane		planes[OVL_LAYER_NR];
> > +	struct drm_plane		**planes;
> 
> Why double pointer? This make things more complicated.
> Single pointer is equal to array, so you need not to modify so many
> place.
> 
> Regards,
> CK
> 
ok

Regards,
Stu

> > +	unsigned int			layer_nr;
> >  	bool				pending_planes;
> >  
> >  	void __iomem			*config_regs;
> > @@ -286,8 +287,8 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
> >  	}
> >  
> >  	/* Initially configure all planes */
> > -	for (i = 0; i < OVL_LAYER_NR; i++) {
> > -		struct drm_plane *plane = &mtk_crtc->planes[i];
> > +	for (i = 0; i < mtk_crtc->layer_nr; i++) {
> > +		struct drm_plane *plane = mtk_crtc->planes[i];
> >  		struct mtk_plane_state *plane_state;
> >  
> >  		plane_state = to_mtk_plane_state(plane->state);
> > @@ -351,8 +352,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
> >  	}
> >  
> >  	if (mtk_crtc->pending_planes) {
> > -		for (i = 0; i < OVL_LAYER_NR; i++) {
> > -			struct drm_plane *plane = &mtk_crtc->planes[i];
> > +		for (i = 0; i < mtk_crtc->layer_nr; i++) {
> > +			struct drm_plane *plane = mtk_crtc->planes[i];
> >  			struct mtk_plane_state *plane_state;
> >  
> >  			plane_state = to_mtk_plane_state(plane->state);
> > @@ -403,8 +404,8 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
> >  		return;
> >  
> >  	/* Set all pending plane state to disabled */
> > -	for (i = 0; i < OVL_LAYER_NR; i++) {
> > -		struct drm_plane *plane = &mtk_crtc->planes[i];
> > +	for (i = 0; i < mtk_crtc->layer_nr; i++) {
> > +		struct drm_plane *plane = mtk_crtc->planes[i];
> >  		struct mtk_plane_state *plane_state;
> >  
> >  		plane_state = to_mtk_plane_state(plane->state);
> > @@ -450,8 +451,8 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
> >  
> >  	if (mtk_crtc->event)
> >  		mtk_crtc->pending_needs_vblank = true;
> > -	for (i = 0; i < OVL_LAYER_NR; i++) {
> > -		struct drm_plane *plane = &mtk_crtc->planes[i];
> > +	for (i = 0; i < mtk_crtc->layer_nr; i++) {
> > +		struct drm_plane *plane = mtk_crtc->planes[i];
> >  		struct mtk_plane_state *plane_state;
> >  
> >  		plane_state = to_mtk_plane_state(plane->state);
> > @@ -598,18 +599,28 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> >  		mtk_crtc->ddp_comp[i] = comp;
> >  	}
> >  
> > -	for (zpos = 0; zpos < OVL_LAYER_NR; zpos++) {
> > +	mtk_crtc->layer_nr = mtk_ddp_comp_layer_nr(mtk_crtc->ddp_comp[0]);
> > +	mtk_crtc->planes = devm_kmalloc_array(dev, mtk_crtc->layer_nr,
> > +					      sizeof(*mtk_crtc->planes),
> > +					      GFP_KERNEL);
> > +
> > +	for (zpos = 0; zpos < mtk_crtc->layer_nr; zpos++) {
> > +		mtk_crtc->planes[zpos] = devm_kzalloc(dev,
> > +						sizeof(*mtk_crtc->planes[zpos]),
> > +						GFP_KERNEL);
> > +
> >  		type = (zpos == 0) ? DRM_PLANE_TYPE_PRIMARY :
> >  				(zpos == 1) ? DRM_PLANE_TYPE_CURSOR :
> >  						DRM_PLANE_TYPE_OVERLAY;
> > -		ret = mtk_plane_init(drm_dev, &mtk_crtc->planes[zpos],
> > +		ret = mtk_plane_init(drm_dev, mtk_crtc->planes[zpos],
> >  				     BIT(pipe), type);
> >  		if (ret)
> >  			goto unprepare;
> >  	}
> >  
> > -	ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0],
> > -				&mtk_crtc->planes[1], pipe);
> > +	ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, mtk_crtc->planes[0],
> > +				mtk_crtc->layer_nr > 1 ? mtk_crtc->planes[1] :
> > +				NULL, pipe);
> >  	if (ret < 0)
> >  		goto unprepare;
> >  	drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > index 9d9410c67ae9..60bcc8aba8e3 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > @@ -18,7 +18,6 @@
> >  #include "mtk_drm_ddp_comp.h"
> >  #include "mtk_drm_plane.h"
> >  
> > -#define OVL_LAYER_NR	4
> >  #define MTK_LUT_SIZE	512
> >  #define MTK_MAX_BPC	10
> >  #define MTK_MIN_BPC	3
> 
>