From: Aapo Vienamo <avienamo@nvidia.com>
To: Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Adrian Hunter <adrian.hunter@intel.com>,
Mikko Perttunen <mperttunen@nvidia.com>,
Stefan Agner <stefan@agner.ch>
Cc: <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>,
Aapo Vienamo <avienamo@nvidia.com>
Subject: [PATCH v2 22/40] mmc: tegra: Configure default tap values
Date: Fri, 10 Aug 2018 21:08:24 +0300 [thread overview]
Message-ID: <1533924522-1037-23-git-send-email-avienamo@nvidia.com> (raw)
In-Reply-To: <1533924522-1037-1-git-send-email-avienamo@nvidia.com>
Set the default inbound timing adjustment tap value on reset and on
non-tunable modes.
The default tap value is not programmed on tunable modes because the
tuning sequence is used instead to determine the tap value.
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
---
drivers/mmc/host/sdhci-tegra.c | 132 ++++++++++++++++++++++++-----------------
1 file changed, 77 insertions(+), 55 deletions(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 0c39c54..208a269 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -213,6 +213,58 @@ static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host)
return true;
}
+static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable)
+{
+ bool status;
+ u32 reg;
+
+ reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ status = !!(reg & SDHCI_CLOCK_CARD_EN);
+
+ if (status == enable)
+ return status;
+
+ if (enable)
+ reg |= SDHCI_CLOCK_CARD_EN;
+ else
+ reg &= ~SDHCI_CLOCK_CARD_EN;
+
+ sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
+
+ return status;
+}
+
+
+static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
+ const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
+ bool card_clk_enabled = false;
+ u32 reg;
+
+ /*
+ * Touching the tap values is a bit tricky on some SoC generations.
+ * The quirk enables a workaround for a glitch that sometimes occurs if
+ * the tap values are changed.
+ */
+
+ if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP)
+ card_clk_enabled = tegra_sdhci_configure_card_clk(host, false);
+
+ reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
+ reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
+ reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
+ sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
+
+ if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP &&
+ card_clk_enabled) {
+ udelay(1);
+ sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+ tegra_sdhci_configure_card_clk(host, card_clk_enabled);
+ }
+}
+
static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -225,6 +277,8 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
if (!(mask & SDHCI_RESET_ALL))
return;
+ tegra_sdhci_set_tap(host, tegra_host->default_tap);
+
misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
@@ -286,27 +340,6 @@ static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable)
usleep_range(1, 2);
}
-static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable)
-{
- bool status;
- u32 reg;
-
- reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
- status = !!(reg & SDHCI_CLOCK_CARD_EN);
-
- if (status == enable)
- return status;
-
- if (enable)
- reg |= SDHCI_CLOCK_CARD_EN;
- else
- reg &= ~SDHCI_CLOCK_CARD_EN;
-
- sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
-
- return status;
-}
-
static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host,
u16 pdpu)
{
@@ -502,19 +535,6 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
}
}
-static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
- unsigned timing)
-{
- struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
- struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
-
- if (timing == MMC_TIMING_UHS_DDR50 ||
- timing == MMC_TIMING_MMC_DDR52)
- tegra_host->ddr_signaling = true;
-
- sdhci_set_uhs_signaling(host, timing);
-}
-
static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -522,34 +542,36 @@ static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
return clk_round_rate(pltfm_host->clk, UINT_MAX);
}
-static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
+static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
+ unsigned timing)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
- const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
- bool card_clk_enabled = false;
- u32 reg;
+ bool set_default_tap = false;
- /*
- * Touching the tap values is a bit tricky on some SoC generations.
- * The quirk enables a workaround for a glitch that sometimes occurs if
- * the tap values are changed.
- */
+ switch (timing) {
+ case MMC_TIMING_UHS_SDR50:
+ case MMC_TIMING_UHS_SDR104:
+ case MMC_TIMING_MMC_HS200:
+ case MMC_TIMING_MMC_HS400:
+ /* Don't set default tap on tunable modes. */
+ break;
+ case MMC_TIMING_MMC_DDR52:
+ case MMC_TIMING_UHS_DDR50:
+ tegra_host->ddr_signaling = true;
+ set_default_tap = true;
+ break;
+ default:
+ set_default_tap = true;
+ break;
+ }
- if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP)
- card_clk_enabled = tegra_sdhci_configure_card_clk(host, false);
+ sdhci_set_uhs_signaling(host, timing);
- reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
- reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
- reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
- sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
+ tegra_sdhci_pad_autocalib(host);
- if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP &&
- card_clk_enabled) {
- usleep_range(1, 2);
- sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
- tegra_sdhci_configure_card_clk(host, card_clk_enabled);
- }
+ if (set_default_tap)
+ tegra_sdhci_set_tap(host, tegra_host->default_tap);
}
static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
--
2.7.4
next prev parent reply other threads:[~2018-08-10 18:10 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-10 18:08 [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 01/40] dt-bindings: Add Tegra PMC pad configuration bindings Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 02/40] dt-bindings: mmc: tegra: Add pad voltage control properties Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 03/40] dt-bindings: Add Tegra SDHCI pad pdpu offset bindings Aapo Vienamo
2018-08-13 19:24 ` Rob Herring
2018-08-10 18:08 ` [PATCH v2 04/40] dt-bindings: mmc: Add Tegra SDHCI sampling trimmer values Aapo Vienamo
2018-08-13 19:25 ` Rob Herring
2018-08-10 18:08 ` [PATCH v2 05/40] soc/tegra: pmc: Fix pad voltage configuration for Tegra186 Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 06/40] soc/tegra: pmc: Factor out DPD register bit calculation Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 07/40] soc/tegra: pmc: Implement tegra_io_pad_is_powered() Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 08/40] soc/tegra: pmc: Use X macro to generate IO pad tables Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 09/40] soc/tegra: pmc: Remove public pad voltage APIs Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 10/40] soc/tegra: pmc: Implement pad configuration via pinctrl Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 11/40] mmc: sdhci: Add a quirk to skip clearing the transfer mode register on tuning Aapo Vienamo
2018-08-27 11:01 ` Adrian Hunter
2018-08-28 14:45 ` Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 12/40] mmc: tegra: Reconfigure pad voltages during voltage switching Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 13/40] mmc: tegra: Poll for calibration completion Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 14/40] mmc: tegra: Set calibration pad voltage reference Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 15/40] mmc: tegra: Power on the calibration pad Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 16/40] mmc: tegra: Disable card clock during pad calibration Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 17/40] mmc: tegra: Program pad autocal offsets from dt Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 18/40] mmc: tegra: Perform pad calibration after voltage switch Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 19/40] mmc: tegra: Enable pad calibration on Tegra210 and Tegra186 Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 20/40] mmc: tegra: Add a workaround for tap value change glitch Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 21/40] mmc: tegra: Parse default trim and tap from dt Aapo Vienamo
2018-08-10 18:08 ` Aapo Vienamo [this message]
2018-08-10 18:08 ` [PATCH v2 23/40] mmc: tegra: Configure default trim value on reset Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 24/40] mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186 Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 25/40] mmc: sdhci: Add a quirk to disable card clock during tuning Aapo Vienamo
2018-08-27 11:25 ` Adrian Hunter
2018-08-28 15:41 ` Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 26/40] mmc: tegra: Enable workaround for tuning transfer mode bug Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 27/40] mmc: tegra: Set SDHCI_QUIRK2_TUNE_DIS_CARD_CLK on Tegra210 Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 28/40] mmc: tegra: Enable UHS and HS200 modes for Tegra210 Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 29/40] mmc: tegra: Enable UHS and HS200 modes for Tegra186 Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 30/40] arm64: dts: Add Tegra210 sdmmc pinctrl voltage states Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 31/40] arm64: dts: Add Tegra186 " Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 32/40] arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 33/40] arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 34/40] arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 35/40] arm64: dts: tegra186: Add sdmmc pad auto calibration offsets Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 36/40] arm64: dts: tegra210: " Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 37/40] arm64: dts: tegra210: Add SDHCI tap and trim values Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 38/40] arm64: dts: tegra186: " Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 39/40] arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4 Aapo Vienamo
2018-08-10 18:08 ` [PATCH v2 40/40] arm64: dts: tegra210: " Aapo Vienamo
2018-08-23 8:47 ` [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling Thierry Reding
2018-08-23 10:42 ` Ulf Hansson
2018-08-27 10:10 ` Thierry Reding
2018-08-27 10:26 ` Adrian Hunter
2018-08-27 11:43 ` Adrian Hunter
2018-08-27 14:10 ` Marcel Ziswiler
2018-08-27 15:50 ` Thierry Reding
2018-08-27 15:57 ` Thierry Reding
2018-08-27 16:27 ` Aapo Vienamo
2018-08-27 21:35 ` Marcel Ziswiler
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1533924522-1037-23-git-send-email-avienamo@nvidia.com \
--to=avienamo@nvidia.com \
--cc=adrian.hunter@intel.com \
--cc=devicetree@vger.kernel.org \
--cc=jonathanh@nvidia.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mmc@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mperttunen@nvidia.com \
--cc=robh+dt@kernel.org \
--cc=stefan@agner.ch \
--cc=thierry.reding@gmail.com \
--cc=ulf.hansson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).