From: Aapo Vienamo <avienamo@nvidia.com>
To: Ulf Hansson <ulf.hansson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Mikko Perttunen <mperttunen@nvidia.com>
Cc: <linux-mmc@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Aapo Vienamo <avienamo@nvidia.com>
Subject: [PATCH v2 1/8] dt-bindings: mmc: Add DQS trim value to Tegra SDHCI
Date: Fri, 10 Aug 2018 21:13:58 +0300 [thread overview]
Message-ID: <1533924845-1466-2-git-send-email-avienamo@nvidia.com> (raw)
In-Reply-To: <1533924845-1466-1-git-send-email-avienamo@nvidia.com>
Document HS400 DQS trim value device tree property.
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
---
Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
index edecf97..32b4b4e 100644
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
@@ -71,6 +71,7 @@ Optional properties for Tegra210 and Tegra186:
trimmer value for non-tunable modes.
- nvidia,default-trim : Specify the default outbound clock trimmer
value.
+- nvidia,dqs-trim : Specify DQS trim value for HS400 timing
Notes on the pad calibration pull up and pulldown offset values:
- The property values are drive codes which are programmed into the
@@ -87,6 +88,9 @@ Optional properties for Tegra210 and Tegra186:
- The values are programmed to the Vendor Clock Control Register.
Please refer to the reference manual of the SoC for correct
values.
+ - The DQS trim values are only used on controllers which support
+ HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports
+ HS400.
Example:
sdhci@700b0000 {
--
2.7.4
next prev parent reply other threads:[~2018-08-10 18:14 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-10 18:13 [PATCH v2 0/8] Tegra SDHCI support HS400 on Tegra210 and Tegra186 Aapo Vienamo
2018-08-10 18:13 ` Aapo Vienamo [this message]
2018-08-13 19:26 ` [PATCH v2 1/8] dt-bindings: mmc: Add DQS trim value to Tegra SDHCI Rob Herring
2018-08-10 18:13 ` [PATCH v2 2/8] mmc: tegra: Parse and program DQS trim value Aapo Vienamo
2018-08-10 18:14 ` [PATCH v2 3/8] mmc: tegra: Implement HS400 enhanced strobe Aapo Vienamo
2018-08-10 18:14 ` [PATCH v2 4/8] mmc: tegra: Implement HS400 delay line calibration Aapo Vienamo
2018-08-10 18:14 ` [PATCH v2 5/8] arm64: dts: tegra186: Add SDMMC4 DQS trim value Aapo Vienamo
2018-08-10 18:14 ` [PATCH v2 6/8] arm64: dts: tegra210: " Aapo Vienamo
2018-08-10 18:14 ` [PATCH v2 7/8] arm64: dts: tegra186: Enable HS400 Aapo Vienamo
2018-08-10 18:14 ` [PATCH v2 8/8] arm64: dts: tegra210: " Aapo Vienamo
2018-08-24 9:11 ` [PATCH v2 0/8] Tegra SDHCI support HS400 on Tegra210 and Tegra186 Thierry Reding
2018-08-27 9:50 ` Ulf Hansson
2018-08-27 10:08 ` Thierry Reding
2018-08-27 10:26 ` Adrian Hunter
2018-08-27 11:47 ` Adrian Hunter
2018-08-31 14:02 ` Thierry Reding
2018-09-03 6:14 ` Ulf Hansson
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