[PATCH v2 0/8] Tegra SDHCI support HS400 on Tegra210 and Tegra186

[PATCH v2 0/8] Tegra SDHCI support HS400 on Tegra210 and Tegra186

[Aapo Vienamo]

Hi all,
This series implements support for HS400 signaling on Tegra210 and
Tegra186. This includes programming the DQS trimmer values, implementing
enhanced strobe and HS400 delay line calibration.

This series depends on the "Tegra SDHCI add support for HS200 and UHS
signaling" series.

Changelog:
v2:
	- Document in dt-bindings which controllers support HS400
	- Use val instead of reg in tegra_sdhci_set_dqs_trim()
	- Change "dt" to "DT" in "mmc: tegra: Parse and program DQS trim
	  value" commit message
	- Add spaces around << in tegra_sdhci_set_dqs_trim()
	- Make the "mmc: tegra: Implement HS400 enhanced strobe" commit
	  message more detailed
	- Remove a debug print from tegra_sdhci_hs400_enhanced_strobe()
	- Add blank lines around if-else-block in
	  tegra_sdhci_hs400_enhanced_strobe()
	- Use val instead of reg in tegra_sdhci_hs400_enhanced_strobe()
	- Make commit message of "mmc: tegra: Implement HS400 delay line
	  calibration" more detailed

Aapo Vienamo (8):
  dt-bindings: mmc: Add DQS trim value to Tegra SDHCI
  mmc: tegra: Parse and program DQS trim value
  mmc: tegra: Implement HS400 enhanced strobe
  mmc: tegra: Implement HS400 delay line calibration
  arm64: dts: tegra186: Add SDMMC4 DQS trim value
  arm64: dts: tegra210: Add SDMMC4 DQS trim value
  arm64: dts: tegra186: Enable HS400
  arm64: dts: tegra210: Enable HS400

 .../bindings/mmc/nvidia,tegra20-sdhci.txt          |  4 ++
 arch/arm64/boot/dts/nvidia/tegra186.dtsi           |  2 +
 arch/arm64/boot/dts/nvidia/tegra210.dtsi           |  2 +
 drivers/mmc/host/sdhci-tegra.c                     | 84 +++++++++++++++++++++-
 4 files changed, 89 insertions(+), 3 deletions(-)

-- 
2.7.4

[PATCH v2 1/8] dt-bindings: mmc: Add DQS trim value to Tegra SDHCI

[Aapo Vienamo]

Document HS400 DQS trim value device tree property.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
---
 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
index edecf97..32b4b4e 100644
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
@@ -71,6 +71,7 @@ Optional properties for Tegra210 and Tegra186:
   trimmer value for non-tunable modes.
 - nvidia,default-trim : Specify the default outbound clock trimmer
   value.
+- nvidia,dqs-trim : Specify DQS trim value for HS400 timing
 
   Notes on the pad calibration pull up and pulldown offset values:
     - The property values are drive codes which are programmed into the
@@ -87,6 +88,9 @@ Optional properties for Tegra210 and Tegra186:
     - The values are programmed to the Vendor Clock Control Register.
       Please refer to the reference manual of the SoC for correct
       values.
+    - The DQS trim values are only used on controllers which support
+      HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports
+      HS400.
 
 Example:
 sdhci@700b0000 {
-- 
2.7.4

[PATCH v2 2/8] mmc: tegra: Parse and program DQS trim value

[Aapo Vienamo]

Parse and program the HS400 DQS trim value from DT. Program a fallback
value in case the property is missing.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
---
 drivers/mmc/host/sdhci-tegra.c | 32 +++++++++++++++++++++++++++++---
 1 file changed, 29 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 2d775ad..6ec92bc 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -43,6 +43,10 @@
 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE		BIT(3)
 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE	BIT(2)
 
+#define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES		0x10c
+#define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK		0x00003f00
+#define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT	8
+
 #define SDHCI_TEGRA_VENDOR_MISC_CTRL			0x120
 #define SDHCI_MISC_CTRL_ENABLE_SDR104			0x8
 #define SDHCI_MISC_CTRL_ENABLE_SDR50			0x10
@@ -112,6 +116,7 @@ struct sdhci_tegra {
 
 	u32 default_tap;
 	u32 default_trim;
+	u32 dqs_trim;
 };
 
 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
@@ -502,7 +507,7 @@ static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host)
 		autocal->pull_down_hs400 = autocal->pull_down_1v8;
 }
 
-static void tegra_sdhci_parse_default_tap_and_trim(struct sdhci_host *host)
+static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host)
 {
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
@@ -517,6 +522,11 @@ static void tegra_sdhci_parse_default_tap_and_trim(struct sdhci_host *host)
 				       &tegra_host->default_trim);
 	if (err)
 		tegra_host->default_trim = 0;
+
+	err = device_property_read_u32(host->mmc->parent, "nvidia,dqs-trim",
+				       &tegra_host->dqs_trim);
+	if (err)
+		tegra_host->dqs_trim = 0x11;
 }
 
 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
@@ -547,20 +557,33 @@ static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
 	return clk_round_rate(pltfm_host->clk, UINT_MAX);
 }
 
+static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim)
+{
+	u32 val;
+
+	val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES);
+	val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK;
+	val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT;
+	sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES);
+}
+
 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
 					  unsigned timing)
 {
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 	bool set_default_tap = false;
+	bool set_dqs_trim = false;
 
 	switch (timing) {
 	case MMC_TIMING_UHS_SDR50:
 	case MMC_TIMING_UHS_SDR104:
 	case MMC_TIMING_MMC_HS200:
-	case MMC_TIMING_MMC_HS400:
 		/* Don't set default tap on tunable modes. */
 		break;
+	case MMC_TIMING_MMC_HS400:
+		set_dqs_trim = true;
+		break;
 	case MMC_TIMING_MMC_DDR52:
 	case MMC_TIMING_UHS_DDR50:
 		tegra_host->ddr_signaling = true;
@@ -577,6 +600,9 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
 
 	if (set_default_tap)
 		tegra_sdhci_set_tap(host, tegra_host->default_tap);
+
+	if (set_dqs_trim)
+		tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim);
 }
 
 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
@@ -933,7 +959,7 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
 
 	tegra_sdhci_parse_pad_autocal_dt(host);
 
-	tegra_sdhci_parse_default_tap_and_trim(host);
+	tegra_sdhci_parse_tap_and_trim(host);
 
 	tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
 							 GPIOD_OUT_HIGH);
-- 
2.7.4

[PATCH v2 3/8] mmc: tegra: Implement HS400 enhanced strobe

[Aapo Vienamo]

Implement eMMC HS400 enhanced strobe. Enhanced strobe is an alternative
mechanism to the HS400 tuning procedure.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
---
 drivers/mmc/host/sdhci-tegra.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 6ec92bc..c0bb0f0 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -43,6 +43,9 @@
 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE		BIT(3)
 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE	BIT(2)
 
+#define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL			0x104
+#define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE		BIT(31)
+
 #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES		0x10c
 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK		0x00003f00
 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT	8
@@ -272,6 +275,23 @@ static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
 	}
 }
 
+static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc,
+					      struct mmc_ios *ios)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	u32 val;
+
+	val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
+
+	if (ios->enhanced_strobe)
+		val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
+	else
+		val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
+
+	sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
+
+}
+
 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
 {
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -950,6 +970,9 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
 				sdhci_tegra_start_signal_voltage_switch;
 	}
 
+	host->mmc_host_ops.hs400_enhanced_strobe =
+			tegra_sdhci_hs400_enhanced_strobe;
+
 	rc = mmc_of_parse(host->mmc);
 	if (rc)
 		goto err_parse_dt;
-- 
2.7.4

[PATCH v2 4/8] mmc: tegra: Implement HS400 delay line calibration

[Aapo Vienamo]

Implement HS400 specific delay line calibration procedure. This is a
Tegra specific procedure and has to be performed regardless whether
enhanced strobe or HS400 tuning is used.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
---
 drivers/mmc/host/sdhci-tegra.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index c0bb0f0..0ae82d3 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -56,6 +56,12 @@
 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300		0x20
 #define SDHCI_MISC_CTRL_ENABLE_DDR50			0x200
 
+#define SDHCI_TEGRA_VENDOR_DLLCAL_CFG			0x1b0
+#define SDHCI_TEGRA_DLLCAL_CALIBRATE			BIT(31)
+
+#define SDHCI_TEGRA_VENDOR_DLLCAL_STA			0x1bc
+#define SDHCI_TEGRA_DLLCAL_STA_ACTIVE			BIT(31)
+
 #define SDHCI_VNDR_TUN_CTRL0_0				0x1c0
 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP			0x20000
 
@@ -587,6 +593,24 @@ static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim)
 	sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES);
 }
 
+static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host)
+{
+	u32 reg;
+	int err;
+
+	reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG);
+	reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE;
+	sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG);
+
+	/* 1 ms sleep, 5 ms timeout */
+	err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA,
+				 reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE),
+				 1000, 5000);
+	if (err)
+		dev_err(mmc_dev(host->mmc),
+			"HS400 delay line calibration timed out\n");
+}
+
 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
 					  unsigned timing)
 {
@@ -594,6 +618,7 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
 	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 	bool set_default_tap = false;
 	bool set_dqs_trim = false;
+	bool do_hs400_dll_cal = false;
 
 	switch (timing) {
 	case MMC_TIMING_UHS_SDR50:
@@ -603,6 +628,7 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
 		break;
 	case MMC_TIMING_MMC_HS400:
 		set_dqs_trim = true;
+		do_hs400_dll_cal = true;
 		break;
 	case MMC_TIMING_MMC_DDR52:
 	case MMC_TIMING_UHS_DDR50:
@@ -623,6 +649,9 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
 
 	if (set_dqs_trim)
 		tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim);
+
+	if (do_hs400_dll_cal)
+		tegra_sdhci_hs400_dll_cal(host);
 }
 
 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
-- 
2.7.4

[PATCH v2 5/8] arm64: dts: tegra186: Add SDMMC4 DQS trim value

[Aapo Vienamo]

Add the HS400 DQS trim value for Tegra186 SDMMC4.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 6e9ef26..9e07bc6 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -313,6 +313,7 @@
 		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
 		nvidia,default-tap = <0x5>;
 		nvidia,default-trim = <0x9>;
+		nvidia,dqs-trim = <63>;
 		status = "disabled";
 	};
 
-- 
2.7.4

[PATCH v2 6/8] arm64: dts: tegra210: Add SDMMC4 DQS trim value

[Aapo Vienamo]

Add the HS400 DQS trim value for Tegra210 SDMMC4.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 14da98a..f8e5f09 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1115,6 +1115,7 @@
 		assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
 				  <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
 		assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
+		nvidia,dqs-trim = <40>;
 		status = "disabled";
 	};
 
-- 
2.7.4

[PATCH v2 7/8] arm64: dts: tegra186: Enable HS400

[Aapo Vienamo]

Enable HS400 signaling on Tegra186 SDMMC4 controller.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 9e07bc6..2f3c8e2 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -314,6 +314,7 @@
 		nvidia,default-tap = <0x5>;
 		nvidia,default-trim = <0x9>;
 		nvidia,dqs-trim = <63>;
+		mmc-hs400-1_8v;
 		status = "disabled";
 	};
 
-- 
2.7.4

[PATCH v2 8/8] arm64: dts: tegra210: Enable HS400

[Aapo Vienamo]

Enable HS400 signaling on Tegra210 SDMMC4 controller.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index f8e5f09..8fe47d6 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1116,6 +1116,7 @@
 				  <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
 		assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
 		nvidia,dqs-trim = <40>;
+		mmc-hs400-1_8v;
 		status = "disabled";
 	};
 
-- 
2.7.4

Re: [PATCH v2 1/8] dt-bindings: mmc: Add DQS trim value to Tegra SDHCI

[Rob Herring]

On Fri, Aug 10, 2018 at 09:13:58PM +0300, Aapo Vienamo wrote:
> Document HS400 DQS trim value device tree property.
> 
> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
> ---
>  Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 4 ++++
>  1 file changed, 4 insertions(+)

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 0/8] Tegra SDHCI support HS400 on Tegra210 and Tegra186

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 2160 bytes --]

On Fri, Aug 10, 2018 at 09:13:57PM +0300, Aapo Vienamo wrote:
> Hi all,
> This series implements support for HS400 signaling on Tegra210 and
> Tegra186. This includes programming the DQS trimmer values, implementing
> enhanced strobe and HS400 delay line calibration.
> 
> This series depends on the "Tegra SDHCI add support for HS200 and UHS
> signaling" series.
> 
> Changelog:
> v2:
> 	- Document in dt-bindings which controllers support HS400
> 	- Use val instead of reg in tegra_sdhci_set_dqs_trim()
> 	- Change "dt" to "DT" in "mmc: tegra: Parse and program DQS trim
> 	  value" commit message
> 	- Add spaces around << in tegra_sdhci_set_dqs_trim()
> 	- Make the "mmc: tegra: Implement HS400 enhanced strobe" commit
> 	  message more detailed
> 	- Remove a debug print from tegra_sdhci_hs400_enhanced_strobe()
> 	- Add blank lines around if-else-block in
> 	  tegra_sdhci_hs400_enhanced_strobe()
> 	- Use val instead of reg in tegra_sdhci_hs400_enhanced_strobe()
> 	- Make commit message of "mmc: tegra: Implement HS400 delay line
> 	  calibration" more detailed
> 
> Aapo Vienamo (8):
>   dt-bindings: mmc: Add DQS trim value to Tegra SDHCI
>   mmc: tegra: Parse and program DQS trim value
>   mmc: tegra: Implement HS400 enhanced strobe
>   mmc: tegra: Implement HS400 delay line calibration
>   arm64: dts: tegra186: Add SDMMC4 DQS trim value
>   arm64: dts: tegra210: Add SDMMC4 DQS trim value
>   arm64: dts: tegra186: Enable HS400
>   arm64: dts: tegra210: Enable HS400
> 
>  .../bindings/mmc/nvidia,tegra20-sdhci.txt          |  4 ++
>  arch/arm64/boot/dts/nvidia/tegra186.dtsi           |  2 +
>  arch/arm64/boot/dts/nvidia/tegra210.dtsi           |  2 +
>  drivers/mmc/host/sdhci-tegra.c                     | 84 +++++++++++++++++++++-
>  4 files changed, 89 insertions(+), 3 deletions(-)

Ulf, Adrian,

Aapo just reminded me of this small series that also has a dependency on
the UHS signalling series posted earlier. I think it's easiest if I just
stash this on top of the existing branch that I have and send this along
with the rest as part of a pull request early after v4.19-rc1.

Thierry

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH v2 0/8] Tegra SDHCI support HS400 on Tegra210 and Tegra186

[Ulf Hansson]

On 24 August 2018 at 11:11, Thierry Reding <thierry.reding@gmail.com> wrote:
> On Fri, Aug 10, 2018 at 09:13:57PM +0300, Aapo Vienamo wrote:
>> Hi all,
>> This series implements support for HS400 signaling on Tegra210 and
>> Tegra186. This includes programming the DQS trimmer values, implementing
>> enhanced strobe and HS400 delay line calibration.
>>
>> This series depends on the "Tegra SDHCI add support for HS200 and UHS
>> signaling" series.
>>
>> Changelog:
>> v2:
>>       - Document in dt-bindings which controllers support HS400
>>       - Use val instead of reg in tegra_sdhci_set_dqs_trim()
>>       - Change "dt" to "DT" in "mmc: tegra: Parse and program DQS trim
>>         value" commit message
>>       - Add spaces around << in tegra_sdhci_set_dqs_trim()
>>       - Make the "mmc: tegra: Implement HS400 enhanced strobe" commit
>>         message more detailed
>>       - Remove a debug print from tegra_sdhci_hs400_enhanced_strobe()
>>       - Add blank lines around if-else-block in
>>         tegra_sdhci_hs400_enhanced_strobe()
>>       - Use val instead of reg in tegra_sdhci_hs400_enhanced_strobe()
>>       - Make commit message of "mmc: tegra: Implement HS400 delay line
>>         calibration" more detailed
>>
>> Aapo Vienamo (8):
>>   dt-bindings: mmc: Add DQS trim value to Tegra SDHCI
>>   mmc: tegra: Parse and program DQS trim value
>>   mmc: tegra: Implement HS400 enhanced strobe
>>   mmc: tegra: Implement HS400 delay line calibration
>>   arm64: dts: tegra186: Add SDMMC4 DQS trim value
>>   arm64: dts: tegra210: Add SDMMC4 DQS trim value
>>   arm64: dts: tegra186: Enable HS400
>>   arm64: dts: tegra210: Enable HS400
>>
>>  .../bindings/mmc/nvidia,tegra20-sdhci.txt          |  4 ++
>>  arch/arm64/boot/dts/nvidia/tegra186.dtsi           |  2 +
>>  arch/arm64/boot/dts/nvidia/tegra210.dtsi           |  2 +
>>  drivers/mmc/host/sdhci-tegra.c                     | 84 +++++++++++++++++++++-
>>  4 files changed, 89 insertions(+), 3 deletions(-)
>
> Ulf, Adrian,
>
> Aapo just reminded me of this small series that also has a dependency on
> the UHS signalling series posted earlier. I think it's easiest if I just
> stash this on top of the existing branch that I have and send this along
> with the rest as part of a pull request early after v4.19-rc1.

Yep, that would be convenient for me.

Although, we first need some input from Adrian.

Kind regards
Uffe

Re: [PATCH v2 0/8] Tegra SDHCI support HS400 on Tegra210 and Tegra186

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 2064 bytes --]

On Fri, Aug 10, 2018 at 09:13:57PM +0300, Aapo Vienamo wrote:
> Hi all,
> This series implements support for HS400 signaling on Tegra210 and
> Tegra186. This includes programming the DQS trimmer values, implementing
> enhanced strobe and HS400 delay line calibration.
> 
> This series depends on the "Tegra SDHCI add support for HS200 and UHS
> signaling" series.
> 
> Changelog:
> v2:
> 	- Document in dt-bindings which controllers support HS400
> 	- Use val instead of reg in tegra_sdhci_set_dqs_trim()
> 	- Change "dt" to "DT" in "mmc: tegra: Parse and program DQS trim
> 	  value" commit message
> 	- Add spaces around << in tegra_sdhci_set_dqs_trim()
> 	- Make the "mmc: tegra: Implement HS400 enhanced strobe" commit
> 	  message more detailed
> 	- Remove a debug print from tegra_sdhci_hs400_enhanced_strobe()
> 	- Add blank lines around if-else-block in
> 	  tegra_sdhci_hs400_enhanced_strobe()
> 	- Use val instead of reg in tegra_sdhci_hs400_enhanced_strobe()
> 	- Make commit message of "mmc: tegra: Implement HS400 delay line
> 	  calibration" more detailed
> 
> Aapo Vienamo (8):
>   dt-bindings: mmc: Add DQS trim value to Tegra SDHCI
>   mmc: tegra: Parse and program DQS trim value
>   mmc: tegra: Implement HS400 enhanced strobe
>   mmc: tegra: Implement HS400 delay line calibration
>   arm64: dts: tegra186: Add SDMMC4 DQS trim value
>   arm64: dts: tegra210: Add SDMMC4 DQS trim value
>   arm64: dts: tegra186: Enable HS400
>   arm64: dts: tegra210: Enable HS400
> 
>  .../bindings/mmc/nvidia,tegra20-sdhci.txt          |  4 ++
>  arch/arm64/boot/dts/nvidia/tegra186.dtsi           |  2 +
>  arch/arm64/boot/dts/nvidia/tegra210.dtsi           |  2 +
>  drivers/mmc/host/sdhci-tegra.c                     | 84 +++++++++++++++++++++-
>  4 files changed, 89 insertions(+), 3 deletions(-)

Adrian,

any chance you could take a brief look at these? They are a prerequisite
for the 2-patch series ("[PATCH 0/2] Tegra SDHCI rerun pad calibration
periodically") that you already acked.

Thanks,
Thierry

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH v2 0/8] Tegra SDHCI support HS400 on Tegra210 and Tegra186

[Adrian Hunter]

On 27/08/18 13:08, Thierry Reding wrote:
> On Fri, Aug 10, 2018 at 09:13:57PM +0300, Aapo Vienamo wrote:
>> Hi all,
>> This series implements support for HS400 signaling on Tegra210 and
>> Tegra186. This includes programming the DQS trimmer values, implementing
>> enhanced strobe and HS400 delay line calibration.
>>
>> This series depends on the "Tegra SDHCI add support for HS200 and UHS
>> signaling" series.
>>
>> Changelog:
>> v2:
>> 	- Document in dt-bindings which controllers support HS400
>> 	- Use val instead of reg in tegra_sdhci_set_dqs_trim()
>> 	- Change "dt" to "DT" in "mmc: tegra: Parse and program DQS trim
>> 	  value" commit message
>> 	- Add spaces around << in tegra_sdhci_set_dqs_trim()
>> 	- Make the "mmc: tegra: Implement HS400 enhanced strobe" commit
>> 	  message more detailed
>> 	- Remove a debug print from tegra_sdhci_hs400_enhanced_strobe()
>> 	- Add blank lines around if-else-block in
>> 	  tegra_sdhci_hs400_enhanced_strobe()
>> 	- Use val instead of reg in tegra_sdhci_hs400_enhanced_strobe()
>> 	- Make commit message of "mmc: tegra: Implement HS400 delay line
>> 	  calibration" more detailed
>>
>> Aapo Vienamo (8):
>>   dt-bindings: mmc: Add DQS trim value to Tegra SDHCI
>>   mmc: tegra: Parse and program DQS trim value
>>   mmc: tegra: Implement HS400 enhanced strobe
>>   mmc: tegra: Implement HS400 delay line calibration
>>   arm64: dts: tegra186: Add SDMMC4 DQS trim value
>>   arm64: dts: tegra210: Add SDMMC4 DQS trim value
>>   arm64: dts: tegra186: Enable HS400
>>   arm64: dts: tegra210: Enable HS400
>>
>>  .../bindings/mmc/nvidia,tegra20-sdhci.txt          |  4 ++
>>  arch/arm64/boot/dts/nvidia/tegra186.dtsi           |  2 +
>>  arch/arm64/boot/dts/nvidia/tegra210.dtsi           |  2 +
>>  drivers/mmc/host/sdhci-tegra.c                     | 84 +++++++++++++++++++++-
>>  4 files changed, 89 insertions(+), 3 deletions(-)
> 
> Adrian,
> 
> any chance you could take a brief look at these? They are a prerequisite
> for the 2-patch series ("[PATCH 0/2] Tegra SDHCI rerun pad calibration
> periodically") that you already acked.

Sure, I'll try and have a look today.

Re: [PATCH v2 0/8] Tegra SDHCI support HS400 on Tegra210 and Tegra186

[Adrian Hunter]

On 27/08/18 13:26, Adrian Hunter wrote:
> On 27/08/18 13:08, Thierry Reding wrote:
>> On Fri, Aug 10, 2018 at 09:13:57PM +0300, Aapo Vienamo wrote:
>>> Hi all,
>>> This series implements support for HS400 signaling on Tegra210 and
>>> Tegra186. This includes programming the DQS trimmer values, implementing
>>> enhanced strobe and HS400 delay line calibration.
>>>
>>> This series depends on the "Tegra SDHCI add support for HS200 and UHS
>>> signaling" series.
>>>
>>> Changelog:
>>> v2:
>>> 	- Document in dt-bindings which controllers support HS400
>>> 	- Use val instead of reg in tegra_sdhci_set_dqs_trim()
>>> 	- Change "dt" to "DT" in "mmc: tegra: Parse and program DQS trim
>>> 	  value" commit message
>>> 	- Add spaces around << in tegra_sdhci_set_dqs_trim()
>>> 	- Make the "mmc: tegra: Implement HS400 enhanced strobe" commit
>>> 	  message more detailed
>>> 	- Remove a debug print from tegra_sdhci_hs400_enhanced_strobe()
>>> 	- Add blank lines around if-else-block in
>>> 	  tegra_sdhci_hs400_enhanced_strobe()
>>> 	- Use val instead of reg in tegra_sdhci_hs400_enhanced_strobe()
>>> 	- Make commit message of "mmc: tegra: Implement HS400 delay line
>>> 	  calibration" more detailed
>>>
>>> Aapo Vienamo (8):
>>>   dt-bindings: mmc: Add DQS trim value to Tegra SDHCI
>>>   mmc: tegra: Parse and program DQS trim value
>>>   mmc: tegra: Implement HS400 enhanced strobe
>>>   mmc: tegra: Implement HS400 delay line calibration
>>>   arm64: dts: tegra186: Add SDMMC4 DQS trim value
>>>   arm64: dts: tegra210: Add SDMMC4 DQS trim value
>>>   arm64: dts: tegra186: Enable HS400
>>>   arm64: dts: tegra210: Enable HS400
>>>
>>>  .../bindings/mmc/nvidia,tegra20-sdhci.txt          |  4 ++
>>>  arch/arm64/boot/dts/nvidia/tegra186.dtsi           |  2 +
>>>  arch/arm64/boot/dts/nvidia/tegra210.dtsi           |  2 +
>>>  drivers/mmc/host/sdhci-tegra.c                     | 84 +++++++++++++++++++++-
>>>  4 files changed, 89 insertions(+), 3 deletions(-)
>>
>> Adrian,
>>
>> any chance you could take a brief look at these? They are a prerequisite
>> for the 2-patch series ("[PATCH 0/2] Tegra SDHCI rerun pad calibration
>> periodically") that you already acked.
> 
> Sure, I'll try and have a look today.
> 

These are fine. For the sdhci-tegra patches (patches 2 - 4):

	Acked-by: Adrian Hunter <adrian.hunter@intel.com>

Re: [PATCH v2 0/8] Tegra SDHCI support HS400 on Tegra210 and Tegra186

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1914 bytes --]

On Fri, Aug 10, 2018 at 09:13:57PM +0300, Aapo Vienamo wrote:
> Hi all,
> This series implements support for HS400 signaling on Tegra210 and
> Tegra186. This includes programming the DQS trimmer values, implementing
> enhanced strobe and HS400 delay line calibration.
> 
> This series depends on the "Tegra SDHCI add support for HS200 and UHS
> signaling" series.
> 
> Changelog:
> v2:
> 	- Document in dt-bindings which controllers support HS400
> 	- Use val instead of reg in tegra_sdhci_set_dqs_trim()
> 	- Change "dt" to "DT" in "mmc: tegra: Parse and program DQS trim
> 	  value" commit message
> 	- Add spaces around << in tegra_sdhci_set_dqs_trim()
> 	- Make the "mmc: tegra: Implement HS400 enhanced strobe" commit
> 	  message more detailed
> 	- Remove a debug print from tegra_sdhci_hs400_enhanced_strobe()
> 	- Add blank lines around if-else-block in
> 	  tegra_sdhci_hs400_enhanced_strobe()
> 	- Use val instead of reg in tegra_sdhci_hs400_enhanced_strobe()
> 	- Make commit message of "mmc: tegra: Implement HS400 delay line
> 	  calibration" more detailed
> 
> Aapo Vienamo (8):
>   dt-bindings: mmc: Add DQS trim value to Tegra SDHCI
>   mmc: tegra: Parse and program DQS trim value
>   mmc: tegra: Implement HS400 enhanced strobe
>   mmc: tegra: Implement HS400 delay line calibration
>   arm64: dts: tegra186: Add SDMMC4 DQS trim value
>   arm64: dts: tegra210: Add SDMMC4 DQS trim value
>   arm64: dts: tegra186: Enable HS400
>   arm64: dts: tegra210: Enable HS400
> 
>  .../bindings/mmc/nvidia,tegra20-sdhci.txt          |  4 ++
>  arch/arm64/boot/dts/nvidia/tegra186.dtsi           |  2 +
>  arch/arm64/boot/dts/nvidia/tegra210.dtsi           |  2 +
>  drivers/mmc/host/sdhci-tegra.c                     | 84 +++++++++++++++++++++-
>  4 files changed, 89 insertions(+), 3 deletions(-)

For patches 1-4:

Acked-by: Thierry Reding <treding@nvidia.com>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH v2 0/8] Tegra SDHCI support HS400 on Tegra210 and Tegra186

[Ulf Hansson]

On 10 August 2018 at 20:13, Aapo Vienamo <avienamo@nvidia.com> wrote:
> Hi all,
> This series implements support for HS400 signaling on Tegra210 and
> Tegra186. This includes programming the DQS trimmer values, implementing
> enhanced strobe and HS400 delay line calibration.
>
> This series depends on the "Tegra SDHCI add support for HS200 and UHS
> signaling" series.
>
> Changelog:
> v2:
>         - Document in dt-bindings which controllers support HS400
>         - Use val instead of reg in tegra_sdhci_set_dqs_trim()
>         - Change "dt" to "DT" in "mmc: tegra: Parse and program DQS trim
>           value" commit message
>         - Add spaces around << in tegra_sdhci_set_dqs_trim()
>         - Make the "mmc: tegra: Implement HS400 enhanced strobe" commit
>           message more detailed
>         - Remove a debug print from tegra_sdhci_hs400_enhanced_strobe()
>         - Add blank lines around if-else-block in
>           tegra_sdhci_hs400_enhanced_strobe()
>         - Use val instead of reg in tegra_sdhci_hs400_enhanced_strobe()
>         - Make commit message of "mmc: tegra: Implement HS400 delay line
>           calibration" more detailed
>
> Aapo Vienamo (8):
>   dt-bindings: mmc: Add DQS trim value to Tegra SDHCI
>   mmc: tegra: Parse and program DQS trim value
>   mmc: tegra: Implement HS400 enhanced strobe
>   mmc: tegra: Implement HS400 delay line calibration
>   arm64: dts: tegra186: Add SDMMC4 DQS trim value
>   arm64: dts: tegra210: Add SDMMC4 DQS trim value
>   arm64: dts: tegra186: Enable HS400
>   arm64: dts: tegra210: Enable HS400
>
>  .../bindings/mmc/nvidia,tegra20-sdhci.txt          |  4 ++
>  arch/arm64/boot/dts/nvidia/tegra186.dtsi           |  2 +
>  arch/arm64/boot/dts/nvidia/tegra210.dtsi           |  2 +
>  drivers/mmc/host/sdhci-tegra.c                     | 84 +++++++++++++++++++++-
>  4 files changed, 89 insertions(+), 3 deletions(-)
>
> --
> 2.7.4
>

Applied patch 1->4 for next, thanks!

Kind regards
Uffe