From: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
To: robh@kernel.org, mchehab@kernel.org, linux-edac@vger.kernel.org,
linux-kernel@vger.kernel.org, Andy Gross <andy.gross@linaro.org>,
David Brown <david.brown@linaro.org>,
linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
robh+dt@kernel.org, mark.rutland@arm.com,
devicetree@vger.kernel.org, tsoni@codeaurora.org,
ckadabi@codeaurora.org, rishabhb@codeaurora.org, bp@alien8.de,
evgreen@chromium.org
Cc: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Subject: [PATCH v2 4/4] dt-bindigs: msm: Update documentation of qcom,llcc
Date: Fri, 17 Aug 2018 17:08:35 -0700 [thread overview]
Message-ID: <1534550915-18230-5-git-send-email-vnkgutta@codeaurora.org> (raw)
In-Reply-To: <1534550915-18230-1-git-send-email-vnkgutta@codeaurora.org>
Add reg-names and interrupts for LLCC documentation and the usage
examples. llcc broadcast base is added in addition to llcc base,
which is used for llcc broadcast writes.
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
---
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
index 5e85749..b4b1c86 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
@@ -18,9 +18,22 @@ Properties:
Value Type: <prop-encoded-array>
Definition: Start address and the the size of the register region.
+- reg-names:
+ Usage: required
+ Value Type: <stringlist>
+ Definition: Register region names. Must be "llcc_base", "llcc_bcast_base".
+
+- interrupts:
+ Usage: required
+ Definition: The interrupt is associated with the llcc edac device.
+ It's used for llcc cache single and double bit error detection
+ and reporting.
+
Example:
cache-controller@1100000 {
compatible = "qcom,sdm845-llcc";
- reg = <0x1100000 0x250000>;
+ reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
+ reg-names = "llcc_base", "llcc_bcast_base";
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2018-08-18 0:08 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-18 0:08 [PATCH v2 0/4] Add EDAC driver for QCOM SoCs Venkata Narendra Kumar Gutta
2018-08-18 0:08 ` [PATCH v2 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC) Venkata Narendra Kumar Gutta
2018-08-23 23:01 ` Evan Green
2018-08-24 17:58 ` vnkgutta
2018-08-18 0:08 ` [PATCH v2 2/4] drivers: soc: Add support to register LLCC EDAC driver Venkata Narendra Kumar Gutta
2018-08-23 23:01 ` Evan Green
2018-08-24 17:57 ` vnkgutta
2018-08-18 0:08 ` [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs Venkata Narendra Kumar Gutta
2018-08-23 23:04 ` Evan Green
2018-08-23 23:07 ` Evan Green
2018-08-24 18:38 ` vnkgutta
2018-08-24 18:32 ` vnkgutta
2018-08-24 20:18 ` Evan Green
2018-08-24 21:05 ` vnkgutta
2018-08-24 16:11 ` Stephen Boyd
2018-08-24 19:47 ` vnkgutta
2018-08-18 0:08 ` Venkata Narendra Kumar Gutta [this message]
2018-08-20 19:53 ` [PATCH v2 4/4] dt-bindigs: msm: Update documentation of qcom,llcc Rob Herring
2018-08-22 21:46 ` vnkgutta
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