* [PATCH v3 0/4] phy: socionext: add new UniPhier USB PHY driver support
@ 2018-08-22 3:50 Kunihiko Hayashi
2018-08-22 3:50 ` [PATCH v3 1/4] dt-bindings: phy: add DT bindings for UniPhier USB3 PHY driver Kunihiko Hayashi
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Kunihiko Hayashi @ 2018-08-22 3:50 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Rob Herring, Mark Rutland, Masahiro Yamada
Cc: linux-arm-kernel, linux-kernel, devicetree, Masami Hiramatsu,
Jassi Brar, Kunihiko Hayashi
This series adds support for PHY interface built into USB controller
implemented in Socionext UniPhier SoCs.
The USB3 PHY driver supports High-Speed PHY and Super-Speed PHY included in
the USB3 glue layer, and the USB2 PHY driver supports High-Speed PHY
integrated into system controller.
Changes since v2:
- rewrite a header with style that other phy drivers use
- replace return value of probe functions with PTR_ERR_OR_ZERO()
- fix typo of register offset macros
Changes since v1:
- rewrite a header with C++ comment style
- dt-bindings: separate a document for ssphy and hsphy
- dt-bindings: sort clock-names and reset-names to begin with "phy"
- dt-bindings: use vbus-supply instead of phy-supply, because vbus isn't
for phy, but vbus is tied to the port that corresponds to each phy [1]
- stop using phy_power and add own .power_on and .power_off functions
to control clk/reset for phy and vbus regulator
- separate clk_get() and reset_control_get() for each clk/reset
and remove arrays of clock_names and reset_names
- remove phy-parameters that are the same as power-on values
- remove functions to set phy-parameters for legacy SoCs
- express phy-parameters by using macros including the number of
the register and its bitfield (msb and lsb)
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-July/593279.html
Kunihiko Hayashi (4):
dt-bindings: phy: add DT bindings for UniPhier USB3 PHY driver
phy: socionext: add USB3 PHY driver for UniPhier SoC
dt-bindings: phy: add DT bindings for UniPhier USB2 PHY driver
phy: socionext: add USB2 PHY driver for UniPhier SoC
.../devicetree/bindings/phy/uniphier-usb2-phy.txt | 45 +++
.../bindings/phy/uniphier-usb3-hsphy.txt | 69 ++++
.../bindings/phy/uniphier-usb3-ssphy.txt | 57 +++
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/socionext/Kconfig | 25 ++
drivers/phy/socionext/Makefile | 7 +
drivers/phy/socionext/phy-uniphier-usb2.c | 244 ++++++++++++
drivers/phy/socionext/phy-uniphier-usb3hs.c | 422 +++++++++++++++++++++
drivers/phy/socionext/phy-uniphier-usb3ss.c | 349 +++++++++++++++++
10 files changed, 1220 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/uniphier-usb2-phy.txt
create mode 100644 Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt
create mode 100644 Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt
create mode 100644 drivers/phy/socionext/Kconfig
create mode 100644 drivers/phy/socionext/Makefile
create mode 100644 drivers/phy/socionext/phy-uniphier-usb2.c
create mode 100644 drivers/phy/socionext/phy-uniphier-usb3hs.c
create mode 100644 drivers/phy/socionext/phy-uniphier-usb3ss.c
--
2.7.4
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3 1/4] dt-bindings: phy: add DT bindings for UniPhier USB3 PHY driver
2018-08-22 3:50 [PATCH v3 0/4] phy: socionext: add new UniPhier USB PHY driver support Kunihiko Hayashi
@ 2018-08-22 3:50 ` Kunihiko Hayashi
2018-08-22 3:50 ` [PATCH v3 2/4] phy: socionext: add USB3 PHY driver for UniPhier SoC Kunihiko Hayashi
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Kunihiko Hayashi @ 2018-08-22 3:50 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Rob Herring, Mark Rutland, Masahiro Yamada
Cc: linux-arm-kernel, linux-kernel, devicetree, Masami Hiramatsu,
Jassi Brar, Kunihiko Hayashi
Add DT bindings for PHY interface built into USB3 controller
implemented in UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
.../bindings/phy/uniphier-usb3-hsphy.txt | 69 ++++++++++++++++++++++
.../bindings/phy/uniphier-usb3-ssphy.txt | 57 ++++++++++++++++++
2 files changed, 126 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt
create mode 100644 Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt
diff --git a/Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt b/Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt
new file mode 100644
index 0000000..e8d8086
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt
@@ -0,0 +1,69 @@
+Socionext UniPhier USB3 High-Speed (HS) PHY
+
+This describes the devicetree bindings for PHY interfaces built into
+USB3 controller implemented on Socionext UniPhier SoCs.
+Although the controller includes High-Speed PHY and Super-Speed PHY,
+this describes about High-Speed PHY.
+
+Required properties:
+- compatible: Should contain one of the following:
+ "socionext,uniphier-pro4-usb3-hsphy" - for Pro4 SoC
+ "socionext,uniphier-pxs2-usb3-hsphy" - for PXs2 SoC
+ "socionext,uniphier-ld20-usb3-hsphy" - for LD20 SoC
+ "socionext,uniphier-pxs3-usb3-hsphy" - for PXs3 SoC
+- reg: Specifies offset and length of the register set for the device.
+- #phy-cells: Should be 0.
+- clocks: A list of phandles to the clock gate for USB3 glue layer.
+ According to the clock-names, appropriate clocks are required.
+- clock-names: Should contain the following:
+ "gio", "link" - for Pro4 SoC
+ "phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional.
+ "phy", "link" - for others
+- resets: A list of phandles to the reset control for USB3 glue layer.
+ According to the reset-names, appropriate resets are required.
+- reset-names: Should contain the following:
+ "gio", "link" - for Pro4 SoC
+ "phy", "link" - for others
+
+Optional properties:
+- vbus-supply: A phandle to the regulator for USB VBUS.
+- nvmem-cells: Phandles to nvmem cell that contains the trimming data.
+ Available only for HS-PHY implemented on LD20 and PXs3, and
+ if unspecified, default value is used.
+- nvmem-cell-names: Should be the following names, which correspond to
+ each nvmem-cells.
+ All of the 3 parameters associated with the following names are
+ required for each port, if any one is omitted, the trimming data
+ of the port will not be set at all.
+ "rterm", "sel_t", "hs_i" - Each cell name for phy parameters
+
+Refer to phy/phy-bindings.txt for the generic PHY binding properties.
+
+Example:
+
+ usb-glue@65b00000 {
+ compatible = "socionext,uniphier-ld20-dwc3-glue",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65b00000 0x400>;
+
+ usb_vbus0: regulator {
+ ...
+ };
+
+ usb_hsphy0: hs-phy@200 {
+ compatible = "socionext,uniphier-ld20-usb3-hsphy";
+ reg = <0x200 0x10>;
+ #phy-cells = <0>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 14>, <&sys_clk 16>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 14>, <&sys_rst 16>;
+ vbus-supply = <&usb_vbus0>;
+ nvmem-cell-names = "rterm", "sel_t", "hs_i";
+ nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
+ <&usb_hs_i0>;
+ };
+ ...
+ };
diff --git a/Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt b/Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt
new file mode 100644
index 0000000..490b815
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt
@@ -0,0 +1,57 @@
+Socionext UniPhier USB3 Super-Speed (SS) PHY
+
+This describes the devicetree bindings for PHY interfaces built into
+USB3 controller implemented on Socionext UniPhier SoCs.
+Although the controller includes High-Speed PHY and Super-Speed PHY,
+this describes about Super-Speed PHY.
+
+Required properties:
+- compatible: Should contain one of the following:
+ "socionext,uniphier-pro4-usb3-ssphy" - for Pro4 SoC
+ "socionext,uniphier-pxs2-usb3-ssphy" - for PXs2 SoC
+ "socionext,uniphier-ld20-usb3-ssphy" - for LD20 SoC
+ "socionext,uniphier-pxs3-usb3-ssphy" - for PXs3 SoC
+- reg: Specifies offset and length of the register set for the device.
+- #phy-cells: Should be 0.
+- clocks: A list of phandles to the clock gate for USB3 glue layer.
+ According to the clock-names, appropriate clocks are required.
+- clock-names:
+ "gio", "link" - for Pro4 SoC
+ "phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional.
+ "phy", "link" - for others
+- resets: A list of phandles to the reset control for USB3 glue layer.
+ According to the reset-names, appropriate resets are required.
+- reset-names:
+ "gio", "link" - for Pro4 SoC
+ "phy", "link" - for others
+
+Optional properties:
+- vbus-supply: A phandle to the regulator for USB VBUS.
+
+Refer to phy/phy-bindings.txt for the generic PHY binding properties.
+
+Example:
+
+ usb-glue@65b00000 {
+ compatible = "socionext,uniphier-ld20-dwc3-glue",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65b00000 0x400>;
+
+ usb_vbus0: regulator {
+ ...
+ };
+
+ usb_ssphy0: ss-phy@300 {
+ compatible = "socionext,uniphier-ld20-usb3-ssphy";
+ reg = <0x300 0x10>;
+ #phy-cells = <0>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 14>, <&sys_clk 16>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 14>, <&sys_rst 16>;
+ vbus-supply = <&usb_vbus0>;
+ };
+ ...
+ };
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v3 2/4] phy: socionext: add USB3 PHY driver for UniPhier SoC
2018-08-22 3:50 [PATCH v3 0/4] phy: socionext: add new UniPhier USB PHY driver support Kunihiko Hayashi
2018-08-22 3:50 ` [PATCH v3 1/4] dt-bindings: phy: add DT bindings for UniPhier USB3 PHY driver Kunihiko Hayashi
@ 2018-08-22 3:50 ` Kunihiko Hayashi
2018-08-22 3:50 ` [PATCH v3 3/4] dt-bindings: phy: add DT bindings for UniPhier USB2 PHY driver Kunihiko Hayashi
2018-08-22 3:50 ` [PATCH v3 4/4] phy: socionext: add USB2 PHY driver for UniPhier SoC Kunihiko Hayashi
3 siblings, 0 replies; 5+ messages in thread
From: Kunihiko Hayashi @ 2018-08-22 3:50 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Rob Herring, Mark Rutland, Masahiro Yamada
Cc: linux-arm-kernel, linux-kernel, devicetree, Masami Hiramatsu,
Jassi Brar, Kunihiko Hayashi
Add a driver for PHY interface built into USB3 controller
implemented in UniPhier SoCs.
This driver supports High-Speed PHY and Super-Speed PHY.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Motoya Tanigawa <tanigawa.motoya@socionext.com>
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
---
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/socionext/Kconfig | 12 +
drivers/phy/socionext/Makefile | 6 +
drivers/phy/socionext/phy-uniphier-usb3hs.c | 422 ++++++++++++++++++++++++++++
drivers/phy/socionext/phy-uniphier-usb3ss.c | 349 +++++++++++++++++++++++
6 files changed, 791 insertions(+)
create mode 100644 drivers/phy/socionext/Kconfig
create mode 100644 drivers/phy/socionext/Makefile
create mode 100644 drivers/phy/socionext/phy-uniphier-usb3hs.c
create mode 100644 drivers/phy/socionext/phy-uniphier-usb3ss.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5c8d452..b752589 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -53,6 +53,7 @@ source "drivers/phy/ralink/Kconfig"
source "drivers/phy/renesas/Kconfig"
source "drivers/phy/rockchip/Kconfig"
source "drivers/phy/samsung/Kconfig"
+source "drivers/phy/socionext/Kconfig"
source "drivers/phy/st/Kconfig"
source "drivers/phy/tegra/Kconfig"
source "drivers/phy/ti/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 84e3bd9..5539cde 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -21,5 +21,6 @@ obj-y += broadcom/ \
qualcomm/ \
ralink/ \
samsung/ \
+ socionext/ \
st/ \
ti/
diff --git a/drivers/phy/socionext/Kconfig b/drivers/phy/socionext/Kconfig
new file mode 100644
index 0000000..4a172fc
--- /dev/null
+++ b/drivers/phy/socionext/Kconfig
@@ -0,0 +1,12 @@
+#
+# PHY drivers for Socionext platforms.
+#
+
+config PHY_UNIPHIER_USB3
+ tristate "UniPhier USB3 PHY driver"
+ depends on ARCH_UNIPHIER || COMPILE_TEST
+ depends on OF && HAS_IOMEM
+ select GENERIC_PHY
+ help
+ Enable this to support USB PHY implemented in USB3 controller
+ on UniPhier SoCs. This controller supports USB3.0 and lower speed.
diff --git a/drivers/phy/socionext/Makefile b/drivers/phy/socionext/Makefile
new file mode 100644
index 0000000..e230fa31
--- /dev/null
+++ b/drivers/phy/socionext/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the phy drivers.
+#
+
+obj-$(CONFIG_PHY_UNIPHIER_USB3) += phy-uniphier-usb3hs.o phy-uniphier-usb3ss.o
diff --git a/drivers/phy/socionext/phy-uniphier-usb3hs.c b/drivers/phy/socionext/phy-uniphier-usb3hs.c
new file mode 100644
index 0000000..b1b048b
--- /dev/null
+++ b/drivers/phy/socionext/phy-uniphier-usb3hs.c
@@ -0,0 +1,422 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * phy-uniphier-usb3hs.c - HS-PHY driver for Socionext UniPhier USB3 controller
+ * Copyright 2015-2018 Socionext Inc.
+ * Author:
+ * Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+ * Contributors:
+ * Motoya Tanigawa <tanigawa.motoya@socionext.com>
+ * Masami Hiramatsu <masami.hiramatsu@linaro.org>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+#define HSPHY_CFG0 0x0
+#define HSPHY_CFG0_HS_I_MASK GENMASK(31, 28)
+#define HSPHY_CFG0_HSDISC_MASK GENMASK(27, 26)
+#define HSPHY_CFG0_SWING_MASK GENMASK(17, 16)
+#define HSPHY_CFG0_SEL_T_MASK GENMASK(15, 12)
+#define HSPHY_CFG0_RTERM_MASK GENMASK(7, 6)
+#define HSPHY_CFG0_TRIMMASK (HSPHY_CFG0_HS_I_MASK \
+ | HSPHY_CFG0_SEL_T_MASK \
+ | HSPHY_CFG0_RTERM_MASK)
+
+#define HSPHY_CFG1 0x4
+#define HSPHY_CFG1_DAT_EN BIT(29)
+#define HSPHY_CFG1_ADR_EN BIT(28)
+#define HSPHY_CFG1_ADR_MASK GENMASK(27, 16)
+#define HSPHY_CFG1_DAT_MASK GENMASK(23, 16)
+
+#define PHY_F(regno, msb, lsb) { (regno), (msb), (lsb) }
+
+#define LS_SLEW PHY_F(10, 6, 6) /* LS mode slew rate */
+#define FS_LS_DRV PHY_F(10, 5, 5) /* FS/LS slew rate */
+
+#define MAX_PHY_PARAMS 2
+
+struct uniphier_u3hsphy_param {
+ struct {
+ int reg_no;
+ int msb;
+ int lsb;
+ } field;
+ u8 value;
+};
+
+struct uniphier_u3hsphy_trim_param {
+ unsigned int rterm;
+ unsigned int sel_t;
+ unsigned int hs_i;
+};
+
+#define trim_param_is_valid(p) ((p)->rterm || (p)->sel_t || (p)->hs_i)
+
+struct uniphier_u3hsphy_priv {
+ struct device *dev;
+ void __iomem *base;
+ struct clk *clk, *clk_parent, *clk_ext;
+ struct reset_control *rst, *rst_parent;
+ struct regulator *vbus;
+ const struct uniphier_u3hsphy_soc_data *data;
+};
+
+struct uniphier_u3hsphy_soc_data {
+ int nparams;
+ const struct uniphier_u3hsphy_param param[MAX_PHY_PARAMS];
+ u32 config0;
+ u32 config1;
+ void (*trim_func)(struct uniphier_u3hsphy_priv *priv, u32 *pconfig,
+ struct uniphier_u3hsphy_trim_param *pt);
+};
+
+static void uniphier_u3hsphy_trim_ld20(struct uniphier_u3hsphy_priv *priv,
+ u32 *pconfig,
+ struct uniphier_u3hsphy_trim_param *pt)
+{
+ *pconfig &= ~HSPHY_CFG0_RTERM_MASK;
+ *pconfig |= FIELD_PREP(HSPHY_CFG0_RTERM_MASK, pt->rterm);
+
+ *pconfig &= ~HSPHY_CFG0_SEL_T_MASK;
+ *pconfig |= FIELD_PREP(HSPHY_CFG0_SEL_T_MASK, pt->sel_t);
+
+ *pconfig &= ~HSPHY_CFG0_HS_I_MASK;
+ *pconfig |= FIELD_PREP(HSPHY_CFG0_HS_I_MASK, pt->hs_i);
+}
+
+static int uniphier_u3hsphy_get_nvparam(struct uniphier_u3hsphy_priv *priv,
+ const char *name, unsigned int *val)
+{
+ struct nvmem_cell *cell;
+ u8 *buf;
+
+ cell = devm_nvmem_cell_get(priv->dev, name);
+ if (IS_ERR(cell))
+ return PTR_ERR(cell);
+
+ buf = nvmem_cell_read(cell, NULL);
+ if (IS_ERR(buf))
+ return PTR_ERR(buf);
+
+ *val = *buf;
+
+ kfree(buf);
+
+ return 0;
+}
+
+static int uniphier_u3hsphy_get_nvparams(struct uniphier_u3hsphy_priv *priv,
+ struct uniphier_u3hsphy_trim_param *pt)
+{
+ int ret;
+
+ ret = uniphier_u3hsphy_get_nvparam(priv, "rterm", &pt->rterm);
+ if (ret)
+ return ret;
+
+ ret = uniphier_u3hsphy_get_nvparam(priv, "sel_t", &pt->sel_t);
+ if (ret)
+ return ret;
+
+ ret = uniphier_u3hsphy_get_nvparam(priv, "hs_i", &pt->hs_i);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int uniphier_u3hsphy_update_config(struct uniphier_u3hsphy_priv *priv,
+ u32 *pconfig)
+{
+ struct uniphier_u3hsphy_trim_param trim;
+ int ret, trimmed = 0;
+
+ if (priv->data->trim_func) {
+ ret = uniphier_u3hsphy_get_nvparams(priv, &trim);
+ if (ret == -EPROBE_DEFER)
+ return ret;
+
+ /*
+ * call trim_func only when trimming parameters that aren't
+ * all-zero can be acquired. All-zero parameters mean nothing
+ * has been written to nvmem.
+ */
+ if (!ret && trim_param_is_valid(&trim)) {
+ priv->data->trim_func(priv, pconfig, &trim);
+ trimmed = 1;
+ } else {
+ dev_dbg(priv->dev, "can't get parameter from nvmem\n");
+ }
+ }
+
+ /* use default parameters without trimming values */
+ if (!trimmed) {
+ *pconfig &= ~HSPHY_CFG0_HSDISC_MASK;
+ *pconfig |= FIELD_PREP(HSPHY_CFG0_HSDISC_MASK, 3);
+ }
+
+ return 0;
+}
+
+static void uniphier_u3hsphy_set_param(struct uniphier_u3hsphy_priv *priv,
+ const struct uniphier_u3hsphy_param *p)
+{
+ u32 val;
+ u32 field_mask = GENMASK(p->field.msb, p->field.lsb);
+ u8 data;
+
+ val = readl(priv->base + HSPHY_CFG1);
+ val &= ~HSPHY_CFG1_ADR_MASK;
+ val |= FIELD_PREP(HSPHY_CFG1_ADR_MASK, p->field.reg_no)
+ | HSPHY_CFG1_ADR_EN;
+ writel(val, priv->base + HSPHY_CFG1);
+
+ val = readl(priv->base + HSPHY_CFG1);
+ val &= ~HSPHY_CFG1_ADR_EN;
+ writel(val, priv->base + HSPHY_CFG1);
+
+ val = readl(priv->base + HSPHY_CFG1);
+ val &= ~FIELD_PREP(HSPHY_CFG1_DAT_MASK, field_mask);
+ data = field_mask & (p->value << p->field.lsb);
+ val |= FIELD_PREP(HSPHY_CFG1_DAT_MASK, data) | HSPHY_CFG1_DAT_EN;
+ writel(val, priv->base + HSPHY_CFG1);
+
+ val = readl(priv->base + HSPHY_CFG1);
+ val &= ~HSPHY_CFG1_DAT_EN;
+ writel(val, priv->base + HSPHY_CFG1);
+}
+
+static int uniphier_u3hsphy_power_on(struct phy *phy)
+{
+ struct uniphier_u3hsphy_priv *priv = phy_get_drvdata(phy);
+ int ret;
+
+ ret = clk_prepare_enable(priv->clk_ext);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret)
+ goto out_clk_ext_disable;
+
+ ret = reset_control_deassert(priv->rst);
+ if (ret)
+ goto out_clk_disable;
+
+ if (priv->vbus) {
+ ret = regulator_enable(priv->vbus);
+ if (ret)
+ goto out_rst_assert;
+ }
+
+ return 0;
+
+out_rst_assert:
+ reset_control_assert(priv->rst);
+out_clk_disable:
+ clk_disable_unprepare(priv->clk);
+out_clk_ext_disable:
+ clk_disable_unprepare(priv->clk_ext);
+
+ return ret;
+}
+
+static int uniphier_u3hsphy_power_off(struct phy *phy)
+{
+ struct uniphier_u3hsphy_priv *priv = phy_get_drvdata(phy);
+
+ if (priv->vbus)
+ regulator_disable(priv->vbus);
+
+ reset_control_assert(priv->rst);
+ clk_disable_unprepare(priv->clk);
+ clk_disable_unprepare(priv->clk_ext);
+
+ return 0;
+}
+
+static int uniphier_u3hsphy_init(struct phy *phy)
+{
+ struct uniphier_u3hsphy_priv *priv = phy_get_drvdata(phy);
+ u32 config0, config1;
+ int i, ret;
+
+ ret = clk_prepare_enable(priv->clk_parent);
+ if (ret)
+ return ret;
+
+ ret = reset_control_deassert(priv->rst_parent);
+ if (ret)
+ goto out_clk_disable;
+
+ if (!priv->data->config0 && !priv->data->config1)
+ return 0;
+
+ config0 = priv->data->config0;
+ config1 = priv->data->config1;
+
+ ret = uniphier_u3hsphy_update_config(priv, &config0);
+ if (ret)
+ goto out_rst_assert;
+
+ writel(config0, priv->base + HSPHY_CFG0);
+ writel(config1, priv->base + HSPHY_CFG1);
+
+ for (i = 0; i < priv->data->nparams; i++)
+ uniphier_u3hsphy_set_param(priv, &priv->data->param[i]);
+
+ return 0;
+
+out_rst_assert:
+ reset_control_assert(priv->rst_parent);
+out_clk_disable:
+ clk_disable_unprepare(priv->clk_parent);
+
+ return ret;
+}
+
+static int uniphier_u3hsphy_exit(struct phy *phy)
+{
+ struct uniphier_u3hsphy_priv *priv = phy_get_drvdata(phy);
+
+ reset_control_assert(priv->rst_parent);
+ clk_disable_unprepare(priv->clk_parent);
+
+ return 0;
+}
+
+static const struct phy_ops uniphier_u3hsphy_ops = {
+ .init = uniphier_u3hsphy_init,
+ .exit = uniphier_u3hsphy_exit,
+ .power_on = uniphier_u3hsphy_power_on,
+ .power_off = uniphier_u3hsphy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int uniphier_u3hsphy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct uniphier_u3hsphy_priv *priv;
+ struct phy_provider *phy_provider;
+ struct resource *res;
+ struct phy *phy;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+ priv->data = of_device_get_match_data(dev);
+ if (WARN_ON(!priv->data ||
+ priv->data->nparams > MAX_PHY_PARAMS))
+ return -EINVAL;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ priv->clk = devm_clk_get(dev, "phy");
+ if (IS_ERR(priv->clk))
+ return PTR_ERR(priv->clk);
+
+ priv->clk_parent = devm_clk_get(dev, "link");
+ if (IS_ERR(priv->clk_parent))
+ return PTR_ERR(priv->clk_parent);
+
+ priv->clk_ext = devm_clk_get(dev, "phy-ext");
+ if (IS_ERR(priv->clk_ext)) {
+ if (PTR_ERR(priv->clk_ext) == -ENOENT)
+ priv->clk_ext = NULL;
+ else
+ return PTR_ERR(priv->clk_ext);
+ }
+
+ priv->rst = devm_reset_control_get_shared(dev, "phy");
+ if (IS_ERR(priv->rst))
+ return PTR_ERR(priv->rst);
+
+ priv->rst_parent = devm_reset_control_get_shared(dev, "link");
+ if (IS_ERR(priv->rst_parent))
+ return PTR_ERR(priv->rst_parent);
+
+ priv->vbus = devm_regulator_get_optional(dev, "vbus");
+ if (IS_ERR(priv->vbus)) {
+ if (PTR_ERR(priv->vbus) == -EPROBE_DEFER)
+ return PTR_ERR(priv->vbus);
+ priv->vbus = NULL;
+ }
+
+ phy = devm_phy_create(dev, dev->of_node, &uniphier_u3hsphy_ops);
+ if (IS_ERR(phy))
+ return PTR_ERR(phy);
+
+ phy_set_drvdata(phy, priv);
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct uniphier_u3hsphy_soc_data uniphier_pxs2_data = {
+ .nparams = 0,
+};
+
+static const struct uniphier_u3hsphy_soc_data uniphier_ld20_data = {
+ .nparams = 2,
+ .param = {
+ { LS_SLEW, 1 },
+ { FS_LS_DRV, 1 },
+ },
+ .trim_func = uniphier_u3hsphy_trim_ld20,
+ .config0 = 0x92316680,
+ .config1 = 0x00000106,
+};
+
+static const struct uniphier_u3hsphy_soc_data uniphier_pxs3_data = {
+ .nparams = 0,
+ .trim_func = uniphier_u3hsphy_trim_ld20,
+ .config0 = 0x92316680,
+ .config1 = 0x00000106,
+};
+
+static const struct of_device_id uniphier_u3hsphy_match[] = {
+ {
+ .compatible = "socionext,uniphier-pxs2-usb3-hsphy",
+ .data = &uniphier_pxs2_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld20-usb3-hsphy",
+ .data = &uniphier_ld20_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pxs3-usb3-hsphy",
+ .data = &uniphier_pxs3_data,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, uniphier_u3hsphy_match);
+
+static struct platform_driver uniphier_u3hsphy_driver = {
+ .probe = uniphier_u3hsphy_probe,
+ .driver = {
+ .name = "uniphier-usb3-hsphy",
+ .of_match_table = uniphier_u3hsphy_match,
+ },
+};
+
+module_platform_driver(uniphier_u3hsphy_driver);
+
+MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
+MODULE_DESCRIPTION("UniPhier HS-PHY driver for USB3 controller");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/phy/socionext/phy-uniphier-usb3ss.c b/drivers/phy/socionext/phy-uniphier-usb3ss.c
new file mode 100644
index 0000000..4be9567
--- /dev/null
+++ b/drivers/phy/socionext/phy-uniphier-usb3ss.c
@@ -0,0 +1,349 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * phy-uniphier-usb3ss.c - SS-PHY driver for Socionext UniPhier USB3 controller
+ * Copyright 2015-2018 Socionext Inc.
+ * Author:
+ * Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+ * Contributors:
+ * Motoya Tanigawa <tanigawa.motoya@socionext.com>
+ * Masami Hiramatsu <masami.hiramatsu@linaro.org>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+
+#define SSPHY_TESTI 0x0
+#define SSPHY_TESTO 0x4
+#define TESTI_DAT_MASK GENMASK(13, 6)
+#define TESTI_ADR_MASK GENMASK(5, 1)
+#define TESTI_WR_EN BIT(0)
+
+#define PHY_F(regno, msb, lsb) { (regno), (msb), (lsb) }
+
+#define CDR_CPD_TRIM PHY_F(7, 3, 0) /* RxPLL charge pump current */
+#define CDR_CPF_TRIM PHY_F(8, 3, 0) /* RxPLL charge pump current 2 */
+#define TX_PLL_TRIM PHY_F(9, 3, 0) /* TxPLL charge pump current */
+#define BGAP_TRIM PHY_F(11, 3, 0) /* Bandgap voltage */
+#define CDR_TRIM PHY_F(13, 6, 5) /* Clock Data Recovery setting */
+#define VCO_CTRL PHY_F(26, 7, 4) /* VCO control */
+#define VCOPLL_CTRL PHY_F(27, 2, 0) /* TxPLL VCO tuning */
+#define VCOPLL_CM PHY_F(28, 1, 0) /* TxPLL voltage */
+
+#define MAX_PHY_PARAMS 7
+
+struct uniphier_u3ssphy_param {
+ struct {
+ int reg_no;
+ int msb;
+ int lsb;
+ } field;
+ u8 value;
+};
+
+struct uniphier_u3ssphy_priv {
+ struct device *dev;
+ void __iomem *base;
+ struct clk *clk, *clk_ext, *clk_parent, *clk_parent_gio;
+ struct reset_control *rst, *rst_parent, *rst_parent_gio;
+ struct regulator *vbus;
+ const struct uniphier_u3ssphy_soc_data *data;
+};
+
+struct uniphier_u3ssphy_soc_data {
+ bool is_legacy;
+ int nparams;
+ const struct uniphier_u3ssphy_param param[MAX_PHY_PARAMS];
+};
+
+static void uniphier_u3ssphy_testio_write(struct uniphier_u3ssphy_priv *priv,
+ u32 data)
+{
+ /* need to read TESTO twice after accessing TESTI */
+ writel(data, priv->base + SSPHY_TESTI);
+ readl(priv->base + SSPHY_TESTO);
+ readl(priv->base + SSPHY_TESTO);
+}
+
+static void uniphier_u3ssphy_set_param(struct uniphier_u3ssphy_priv *priv,
+ const struct uniphier_u3ssphy_param *p)
+{
+ u32 val;
+ u8 field_mask = GENMASK(p->field.msb, p->field.lsb);
+ u8 data;
+
+ /* read previous data */
+ val = FIELD_PREP(TESTI_DAT_MASK, 1);
+ val |= FIELD_PREP(TESTI_ADR_MASK, p->field.reg_no);
+ uniphier_u3ssphy_testio_write(priv, val);
+ val = readl(priv->base + SSPHY_TESTO);
+
+ /* update value */
+ val &= ~FIELD_PREP(TESTI_DAT_MASK, field_mask);
+ data = field_mask & (p->value << p->field.lsb);
+ val = FIELD_PREP(TESTI_DAT_MASK, data);
+ val |= FIELD_PREP(TESTI_ADR_MASK, p->field.reg_no);
+ uniphier_u3ssphy_testio_write(priv, val);
+ uniphier_u3ssphy_testio_write(priv, val | TESTI_WR_EN);
+ uniphier_u3ssphy_testio_write(priv, val);
+
+ /* read current data as dummy */
+ val = FIELD_PREP(TESTI_DAT_MASK, 1);
+ val |= FIELD_PREP(TESTI_ADR_MASK, p->field.reg_no);
+ uniphier_u3ssphy_testio_write(priv, val);
+ readl(priv->base + SSPHY_TESTO);
+}
+
+static int uniphier_u3ssphy_power_on(struct phy *phy)
+{
+ struct uniphier_u3ssphy_priv *priv = phy_get_drvdata(phy);
+ int ret;
+
+ ret = clk_prepare_enable(priv->clk_ext);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret)
+ goto out_clk_ext_disable;
+
+ ret = reset_control_deassert(priv->rst);
+ if (ret)
+ goto out_clk_disable;
+
+ if (priv->vbus) {
+ ret = regulator_enable(priv->vbus);
+ if (ret)
+ goto out_rst_assert;
+ }
+
+ return 0;
+
+out_rst_assert:
+ reset_control_assert(priv->rst);
+out_clk_disable:
+ clk_disable_unprepare(priv->clk);
+out_clk_ext_disable:
+ clk_disable_unprepare(priv->clk_ext);
+
+ return ret;
+}
+
+static int uniphier_u3ssphy_power_off(struct phy *phy)
+{
+ struct uniphier_u3ssphy_priv *priv = phy_get_drvdata(phy);
+
+ if (priv->vbus)
+ regulator_disable(priv->vbus);
+
+ reset_control_assert(priv->rst);
+ clk_disable_unprepare(priv->clk);
+ clk_disable_unprepare(priv->clk_ext);
+
+ return 0;
+}
+
+static int uniphier_u3ssphy_init(struct phy *phy)
+{
+ struct uniphier_u3ssphy_priv *priv = phy_get_drvdata(phy);
+ int i, ret;
+
+ ret = clk_prepare_enable(priv->clk_parent);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(priv->clk_parent_gio);
+ if (ret)
+ goto out_clk_disable;
+
+ ret = reset_control_deassert(priv->rst_parent);
+ if (ret)
+ goto out_clk_gio_disable;
+
+ ret = reset_control_deassert(priv->rst_parent_gio);
+ if (ret)
+ goto out_rst_assert;
+
+ if (priv->data->is_legacy)
+ return 0;
+
+ for (i = 0; i < priv->data->nparams; i++)
+ uniphier_u3ssphy_set_param(priv, &priv->data->param[i]);
+
+ return 0;
+
+out_rst_assert:
+ reset_control_assert(priv->rst_parent);
+out_clk_gio_disable:
+ clk_disable_unprepare(priv->clk_parent_gio);
+out_clk_disable:
+ clk_disable_unprepare(priv->clk_parent);
+
+ return ret;
+}
+
+static int uniphier_u3ssphy_exit(struct phy *phy)
+{
+ struct uniphier_u3ssphy_priv *priv = phy_get_drvdata(phy);
+
+ reset_control_assert(priv->rst_parent_gio);
+ reset_control_assert(priv->rst_parent);
+ clk_disable_unprepare(priv->clk_parent_gio);
+ clk_disable_unprepare(priv->clk_parent);
+
+ return 0;
+}
+
+static const struct phy_ops uniphier_u3ssphy_ops = {
+ .init = uniphier_u3ssphy_init,
+ .exit = uniphier_u3ssphy_exit,
+ .power_on = uniphier_u3ssphy_power_on,
+ .power_off = uniphier_u3ssphy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int uniphier_u3ssphy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct uniphier_u3ssphy_priv *priv;
+ struct phy_provider *phy_provider;
+ struct resource *res;
+ struct phy *phy;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+ priv->data = of_device_get_match_data(dev);
+ if (WARN_ON(!priv->data ||
+ priv->data->nparams > MAX_PHY_PARAMS))
+ return -EINVAL;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ if (!priv->data->is_legacy) {
+ priv->clk = devm_clk_get(dev, "phy");
+ if (IS_ERR(priv->clk))
+ return PTR_ERR(priv->clk);
+
+ priv->clk_ext = devm_clk_get(dev, "phy-ext");
+ if (IS_ERR(priv->clk_ext)) {
+ if (PTR_ERR(priv->clk_ext) == -ENOENT)
+ priv->clk_ext = NULL;
+ else
+ return PTR_ERR(priv->clk_ext);
+ }
+
+ priv->rst = devm_reset_control_get_shared(dev, "phy");
+ if (IS_ERR(priv->rst))
+ return PTR_ERR(priv->rst);
+ } else {
+ priv->clk_parent_gio = devm_clk_get(dev, "gio");
+ if (IS_ERR(priv->clk_parent_gio))
+ return PTR_ERR(priv->clk_parent_gio);
+
+ priv->rst_parent_gio =
+ devm_reset_control_get_shared(dev, "gio");
+ if (IS_ERR(priv->rst_parent_gio))
+ return PTR_ERR(priv->rst_parent_gio);
+ }
+
+ priv->clk_parent = devm_clk_get(dev, "link");
+ if (IS_ERR(priv->clk_parent))
+ return PTR_ERR(priv->clk_parent);
+
+ priv->rst_parent = devm_reset_control_get_shared(dev, "link");
+ if (IS_ERR(priv->rst_parent))
+ return PTR_ERR(priv->rst_parent);
+
+ priv->vbus = devm_regulator_get_optional(dev, "vbus");
+ if (IS_ERR(priv->vbus)) {
+ if (PTR_ERR(priv->vbus) == -EPROBE_DEFER)
+ return PTR_ERR(priv->vbus);
+ priv->vbus = NULL;
+ }
+
+ phy = devm_phy_create(dev, dev->of_node, &uniphier_u3ssphy_ops);
+ if (IS_ERR(phy))
+ return PTR_ERR(phy);
+
+ phy_set_drvdata(phy, priv);
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct uniphier_u3ssphy_soc_data uniphier_pro4_data = {
+ .is_legacy = true,
+};
+
+static const struct uniphier_u3ssphy_soc_data uniphier_pxs2_data = {
+ .is_legacy = false,
+ .nparams = 7,
+ .param = {
+ { CDR_CPD_TRIM, 10 },
+ { CDR_CPF_TRIM, 3 },
+ { TX_PLL_TRIM, 5 },
+ { BGAP_TRIM, 9 },
+ { CDR_TRIM, 2 },
+ { VCOPLL_CTRL, 7 },
+ { VCOPLL_CM, 1 },
+ },
+};
+
+static const struct uniphier_u3ssphy_soc_data uniphier_ld20_data = {
+ .is_legacy = false,
+ .nparams = 3,
+ .param = {
+ { CDR_CPD_TRIM, 6 },
+ { CDR_TRIM, 2 },
+ { VCO_CTRL, 5 },
+ },
+};
+
+static const struct of_device_id uniphier_u3ssphy_match[] = {
+ {
+ .compatible = "socionext,uniphier-pro4-usb3-ssphy",
+ .data = &uniphier_pro4_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pxs2-usb3-ssphy",
+ .data = &uniphier_pxs2_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld20-usb3-ssphy",
+ .data = &uniphier_ld20_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pxs3-usb3-ssphy",
+ .data = &uniphier_ld20_data,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, uniphier_u3ssphy_match);
+
+static struct platform_driver uniphier_u3ssphy_driver = {
+ .probe = uniphier_u3ssphy_probe,
+ .driver = {
+ .name = "uniphier-usb3-ssphy",
+ .of_match_table = uniphier_u3ssphy_match,
+ },
+};
+
+module_platform_driver(uniphier_u3ssphy_driver);
+
+MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
+MODULE_DESCRIPTION("UniPhier SS-PHY driver for USB3 controller");
+MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v3 3/4] dt-bindings: phy: add DT bindings for UniPhier USB2 PHY driver
2018-08-22 3:50 [PATCH v3 0/4] phy: socionext: add new UniPhier USB PHY driver support Kunihiko Hayashi
2018-08-22 3:50 ` [PATCH v3 1/4] dt-bindings: phy: add DT bindings for UniPhier USB3 PHY driver Kunihiko Hayashi
2018-08-22 3:50 ` [PATCH v3 2/4] phy: socionext: add USB3 PHY driver for UniPhier SoC Kunihiko Hayashi
@ 2018-08-22 3:50 ` Kunihiko Hayashi
2018-08-22 3:50 ` [PATCH v3 4/4] phy: socionext: add USB2 PHY driver for UniPhier SoC Kunihiko Hayashi
3 siblings, 0 replies; 5+ messages in thread
From: Kunihiko Hayashi @ 2018-08-22 3:50 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Rob Herring, Mark Rutland, Masahiro Yamada
Cc: linux-arm-kernel, linux-kernel, devicetree, Masami Hiramatsu,
Jassi Brar, Kunihiko Hayashi
Add DT bindings for PHY interface built into USB2 controller
implemented on Socionext UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
.../devicetree/bindings/phy/uniphier-usb2-phy.txt | 45 ++++++++++++++++++++++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/uniphier-usb2-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/uniphier-usb2-phy.txt b/Documentation/devicetree/bindings/phy/uniphier-usb2-phy.txt
new file mode 100644
index 0000000..b43b282
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/uniphier-usb2-phy.txt
@@ -0,0 +1,45 @@
+Socionext UniPhier USB2 PHY
+
+This describes the devicetree bindings for PHY interface built into
+USB2 controller implemented on Socionext UniPhier SoCs.
+
+Pro4 SoC has both USB2 and USB3 host controllers, however, this USB3
+controller doesn't include its own High-Speed PHY. This needs to specify
+USB2 PHY instead of USB3 HS-PHY.
+
+Required properties:
+- compatible: Should contain one of the following:
+ "socionext,uniphier-pro4-usb2-phy" - for Pro4 SoC
+ "socionext,uniphier-ld11-usb2-phy" - for LD11 SoC
+
+Sub-nodes:
+Each PHY should be represented as a sub-node.
+
+Sub-nodes required properties:
+- #phy-cells: Should be 0.
+- reg: The number of the PHY.
+
+Sub-nodes optional properties:
+- vbus-supply: A phandle to the regulator for USB VBUS.
+
+Refer to phy/phy-bindings.txt for the generic PHY binding properties.
+
+Example:
+ soc-glue@5f800000 {
+ ...
+ usb-phy {
+ compatible = "socionext,uniphier-ld11-usb2-phy";
+ usb_phy0: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ ...
+ };
+ };
+
+ usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ ...
+ phy-names = "usb";
+ phys = <&usb_phy0>;
+ };
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v3 4/4] phy: socionext: add USB2 PHY driver for UniPhier SoC
2018-08-22 3:50 [PATCH v3 0/4] phy: socionext: add new UniPhier USB PHY driver support Kunihiko Hayashi
` (2 preceding siblings ...)
2018-08-22 3:50 ` [PATCH v3 3/4] dt-bindings: phy: add DT bindings for UniPhier USB2 PHY driver Kunihiko Hayashi
@ 2018-08-22 3:50 ` Kunihiko Hayashi
3 siblings, 0 replies; 5+ messages in thread
From: Kunihiko Hayashi @ 2018-08-22 3:50 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Rob Herring, Mark Rutland, Masahiro Yamada
Cc: linux-arm-kernel, linux-kernel, devicetree, Masami Hiramatsu,
Jassi Brar, Kunihiko Hayashi
Add a driver for PHY interface built into USB2 controller implemented on
UniPhier SoCs. This driver supports HS-PHY for Pro4 and LD11.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/phy/socionext/Kconfig | 13 ++
drivers/phy/socionext/Makefile | 1 +
drivers/phy/socionext/phy-uniphier-usb2.c | 244 ++++++++++++++++++++++++++++++
3 files changed, 258 insertions(+)
create mode 100644 drivers/phy/socionext/phy-uniphier-usb2.c
diff --git a/drivers/phy/socionext/Kconfig b/drivers/phy/socionext/Kconfig
index 4a172fc..497ca38 100644
--- a/drivers/phy/socionext/Kconfig
+++ b/drivers/phy/socionext/Kconfig
@@ -2,6 +2,19 @@
# PHY drivers for Socionext platforms.
#
+config PHY_UNIPHIER_USB2
+ tristate "UniPhier USB2 PHY driver"
+ depends on ARCH_UNIPHIER || COMPILE_TEST
+ depends on OF && HAS_IOMEM
+ select GENERIC_PHY
+ select MFD_SYSCON
+ help
+ Enable this to support USB PHY implemented on USB2 controller
+ on UniPhier SoCs. This driver provides interface to interact
+ with USB 2.0 PHY that is part of the UniPhier SoC.
+ In case of Pro4, it is necessary to specify this USB2 PHY instead
+ of USB3 HS-PHY.
+
config PHY_UNIPHIER_USB3
tristate "UniPhier USB3 PHY driver"
depends on ARCH_UNIPHIER || COMPILE_TEST
diff --git a/drivers/phy/socionext/Makefile b/drivers/phy/socionext/Makefile
index e230fa31..91e4825 100644
--- a/drivers/phy/socionext/Makefile
+++ b/drivers/phy/socionext/Makefile
@@ -3,4 +3,5 @@
# Makefile for the phy drivers.
#
+obj-$(CONFIG_PHY_UNIPHIER_USB2) += phy-uniphier-usb2.o
obj-$(CONFIG_PHY_UNIPHIER_USB3) += phy-uniphier-usb3hs.o phy-uniphier-usb3ss.o
diff --git a/drivers/phy/socionext/phy-uniphier-usb2.c b/drivers/phy/socionext/phy-uniphier-usb2.c
new file mode 100644
index 0000000..3f2086e
--- /dev/null
+++ b/drivers/phy/socionext/phy-uniphier-usb2.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * phy-uniphier-usb2.c - PHY driver for UniPhier USB2 controller
+ * Copyright 2015-2018 Socionext Inc.
+ * Author:
+ * Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+
+#define SG_USBPHY1CTRL 0x500
+#define SG_USBPHY1CTRL2 0x504
+#define SG_USBPHY2CTRL 0x508
+#define SG_USBPHY2CTRL2 0x50c /* LD11 */
+#define SG_USBPHY12PLL 0x50c /* Pro4 */
+#define SG_USBPHY3CTRL 0x510
+#define SG_USBPHY3CTRL2 0x514
+#define SG_USBPHY4CTRL 0x518 /* Pro4 */
+#define SG_USBPHY4CTRL2 0x51c /* Pro4 */
+#define SG_USBPHY34PLL 0x51c /* Pro4 */
+
+struct uniphier_u2phy_param {
+ u32 offset;
+ u32 value;
+};
+
+struct uniphier_u2phy_soc_data {
+ struct uniphier_u2phy_param config0;
+ struct uniphier_u2phy_param config1;
+};
+
+struct uniphier_u2phy_priv {
+ struct regmap *regmap;
+ struct phy *phy;
+ struct regulator *vbus;
+ const struct uniphier_u2phy_soc_data *data;
+ struct uniphier_u2phy_priv *next;
+};
+
+static int uniphier_u2phy_power_on(struct phy *phy)
+{
+ struct uniphier_u2phy_priv *priv = phy_get_drvdata(phy);
+ int ret = 0;
+
+ if (priv->vbus)
+ ret = regulator_enable(priv->vbus);
+
+ return ret;
+}
+
+static int uniphier_u2phy_power_off(struct phy *phy)
+{
+ struct uniphier_u2phy_priv *priv = phy_get_drvdata(phy);
+
+ if (priv->vbus)
+ regulator_disable(priv->vbus);
+
+ return 0;
+}
+
+static int uniphier_u2phy_init(struct phy *phy)
+{
+ struct uniphier_u2phy_priv *priv = phy_get_drvdata(phy);
+
+ if (!priv->data)
+ return 0;
+
+ regmap_write(priv->regmap, priv->data->config0.offset,
+ priv->data->config0.value);
+ regmap_write(priv->regmap, priv->data->config1.offset,
+ priv->data->config1.value);
+
+ return 0;
+}
+
+static struct phy *uniphier_u2phy_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct uniphier_u2phy_priv *priv = dev_get_drvdata(dev);
+
+ while (priv && args->np != priv->phy->dev.of_node)
+ priv = priv->next;
+
+ if (!priv) {
+ dev_err(dev, "Failed to find appropriate phy\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ return priv->phy;
+}
+
+static const struct phy_ops uniphier_u2phy_ops = {
+ .init = uniphier_u2phy_init,
+ .power_on = uniphier_u2phy_power_on,
+ .power_off = uniphier_u2phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int uniphier_u2phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *parent, *child;
+ struct uniphier_u2phy_priv *priv = NULL, *next = NULL;
+ struct phy_provider *phy_provider;
+ struct regmap *regmap;
+ const struct uniphier_u2phy_soc_data *data;
+ int ret, data_idx, ndatas;
+
+ data = of_device_get_match_data(dev);
+ if (WARN_ON(!data))
+ return -EINVAL;
+
+ /* get number of data */
+ for (ndatas = 0; data[ndatas].config0.offset; ndatas++)
+ ;
+
+ parent = of_get_parent(dev->of_node);
+ regmap = syscon_node_to_regmap(parent);
+ of_node_put(parent);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "Failed to get regmap\n");
+ return PTR_ERR(regmap);
+ }
+
+ for_each_child_of_node(dev->of_node, child) {
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ ret = -ENOMEM;
+ goto out_put_child;
+ }
+ priv->regmap = regmap;
+
+ priv->vbus = devm_regulator_get_optional(dev, "vbus");
+ if (IS_ERR(priv->vbus)) {
+ if (PTR_ERR(priv->vbus) == -EPROBE_DEFER) {
+ ret = PTR_ERR(priv->vbus);
+ goto out_put_child;
+ }
+ priv->vbus = NULL;
+ }
+
+ priv->phy = devm_phy_create(dev, child, &uniphier_u2phy_ops);
+ if (IS_ERR(priv->phy)) {
+ dev_err(dev, "Failed to create phy\n");
+ ret = PTR_ERR(priv->phy);
+ goto out_put_child;
+ }
+
+ ret = of_property_read_u32(child, "reg", &data_idx);
+ if (ret) {
+ dev_err(dev, "Failed to get reg property\n");
+ goto out_put_child;
+ }
+
+ if (data_idx < ndatas)
+ priv->data = &data[data_idx];
+ else
+ dev_warn(dev, "No phy configuration: %s\n",
+ child->full_name);
+
+ phy_set_drvdata(priv->phy, priv);
+ priv->next = next;
+ next = priv;
+ }
+
+ dev_set_drvdata(dev, priv);
+ phy_provider = devm_of_phy_provider_register(dev,
+ uniphier_u2phy_xlate);
+ return PTR_ERR_OR_ZERO(phy_provider);
+
+out_put_child:
+ of_node_put(child);
+
+ return ret;
+}
+
+static const struct uniphier_u2phy_soc_data uniphier_pro4_data[] = {
+ {
+ .config0 = { SG_USBPHY1CTRL, 0x05142400 },
+ .config1 = { SG_USBPHY12PLL, 0x00010010 },
+ },
+ {
+ .config0 = { SG_USBPHY2CTRL, 0x05142400 },
+ .config1 = { SG_USBPHY12PLL, 0x00010010 },
+ },
+ {
+ .config0 = { SG_USBPHY3CTRL, 0x05142400 },
+ .config1 = { SG_USBPHY34PLL, 0x00010010 },
+ },
+ {
+ .config0 = { SG_USBPHY4CTRL, 0x05142400 },
+ .config1 = { SG_USBPHY34PLL, 0x00010010 },
+ },
+ { /* sentinel */ }
+};
+
+static const struct uniphier_u2phy_soc_data uniphier_ld11_data[] = {
+ {
+ .config0 = { SG_USBPHY1CTRL, 0x82280000 },
+ .config1 = { SG_USBPHY1CTRL2, 0x00000106 },
+ },
+ {
+ .config0 = { SG_USBPHY2CTRL, 0x82280000 },
+ .config1 = { SG_USBPHY2CTRL2, 0x00000106 },
+ },
+ {
+ .config0 = { SG_USBPHY3CTRL, 0x82280000 },
+ .config1 = { SG_USBPHY3CTRL2, 0x00000106 },
+ },
+ { /* sentinel */ }
+};
+
+static const struct of_device_id uniphier_u2phy_match[] = {
+ {
+ .compatible = "socionext,uniphier-pro4-usb2-phy",
+ .data = &uniphier_pro4_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld11-usb2-phy",
+ .data = &uniphier_ld11_data,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, uniphier_u2phy_match);
+
+static struct platform_driver uniphier_u2phy_driver = {
+ .probe = uniphier_u2phy_probe,
+ .driver = {
+ .name = "uniphier-usb2-phy",
+ .of_match_table = uniphier_u2phy_match,
+ },
+};
+module_platform_driver(uniphier_u2phy_driver);
+
+MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
+MODULE_DESCRIPTION("UniPhier PHY driver for USB2 controller");
+MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-08-22 3:51 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-08-22 3:50 [PATCH v3 0/4] phy: socionext: add new UniPhier USB PHY driver support Kunihiko Hayashi
2018-08-22 3:50 ` [PATCH v3 1/4] dt-bindings: phy: add DT bindings for UniPhier USB3 PHY driver Kunihiko Hayashi
2018-08-22 3:50 ` [PATCH v3 2/4] phy: socionext: add USB3 PHY driver for UniPhier SoC Kunihiko Hayashi
2018-08-22 3:50 ` [PATCH v3 3/4] dt-bindings: phy: add DT bindings for UniPhier USB2 PHY driver Kunihiko Hayashi
2018-08-22 3:50 ` [PATCH v3 4/4] phy: socionext: add USB2 PHY driver for UniPhier SoC Kunihiko Hayashi
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