From: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
To: <vkoul@kernel.org>, <dan.j.williams@intel.com>,
<michal.simek@xilinx.com>, <appana.durga.rao@xilinx.com>,
<radhey.shyam.pandey@xilinx.com>
Cc: <dmaengine@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH v2 4/4] dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer
Date: Sat, 29 Sep 2018 11:18:00 -0600 [thread overview]
Message-ID: <1538241480-13844-5-git-send-email-radhey.shyam.pandey@xilinx.com> (raw)
In-Reply-To: <1538241480-13844-1-git-send-email-radhey.shyam.pandey@xilinx.com>
In AXI CDMA simple mode also pass MSB bits of source and destination
address to xilinx_write function. This fixes simple CDMA operation
mode using 64-bit addressing.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Changes for v2:
Use helper macro for preparing dma_addr_t.
---
drivers/dma/xilinx/xilinx_dma.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index c27ab64..d04ef85 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -1247,8 +1247,10 @@ static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
hw = &segment->hw;
- xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, hw->src_addr);
- xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, hw->dest_addr);
+ xilinx_write(chan, XILINX_CDMA_REG_SRCADDR,
+ xilinx_prep_dma_addr_t(hw->src_addr));
+ xilinx_write(chan, XILINX_CDMA_REG_DSTADDR,
+ xilinx_prep_dma_addr_t(hw->dest_addr));
/* Start the transfer */
dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
--
1.7.1
next prev parent reply other threads:[~2018-09-29 17:18 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-29 17:17 [PATCH v2 0/4] dmaengine: xilinx_dma: Minor fix and refactoring Radhey Shyam Pandey
2018-09-29 17:17 ` [PATCH v2 1/4] dmaengine: xilinx_dma: Refactor axidma channel allocation Radhey Shyam Pandey
2018-09-29 17:17 ` [PATCH v2 2/4] dmaengine: xilinx_dma: Refactor axidma channel validation Radhey Shyam Pandey
2018-11-11 10:29 ` Vinod Koul
2018-11-15 2:57 ` Radhey Shyam Pandey
2018-09-29 17:17 ` [PATCH v2 3/4] dmaengine: xilinx_dma: Introduce helper macro for preparing dma address Radhey Shyam Pandey
2018-10-19 10:37 ` Appana Durga Kedareswara Rao
2018-09-29 17:18 ` Radhey Shyam Pandey [this message]
2018-10-19 10:38 ` [PATCH v2 4/4] dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer Appana Durga Kedareswara Rao
2018-11-11 10:34 ` [PATCH v2 0/4] dmaengine: xilinx_dma: Minor fix and refactoring Vinod Koul
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