From: <honghui.zhang@mediatek.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>, <linux-pci@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <ryder.lee@mediatek.com>
Cc: <ulf.hansson@linaro.org>, <marc.zyngier@arm.com>,
<matthias.bgg@gmail.com>, <devicetree@vger.kernel.org>,
<yingjoe.chen@mediatek.com>, <eddie.huang@mediatek.com>,
<honghui.zhang@mediatek.com>, <youlin.pei@mediatek.com>,
<yt.shen@mediatek.com>, <sean.wang@mediatek.com>
Subject: [PATCH v6 2/9] PCI: mediatek: Fixup class ID for MT7622 as PCI_CLASS_BRIDGE_PCI
Date: Mon, 8 Oct 2018 11:24:41 +0800 [thread overview]
Message-ID: <1538969088-7136-3-git-send-email-honghui.zhang@mediatek.com> (raw)
In-Reply-To: <1538969088-7136-1-git-send-email-honghui.zhang@mediatek.com>
From: Honghui Zhang <honghui.zhang@mediatek.com>
The PCIe controller of MT7622 has TYPE 1 configuration space type, but
the HW default class type values is invalid.
The commit 101c92dc80c8 ("PCI: mediatek: Set up vendor ID and class
type for MT7622") have set the class ID for MT7622 as
PCI_CLASS_BRIDGE_HOST, but it's not workable for MT7622:
In __pci_bus_assign_resources, the framework only setup bridge's
resource window only if class type is PCI_CLASS_BRIDGE_PCI. Or it
will leave the subordinary PCIe device's MMIO window un-touched.
Fixup the class type to PCI_CLASS_BRIDGE_PCI as most of the controller
driver do.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
---
drivers/pci/controller/pcie-mediatek.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index 288b8e2..bcdac9b 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -432,7 +432,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
val = PCI_VENDOR_ID_MEDIATEK;
writew(val, port->base + PCIE_CONF_VEND_ID);
- val = PCI_CLASS_BRIDGE_HOST;
+ val = PCI_CLASS_BRIDGE_PCI;
writew(val, port->base + PCIE_CONF_CLASS_ID);
}
--
2.6.4
next prev parent reply other threads:[~2018-10-08 3:25 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-08 3:24 [PATCH v6 0/9] PCI: mediatek: fixup find_port, enable_msi and add pm, module support honghui.zhang
2018-10-08 3:24 ` [PATCH v6 1/9] PCI: mediatek: Using slot's devfn for compare to fix mtk_pcie_find_port logic honghui.zhang
2018-10-08 3:24 ` honghui.zhang [this message]
2018-10-08 17:23 ` [PATCH v6 2/9] PCI: mediatek: Fixup class ID for MT7622 as PCI_CLASS_BRIDGE_PCI Lorenzo Pieralisi
2018-10-09 3:08 ` Honghui Zhang
2018-10-11 11:38 ` Lorenzo Pieralisi
2018-10-12 8:01 ` Honghui Zhang
2018-10-12 10:22 ` Lorenzo Pieralisi
2018-10-12 14:12 ` Bjorn Helgaas
2018-10-15 2:42 ` Honghui Zhang
2018-10-15 18:34 ` Bjorn Helgaas
2018-10-15 2:04 ` Honghui Zhang
2018-10-08 3:24 ` [PATCH v6 3/9] PCI: mediatek: Remove the redundant dev->pm_domain check honghui.zhang
2018-10-08 3:24 ` [PATCH v6 4/9] PCI: mediatek: Convert to use pci_host_probe() honghui.zhang
2018-10-08 3:24 ` [PATCH v6 5/9] PCI: mediatek: Move the mtk_pcie_startup_port_v2 function's define after mtk_pcie_setup_irq honghui.zhang
2018-10-08 3:24 ` [PATCH v6 6/9] PCI: mediatek: Fixup enable msi logic by enable msi after clock enabled honghui.zhang
2018-10-08 3:24 ` [PATCH v6 7/9] PCI: mediatek: Add system pm support for MT2712 and MT7622 honghui.zhang
2018-10-08 3:24 ` [PATCH v6 8/9] PCI: mediatek: Save the GIC IRQ in mtk_pcie_port honghui.zhang
2018-10-08 3:24 ` [PATCH v6 9/9] PCI: mediatek: Add loadable kernel module support honghui.zhang
2018-10-08 17:31 ` [PATCH v6 0/9] PCI: mediatek: fixup find_port, enable_msi and add pm, " Bjorn Helgaas
2018-10-09 1:44 ` Honghui Zhang
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