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From: <honghui.zhang@mediatek.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>, <linux-pci@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <ryder.lee@mediatek.com>
Cc: <ulf.hansson@linaro.org>, <marc.zyngier@arm.com>,
	<matthias.bgg@gmail.com>, <devicetree@vger.kernel.org>,
	<yingjoe.chen@mediatek.com>, <eddie.huang@mediatek.com>,
	<honghui.zhang@mediatek.com>, <youlin.pei@mediatek.com>,
	<yt.shen@mediatek.com>, <jianjun.wang@mediatek.com>
Subject: [PATCH v7 2/9] PCI: mediatek: Fix class type for MT7622 as PCI_CLASS_BRIDGE_PCI
Date: Mon, 15 Oct 2018 13:44:40 +0800	[thread overview]
Message-ID: <1539582287-9171-3-git-send-email-honghui.zhang@mediatek.com> (raw)
In-Reply-To: <1539582287-9171-1-git-send-email-honghui.zhang@mediatek.com>

From: Honghui Zhang <honghui.zhang@mediatek.com>

The commit 101c92dc80c8 ("PCI: mediatek: Set up vendor ID and class
type for MT7622") have set the class type for MT7622 as un-properly
value of PCI_CLASS_BRIDGE_HOST.

The PCIe controller of MT7622 is complexed with Root Port and PCI-to-PCI
bridge, the bridge has type 1 configuration space header and related bridge
windows. The HW default value of this bridge's class type is invalid. Fix
its class type as PCI_CLASS_BRIDGE_PCI since it is HW defines.

Making the bridge visiable to PCI framework by setting its class type
properly will get its bridge windows configurated during PCI device
enumerate.

Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
---
 drivers/pci/controller/pcie-mediatek.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index 288b8e2..bcdac9b 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -432,7 +432,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
 		val = PCI_VENDOR_ID_MEDIATEK;
 		writew(val, port->base + PCIE_CONF_VEND_ID);
 
-		val = PCI_CLASS_BRIDGE_HOST;
+		val = PCI_CLASS_BRIDGE_PCI;
 		writew(val, port->base + PCIE_CONF_CLASS_ID);
 	}
 
-- 
2.6.4


  parent reply	other threads:[~2018-10-15  5:45 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-15  5:44 [PATCH v7 0/9] PCI: mediatek: fixup find_port, enable_msi and add PM, module support honghui.zhang
2018-10-15  5:44 ` [PATCH v7 1/9] PCI: mediatek: Using slot's devfn for compare to fix mtk_pcie_find_port logic honghui.zhang
2018-10-15  5:44 ` honghui.zhang [this message]
2018-10-15  5:44 ` [PATCH v7 3/9] PCI: mediatek: Remove the redundant dev->pm_domain check honghui.zhang
2018-10-15  5:44 ` [PATCH v7 4/9] PCI: mediatek: Convert to use pci_host_probe() honghui.zhang
2018-10-15  5:44 ` [PATCH v7 5/9] PCI: mediatek: Move the mtk_pcie_startup_port_v2 function's define after mtk_pcie_setup_irq honghui.zhang
2018-10-15  5:44 ` [PATCH v7 6/9] PCI: mediatek: Fixup enable MSI logic by enable MSI after clock enabled honghui.zhang
2018-10-15  5:44 ` [PATCH v7 7/9] PCI: mediatek: Add system PM support for MT2712 and MT7622 honghui.zhang
2018-10-15  5:44 ` [PATCH v7 8/9] PCI: mediatek: Save the GIC IRQ in mtk_pcie_port honghui.zhang
2018-10-15  5:44 ` [PATCH v7 9/9] PCI: mediatek: Add loadable kernel module support honghui.zhang
2018-10-15  6:05 ` [PATCH v7 0/9] PCI: mediatek: fixup find_port, enable_msi and add PM, " Ryder Lee
2018-10-15  6:49   ` Honghui Zhang

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