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* [PATCH V12 00/14] Krait clocks + Krait CPUfreq
@ 2018-08-14 12:12 Sricharan R
  2018-08-14 12:12 ` [PATCH v12 01/14] ARM: Add Krait L2 register accessor functions Sricharan R
                   ` (14 more replies)
  0 siblings, 15 replies; 32+ messages in thread
From: Sricharan R @ 2018-08-14 12:12 UTC (permalink / raw)
  To: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel
  Cc: sricharan

[v12]
  * Added my signed-off that was missing in some patches.
  * Added Bjorn's acked that i missed earlier.

[v11]
  * Dropped patch 13 and 14 from v10 and
    merged the qcom-cpufreq-krait driver to the existing qcom-cpufreq-kryo.c
  * Rebased on top of clk-next
  * Fixed a bug while populating the pvs version for krait.

[v10]
  * Addressed Stephen's comments to add clocks bindings properties
    to the newly introduced nodes.
  * Added a change to include opp-supported-hw to qcom-cpufreq.c
  * Rebased on top of clk-next
  * Although there were minor changes to bindings and the driver
    retained the acked-by tags from Rob and Viresh respectively.    

[v9]
  * Fixed a rebase issue in Makefile and added Tag from Robh.

[v8]
  * Fixed a bug in path#14 pointed out by Viresh and also added tags.
    No change in any other patch.

[v7]
  * Fixed comments from Viresh for cleaning up the error handling
    in qcom-cpufreq.c. Also changed the init function to lateinit
    call. This is required because nvmem which gets initialised with
    module_init needs to go first.
  * Fixed Rob's comments for bindings documentation
  * Fixed kbuild build issue in clk-lpc32xx.c
  * Rebased on top of clk-next

[v6]
  * Adrressed comments from Viresh for patch #14 in v5 [5]
  * Introduced a new binding operating-points-v2-krait-cpu
    as per discussion with Rob
  * Added Review tags

[v5]
  * Addressed comments from Rob for bindings
  * Addressed comments from Viresh to use dev_pm_opp_set_prop_name, accordingly
    dropped patch #12 and corrected patch #11 from previous patch set in [4]
  * Converted to use #spdx tags for newly introduced files

Mostly a resend of the v3 posted by Stephen quite some time back [1]
except for few changes.
  Based on reading some feedback from list,
  * Dropped the patch "clk: Add safe switch hook" from v3 [2].
    Now this is taken care by patch#10 in this series only for Krait.
  * Dropped the path "clk: Avoid sending high rates to downstream
		      clocks during set_rate" from v3 [3].
  * Rebased on top of clk-next.
  * Dropped the DT update from the series. Will send separately
  * Now with cpufreq-dt+opp supporting voltage scaling, registering the
    krait cpu supplies in DT should be sufficient. But one issue is,
    the qcom-cpufreq drivers reads the efuse and based on that registers
    the opp data and then registers the cpufreq-dt device. So when
    cpufreq-dt driver probes and registers the regulator to the OPP framework,
    it expects that the opp data for the device should not be registered before
    the regulator. Will send a RFC patch removing that check, to find out the
    right way of doing it.

These patches provide cpufreq scaling on devices with Krait CPUs.
In Krait CPU designs there's one PLL and two muxes per CPU, allowing
us to switch CPU frequencies independently.

				 secondary
	 +-----+                    +
	 | QSB |-------+------------|\
	 +-----+       |            | |-+
		       |    +-------|/  |
		       |    |       +   |
	 +-----+       |    |           |
	 | PLL |----+-------+           |   primary
	 +-----+    |  |                |     +
		    |  |                +-----|\       +------+
	 +-------+  |  |                      | \      |      |
	 | HFPLL |----------+-----------------|  |-----| CPU0 |
	 +-------+  |  |    |                 |  |     |      |
		    |  |    | +-----+         | /      +------+
		    |  |    +-| / 2 |---------|/
		    |  |      +-----+         +
		    |  |         secondary
		    |  |            +
		    |  +------------|\
		    |               | |-+
		    +---------------|/  |   primary
				    +   |     +
					+-----|\       +------+
	 +-------+                            | \      |      |
	 | HFPLL |----------------------------|  |-----| CPU1 |
	 +-------+          |                 |  |     |      |
			    | +-----+         | /      +------+
			    +-| / 2 |---------|/
			      +-----+         +

To support this in the common clock framework we model the muxes,
dividers, and PLLs as different clocks. CPUfreq only interacts
with the primary mux (farthest right in the diagram). When CPUfreq
sets a rate, the mux code finds the best parent that can provide the rate.
Due to the design, QSB and the top PLL are always a fixed rate and thus
only support one frequency each. These sources provide the lowest
frequencies for the CPUs. The HFPLLs are where we can make the CPU go
faster (GHz range). Sometimes we need to run the HFPLL twice as
fast and divide it by two to get a particular frequency.

When switching rates we can't leave the CPU clocked by the HFPLL because
we need to turn off the output of the PLL when changing its frequency.
This means we have to switch over to the secondary mux and use one of the
fixed sources. This is why we need something like the safe parent patch.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332607.html
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332615.html
[3] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
[4] https://lwn.net/Articles/740994/ 
[5] https://lkml.org/lkml/2017/12/19/537


Sricharan R (3):
  clk: qcom: Add safe switch hook for krait mux clocks
  cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem
    based qcom socs
  cpufreq: qcom: Add support for krait based socs

Stephen Boyd (11):
  ARM: Add Krait L2 register accessor functions
  clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
  clk: qcom: Add HFPLL driver
  dt-bindings: clock: Document qcom,hfpll
  clk: qcom: Add MSM8960/APQ8064's HFPLLs
  clk: qcom: Add IPQ806X's HFPLLs
  clk: qcom: Add support for Krait clocks
  clk: qcom: Add KPSS ACC/GCC driver
  dt-bindings: arm: Document qcom,kpss-gcc
  clk: qcom: Add Krait clock controller driver
  dt-bindings: clock: Document qcom,krait-cc

 .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt  |  19 +
 .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt  |  44 +++
 .../devicetree/bindings/clock/qcom,hfpll.txt       |  60 ++++
 .../devicetree/bindings/clock/qcom,krait-cc.txt    |  34 ++
 .../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt}   |   7 +-
 arch/arm/common/Kconfig                            |   3 +
 arch/arm/common/Makefile                           |   1 +
 arch/arm/common/krait-l2-accessors.c               |  48 +++
 arch/arm/include/asm/krait-l2-accessors.h          |   9 +
 drivers/clk/qcom/Kconfig                           |  28 ++
 drivers/clk/qcom/Makefile                          |   5 +
 drivers/clk/qcom/clk-hfpll.c                       | 244 +++++++++++++
 drivers/clk/qcom/clk-hfpll.h                       |  44 +++
 drivers/clk/qcom/clk-krait.c                       | 126 +++++++
 drivers/clk/qcom/clk-krait.h                       |  40 +++
 drivers/clk/qcom/gcc-ipq806x.c                     |  82 +++++
 drivers/clk/qcom/gcc-msm8960.c                     | 172 +++++++++
 drivers/clk/qcom/hfpll.c                           |  96 +++++
 drivers/clk/qcom/kpss-xcc.c                        |  87 +++++
 drivers/clk/qcom/krait-cc.c                        | 397 +++++++++++++++++++++
 drivers/cpufreq/Kconfig.arm                        |   6 +-
 drivers/cpufreq/Makefile                           |   2 +-
 drivers/cpufreq/cpufreq-dt-platdev.c               |   5 +
 drivers/cpufreq/qcom-cpufreq-kryo.c                | 232 ------------
 drivers/cpufreq/qcom-cpufreq-nvmem.c               | 387 ++++++++++++++++++++
 include/dt-bindings/clock/qcom,gcc-msm8960.h       |   2 +
 26 files changed, 1941 insertions(+), 239 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
 rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} (98%)
 create mode 100644 arch/arm/common/krait-l2-accessors.c
 create mode 100644 arch/arm/include/asm/krait-l2-accessors.h
 create mode 100644 drivers/clk/qcom/clk-hfpll.c
 create mode 100644 drivers/clk/qcom/clk-hfpll.h
 create mode 100644 drivers/clk/qcom/clk-krait.c
 create mode 100644 drivers/clk/qcom/clk-krait.h
 create mode 100644 drivers/clk/qcom/hfpll.c
 create mode 100644 drivers/clk/qcom/kpss-xcc.c
 create mode 100644 drivers/clk/qcom/krait-cc.c
 delete mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
 create mode 100644 drivers/cpufreq/qcom-cpufreq-nvmem.c

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH v12 01/14] ARM: Add Krait L2 register accessor functions
  2018-08-14 12:12 [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
@ 2018-08-14 12:12 ` Sricharan R
  2018-08-14 12:12 ` [PATCH v12 02/14] clk: qcom: Add support for High-Frequency PLLs (HFPLLs) Sricharan R
                   ` (13 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Sricharan R @ 2018-08-14 12:12 UTC (permalink / raw)
  To: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel
  Cc: sricharan

From: Stephen Boyd <sboyd@codeaurora.org>

Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write.  Then you
read/write the 'window' register to do what you want. The
l2cpselr register is not banked per-cpu so we must lock around
accesses to it to prevent other CPUs from re-pointing l2cpdr
underneath us.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
 arch/arm/common/Kconfig                   |  3 ++
 arch/arm/common/Makefile                  |  1 +
 arch/arm/common/krait-l2-accessors.c      | 48 +++++++++++++++++++++++++++++++
 arch/arm/include/asm/krait-l2-accessors.h |  9 ++++++
 4 files changed, 61 insertions(+)
 create mode 100644 arch/arm/common/krait-l2-accessors.c
 create mode 100644 arch/arm/include/asm/krait-l2-accessors.h

diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index e5ad070..c8e1986 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -7,6 +7,9 @@ config DMABOUNCE
 	bool
 	select ZONE_DMA
 
+config KRAIT_L2_ACCESSORS
+	bool
+
 config SHARP_LOCOMO
 	bool
 
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 3157be4..219a260 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -7,6 +7,7 @@ obj-y				+= firmware.o
 
 obj-$(CONFIG_SA1111)		+= sa1111.o
 obj-$(CONFIG_DMABOUNCE)		+= dmabounce.o
+obj-$(CONFIG_KRAIT_L2_ACCESSORS) += krait-l2-accessors.o
 obj-$(CONFIG_SHARP_LOCOMO)	+= locomo.o
 obj-$(CONFIG_SHARP_PARAM)	+= sharpsl_param.o
 obj-$(CONFIG_SHARP_SCOOP)	+= scoop.o
diff --git a/arch/arm/common/krait-l2-accessors.c b/arch/arm/common/krait-l2-accessors.c
new file mode 100644
index 0000000..9a97dda
--- /dev/null
+++ b/arch/arm/common/krait-l2-accessors.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include <linux/spinlock.h>
+#include <linux/export.h>
+
+#include <asm/barrier.h>
+#include <asm/krait-l2-accessors.h>
+
+static DEFINE_RAW_SPINLOCK(krait_l2_lock);
+
+void krait_set_l2_indirect_reg(u32 addr, u32 val)
+{
+	unsigned long flags;
+
+	raw_spin_lock_irqsave(&krait_l2_lock, flags);
+	/*
+	 * Select the L2 window by poking l2cpselr, then write to the window
+	 * via l2cpdr.
+	 */
+	asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr));
+	isb();
+	asm volatile ("mcr p15, 3, %0, c15, c0, 7 @ l2cpdr" : : "r" (val));
+	isb();
+
+	raw_spin_unlock_irqrestore(&krait_l2_lock, flags);
+}
+EXPORT_SYMBOL(krait_set_l2_indirect_reg);
+
+u32 krait_get_l2_indirect_reg(u32 addr)
+{
+	u32 val;
+	unsigned long flags;
+
+	raw_spin_lock_irqsave(&krait_l2_lock, flags);
+	/*
+	 * Select the L2 window by poking l2cpselr, then read from the window
+	 * via l2cpdr.
+	 */
+	asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr));
+	isb();
+	asm volatile ("mrc p15, 3, %0, c15, c0, 7 @ l2cpdr" : "=r" (val));
+
+	raw_spin_unlock_irqrestore(&krait_l2_lock, flags);
+
+	return val;
+}
+EXPORT_SYMBOL(krait_get_l2_indirect_reg);
diff --git a/arch/arm/include/asm/krait-l2-accessors.h b/arch/arm/include/asm/krait-l2-accessors.h
new file mode 100644
index 0000000..a5f2cdd
--- /dev/null
+++ b/arch/arm/include/asm/krait-l2-accessors.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASMARM_KRAIT_L2_ACCESSORS_H
+#define __ASMARM_KRAIT_L2_ACCESSORS_H
+
+extern void krait_set_l2_indirect_reg(u32 addr, u32 val);
+extern u32 krait_get_l2_indirect_reg(u32 addr);
+
+#endif
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH v12 02/14] clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
  2018-08-14 12:12 [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
  2018-08-14 12:12 ` [PATCH v12 01/14] ARM: Add Krait L2 register accessor functions Sricharan R
@ 2018-08-14 12:12 ` Sricharan R
  2018-08-14 12:12 ` [PATCH v12 03/14] clk: qcom: Add HFPLL driver Sricharan R
                   ` (12 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Sricharan R @ 2018-08-14 12:12 UTC (permalink / raw)
  To: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel
  Cc: sricharan

From: Stephen Boyd <sboyd@codeaurora.org>

HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
 drivers/clk/qcom/Makefile    |   1 +
 drivers/clk/qcom/clk-hfpll.c | 244 +++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/qcom/clk-hfpll.h |  44 ++++++++
 3 files changed, 289 insertions(+)
 create mode 100644 drivers/clk/qcom/clk-hfpll.c
 create mode 100644 drivers/clk/qcom/clk-hfpll.h

diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 21a4503..7818e6c 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -11,6 +11,7 @@ clk-qcom-y += clk-branch.o
 clk-qcom-y += clk-regmap-divider.o
 clk-qcom-y += clk-regmap-mux.o
 clk-qcom-y += clk-regmap-mux-div.o
+clk-qcom-y += clk-hfpll.o
 clk-qcom-y += reset.o
 clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
 
diff --git a/drivers/clk/qcom/clk-hfpll.c b/drivers/clk/qcom/clk-hfpll.c
new file mode 100644
index 0000000..3c04805
--- /dev/null
+++ b/drivers/clk/qcom/clk-hfpll.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include <linux/kernel.h>
+#include <linux/export.h>
+#include <linux/regmap.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/clk-provider.h>
+#include <linux/spinlock.h>
+
+#include "clk-regmap.h"
+#include "clk-hfpll.h"
+
+#define PLL_OUTCTRL	BIT(0)
+#define PLL_BYPASSNL	BIT(1)
+#define PLL_RESET_N	BIT(2)
+
+/* Initialize a HFPLL at a given rate and enable it. */
+static void __clk_hfpll_init_once(struct clk_hw *hw)
+{
+	struct clk_hfpll *h = to_clk_hfpll(hw);
+	struct hfpll_data const *hd = h->d;
+	struct regmap *regmap = h->clkr.regmap;
+
+	if (likely(h->init_done))
+		return;
+
+	/* Configure PLL parameters for integer mode. */
+	if (hd->config_val)
+		regmap_write(regmap, hd->config_reg, hd->config_val);
+	regmap_write(regmap, hd->m_reg, 0);
+	regmap_write(regmap, hd->n_reg, 1);
+
+	if (hd->user_reg) {
+		u32 regval = hd->user_val;
+		unsigned long rate;
+
+		rate = clk_hw_get_rate(hw);
+
+		/* Pick the right VCO. */
+		if (hd->user_vco_mask && rate > hd->low_vco_max_rate)
+			regval |= hd->user_vco_mask;
+		regmap_write(regmap, hd->user_reg, regval);
+	}
+
+	if (hd->droop_reg)
+		regmap_write(regmap, hd->droop_reg, hd->droop_val);
+
+	h->init_done = true;
+}
+
+static void __clk_hfpll_enable(struct clk_hw *hw)
+{
+	struct clk_hfpll *h = to_clk_hfpll(hw);
+	struct hfpll_data const *hd = h->d;
+	struct regmap *regmap = h->clkr.regmap;
+	u32 val;
+
+	__clk_hfpll_init_once(hw);
+
+	/* Disable PLL bypass mode. */
+	regmap_update_bits(regmap, hd->mode_reg, PLL_BYPASSNL, PLL_BYPASSNL);
+
+	/*
+	 * H/W requires a 5us delay between disabling the bypass and
+	 * de-asserting the reset. Delay 10us just to be safe.
+	 */
+	udelay(10);
+
+	/* De-assert active-low PLL reset. */
+	regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
+
+	/* Wait for PLL to lock. */
+	if (hd->status_reg) {
+		do {
+			regmap_read(regmap, hd->status_reg, &val);
+		} while (!(val & BIT(hd->lock_bit)));
+	} else {
+		udelay(60);
+	}
+
+	/* Enable PLL output. */
+	regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL);
+}
+
+/* Enable an already-configured HFPLL. */
+static int clk_hfpll_enable(struct clk_hw *hw)
+{
+	unsigned long flags;
+	struct clk_hfpll *h = to_clk_hfpll(hw);
+	struct hfpll_data const *hd = h->d;
+	struct regmap *regmap = h->clkr.regmap;
+	u32 mode;
+
+	spin_lock_irqsave(&h->lock, flags);
+	regmap_read(regmap, hd->mode_reg, &mode);
+	if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)))
+		__clk_hfpll_enable(hw);
+	spin_unlock_irqrestore(&h->lock, flags);
+
+	return 0;
+}
+
+static void __clk_hfpll_disable(struct clk_hfpll *h)
+{
+	struct hfpll_data const *hd = h->d;
+	struct regmap *regmap = h->clkr.regmap;
+
+	/*
+	 * Disable the PLL output, disable test mode, enable the bypass mode,
+	 * and assert the reset.
+	 */
+	regmap_update_bits(regmap, hd->mode_reg,
+			   PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0);
+}
+
+static void clk_hfpll_disable(struct clk_hw *hw)
+{
+	struct clk_hfpll *h = to_clk_hfpll(hw);
+	unsigned long flags;
+
+	spin_lock_irqsave(&h->lock, flags);
+	__clk_hfpll_disable(h);
+	spin_unlock_irqrestore(&h->lock, flags);
+}
+
+static long clk_hfpll_round_rate(struct clk_hw *hw, unsigned long rate,
+				 unsigned long *parent_rate)
+{
+	struct clk_hfpll *h = to_clk_hfpll(hw);
+	struct hfpll_data const *hd = h->d;
+	unsigned long rrate;
+
+	rate = clamp(rate, hd->min_rate, hd->max_rate);
+
+	rrate = DIV_ROUND_UP(rate, *parent_rate) * *parent_rate;
+	if (rrate > hd->max_rate)
+		rrate -= *parent_rate;
+
+	return rrate;
+}
+
+/*
+ * For optimization reasons, assumes no downstream clocks are actively using
+ * it.
+ */
+static int clk_hfpll_set_rate(struct clk_hw *hw, unsigned long rate,
+			      unsigned long parent_rate)
+{
+	struct clk_hfpll *h = to_clk_hfpll(hw);
+	struct hfpll_data const *hd = h->d;
+	struct regmap *regmap = h->clkr.regmap;
+	unsigned long flags;
+	u32 l_val, val;
+	bool enabled;
+
+	l_val = rate / parent_rate;
+
+	spin_lock_irqsave(&h->lock, flags);
+
+	enabled = __clk_is_enabled(hw->clk);
+	if (enabled)
+		__clk_hfpll_disable(h);
+
+	/* Pick the right VCO. */
+	if (hd->user_reg && hd->user_vco_mask) {
+		regmap_read(regmap, hd->user_reg, &val);
+		if (rate <= hd->low_vco_max_rate)
+			val &= ~hd->user_vco_mask;
+		else
+			val |= hd->user_vco_mask;
+		regmap_write(regmap, hd->user_reg, val);
+	}
+
+	regmap_write(regmap, hd->l_reg, l_val);
+
+	if (enabled)
+		__clk_hfpll_enable(hw);
+
+	spin_unlock_irqrestore(&h->lock, flags);
+
+	return 0;
+}
+
+static unsigned long clk_hfpll_recalc_rate(struct clk_hw *hw,
+					   unsigned long parent_rate)
+{
+	struct clk_hfpll *h = to_clk_hfpll(hw);
+	struct hfpll_data const *hd = h->d;
+	struct regmap *regmap = h->clkr.regmap;
+	u32 l_val;
+
+	regmap_read(regmap, hd->l_reg, &l_val);
+
+	return l_val * parent_rate;
+}
+
+static void clk_hfpll_init(struct clk_hw *hw)
+{
+	struct clk_hfpll *h = to_clk_hfpll(hw);
+	struct hfpll_data const *hd = h->d;
+	struct regmap *regmap = h->clkr.regmap;
+	u32 mode, status;
+
+	regmap_read(regmap, hd->mode_reg, &mode);
+	if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) {
+		__clk_hfpll_init_once(hw);
+		return;
+	}
+
+	if (hd->status_reg) {
+		regmap_read(regmap, hd->status_reg, &status);
+		if (!(status & BIT(hd->lock_bit))) {
+			WARN(1, "HFPLL %s is ON, but not locked!\n",
+			     __clk_get_name(hw->clk));
+			clk_hfpll_disable(hw);
+			__clk_hfpll_init_once(hw);
+		}
+	}
+}
+
+static int hfpll_is_enabled(struct clk_hw *hw)
+{
+	struct clk_hfpll *h = to_clk_hfpll(hw);
+	struct hfpll_data const *hd = h->d;
+	struct regmap *regmap = h->clkr.regmap;
+	u32 mode;
+
+	regmap_read(regmap, hd->mode_reg, &mode);
+	mode &= 0x7;
+	return mode == (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL);
+}
+
+const struct clk_ops clk_ops_hfpll = {
+	.enable = clk_hfpll_enable,
+	.disable = clk_hfpll_disable,
+	.is_enabled = hfpll_is_enabled,
+	.round_rate = clk_hfpll_round_rate,
+	.set_rate = clk_hfpll_set_rate,
+	.recalc_rate = clk_hfpll_recalc_rate,
+	.init = clk_hfpll_init,
+};
+EXPORT_SYMBOL_GPL(clk_ops_hfpll);
diff --git a/drivers/clk/qcom/clk-hfpll.h b/drivers/clk/qcom/clk-hfpll.h
new file mode 100644
index 0000000..2a57b2f
--- /dev/null
+++ b/drivers/clk/qcom/clk-hfpll.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __QCOM_CLK_HFPLL_H__
+#define __QCOM_CLK_HFPLL_H__
+
+#include <linux/clk-provider.h>
+#include <linux/spinlock.h>
+#include "clk-regmap.h"
+
+struct hfpll_data {
+	u32 mode_reg;
+	u32 l_reg;
+	u32 m_reg;
+	u32 n_reg;
+	u32 user_reg;
+	u32 droop_reg;
+	u32 config_reg;
+	u32 status_reg;
+	u8  lock_bit;
+
+	u32 droop_val;
+	u32 config_val;
+	u32 user_val;
+	u32 user_vco_mask;
+	unsigned long low_vco_max_rate;
+
+	unsigned long min_rate;
+	unsigned long max_rate;
+};
+
+struct clk_hfpll {
+	struct hfpll_data const *d;
+	int init_done;
+
+	struct clk_regmap clkr;
+	spinlock_t lock;
+};
+
+#define to_clk_hfpll(_hw) \
+	container_of(to_clk_regmap(_hw), struct clk_hfpll, clkr)
+
+extern const struct clk_ops clk_ops_hfpll;
+
+#endif
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH v12 03/14] clk: qcom: Add HFPLL driver
  2018-08-14 12:12 [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
  2018-08-14 12:12 ` [PATCH v12 01/14] ARM: Add Krait L2 register accessor functions Sricharan R
  2018-08-14 12:12 ` [PATCH v12 02/14] clk: qcom: Add support for High-Frequency PLLs (HFPLLs) Sricharan R
@ 2018-08-14 12:12 ` Sricharan R
  2018-08-14 12:12 ` [PATCH v12 04/14] dt-bindings: clock: Document qcom,hfpll Sricharan R
                   ` (11 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Sricharan R @ 2018-08-14 12:12 UTC (permalink / raw)
  To: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel
  Cc: sricharan

From: Stephen Boyd <sboyd@codeaurora.org>

On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
 drivers/clk/qcom/Kconfig  |  8 ++++
 drivers/clk/qcom/Makefile |  1 +
 drivers/clk/qcom/hfpll.c  | 96 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 105 insertions(+)
 create mode 100644 drivers/clk/qcom/hfpll.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 0647686..21aec10 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -272,3 +272,11 @@ config SPMI_PMIC_CLKDIV
 	  Technologies, Inc. SPMI PMIC. It configures the frequency of
 	  clkdiv outputs of the PMIC. These clocks are typically wired
 	  through alternate functions on GPIO pins.
+
+config QCOM_HFPLL
+	tristate "High-Frequency PLL (HFPLL) Clock Controller"
+	depends on COMMON_CLK_QCOM
+	help
+	  Support for the high-frequency PLLs present on Qualcomm devices.
+	  Say Y if you want to support CPU frequency scaling on devices
+	  such as MSM8974, APQ8084, etc.
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 7818e6c..f82eeac 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
 obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
 obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
 obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
+obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
new file mode 100644
index 0000000..a6de7101
--- /dev/null
+++ b/drivers/clk/qcom/hfpll.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+
+#include "clk-regmap.h"
+#include "clk-hfpll.h"
+
+static const struct hfpll_data hdata = {
+	.mode_reg = 0x00,
+	.l_reg = 0x04,
+	.m_reg = 0x08,
+	.n_reg = 0x0c,
+	.user_reg = 0x10,
+	.config_reg = 0x14,
+	.config_val = 0x430405d,
+	.status_reg = 0x1c,
+	.lock_bit = 16,
+
+	.user_val = 0x8,
+	.user_vco_mask = 0x100000,
+	.low_vco_max_rate = 1248000000,
+	.min_rate = 537600000UL,
+	.max_rate = 2900000000UL,
+};
+
+static const struct of_device_id qcom_hfpll_match_table[] = {
+	{ .compatible = "qcom,hfpll" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
+
+static const struct regmap_config hfpll_regmap_config = {
+	.reg_bits	= 32,
+	.reg_stride	= 4,
+	.val_bits	= 32,
+	.max_register	= 0x30,
+	.fast_io	= true,
+};
+
+static int qcom_hfpll_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct device *dev = &pdev->dev;
+	void __iomem *base;
+	struct regmap *regmap;
+	struct clk_hfpll *h;
+	struct clk_init_data init = {
+		.parent_names = (const char *[]){ "xo" },
+		.num_parents = 1,
+		.ops = &clk_ops_hfpll,
+	};
+
+	h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
+	if (!h)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config);
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	if (of_property_read_string_index(dev->of_node, "clock-output-names",
+					  0, &init.name))
+		return -ENODEV;
+
+	h->d = &hdata;
+	h->clkr.hw.init = &init;
+	spin_lock_init(&h->lock);
+
+	return devm_clk_register_regmap(&pdev->dev, &h->clkr);
+}
+
+static struct platform_driver qcom_hfpll_driver = {
+	.probe		= qcom_hfpll_probe,
+	.driver		= {
+		.name	= "qcom-hfpll",
+		.of_match_table = qcom_hfpll_match_table,
+	},
+};
+module_platform_driver(qcom_hfpll_driver);
+
+MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:qcom-hfpll");
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH v12 04/14] dt-bindings: clock: Document qcom,hfpll
  2018-08-14 12:12 [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
                   ` (2 preceding siblings ...)
  2018-08-14 12:12 ` [PATCH v12 03/14] clk: qcom: Add HFPLL driver Sricharan R
@ 2018-08-14 12:12 ` Sricharan R
  2018-08-14 12:12 ` [PATCH v12 05/14] clk: qcom: Add MSM8960/APQ8064's HFPLLs Sricharan R
                   ` (10 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Sricharan R @ 2018-08-14 12:12 UTC (permalink / raw)
  To: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel
  Cc: sricharan

From: Stephen Boyd <sboyd@codeaurora.org>

Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
 .../devicetree/bindings/clock/qcom,hfpll.txt       | 60 ++++++++++++++++++++++
 1 file changed, 60 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt

diff --git a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
new file mode 100644
index 0000000..ec02a02
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
@@ -0,0 +1,60 @@
+High-Frequency PLL (HFPLL)
+
+PROPERTIES
+
+- compatible:
+	Usage: required
+	Value type: <string>:
+		shall contain only one of the following. The generic
+		compatible "qcom,hfpll" should be also included.
+
+                        "qcom,hfpll-ipq8064", "qcom,hfpll"
+                        "qcom,hfpll-apq8064", "qcom,hfpll"
+                        "qcom,hfpll-msm8974", "qcom,hfpll"
+                        "qcom,hfpll-msm8960", "qcom,hfpll"
+
+- reg:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: address and size of HPLL registers. An optional second
+		    element specifies the address and size of the alias
+		    register region.
+
+- clocks:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: reference to the xo clock.
+
+- clock-names:
+	Usage: required
+	Value type: <stringlist>
+	Definition: must be "xo".
+
+- clock-output-names:
+	Usage: required
+	Value type: <string>
+	Definition: Name of the PLL. Typically hfpllX where X is a CPU number
+		    starting at 0. Otherwise hfpll_Y where Y is more specific
+		    such as "l2".
+
+Example:
+
+1) An HFPLL for the L2 cache.
+
+	clock-controller@f9016000 {
+		compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
+		reg = <0xf9016000 0x30>;
+		clocks = <&xo_board>;
+		clock-names = "xo";
+		clock-output-names = "hfpll_l2";
+	};
+
+2) An HFPLL for CPU0. This HFPLL has the alias register region.
+
+	clock-controller@f908a000 {
+		compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
+		reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
+		clocks = <&xo_board>;
+		clock-names = "xo";
+		clock-output-names = "hfpll0";
+	};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH v12 05/14] clk: qcom: Add MSM8960/APQ8064's HFPLLs
  2018-08-14 12:12 [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
                   ` (3 preceding siblings ...)
  2018-08-14 12:12 ` [PATCH v12 04/14] dt-bindings: clock: Document qcom,hfpll Sricharan R
@ 2018-08-14 12:12 ` Sricharan R
  2018-08-14 12:12 ` [PATCH v12 06/14] clk: qcom: Add IPQ806X's HFPLLs Sricharan R
                   ` (9 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Sricharan R @ 2018-08-14 12:12 UTC (permalink / raw)
  To: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel
  Cc: sricharan

From: Stephen Boyd <sboyd@codeaurora.org>

Describe the HFPLLs present on MSM8960 and APQ8064 devices.

Acked-by: Rob Herring <robh@kernel.org> (bindings)
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
 drivers/clk/qcom/gcc-msm8960.c               | 172 +++++++++++++++++++++++++++
 include/dt-bindings/clock/qcom,gcc-msm8960.h |   2 +
 2 files changed, 174 insertions(+)

diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index fd495e0..3994747 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -30,6 +30,7 @@
 #include "clk-pll.h"
 #include "clk-rcg.h"
 #include "clk-branch.h"
+#include "clk-hfpll.h"
 #include "reset.h"
 
 static struct clk_pll pll3 = {
@@ -86,6 +87,164 @@
 	},
 };
 
+static struct hfpll_data hfpll0_data = {
+	.mode_reg = 0x3200,
+	.l_reg = 0x3208,
+	.m_reg = 0x320c,
+	.n_reg = 0x3210,
+	.config_reg = 0x3204,
+	.status_reg = 0x321c,
+	.config_val = 0x7845c665,
+	.droop_reg = 0x3214,
+	.droop_val = 0x0108c000,
+	.min_rate = 600000000UL,
+	.max_rate = 1800000000UL,
+};
+
+static struct clk_hfpll hfpll0 = {
+	.d = &hfpll0_data,
+	.clkr.hw.init = &(struct clk_init_data){
+		.parent_names = (const char *[]){ "pxo" },
+		.num_parents = 1,
+		.name = "hfpll0",
+		.ops = &clk_ops_hfpll,
+		.flags = CLK_IGNORE_UNUSED,
+	},
+	.lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
+};
+
+static struct hfpll_data hfpll1_8064_data = {
+	.mode_reg = 0x3240,
+	.l_reg = 0x3248,
+	.m_reg = 0x324c,
+	.n_reg = 0x3250,
+	.config_reg = 0x3244,
+	.status_reg = 0x325c,
+	.config_val = 0x7845c665,
+	.droop_reg = 0x3254,
+	.droop_val = 0x0108c000,
+	.min_rate = 600000000UL,
+	.max_rate = 1800000000UL,
+};
+
+static struct hfpll_data hfpll1_data = {
+	.mode_reg = 0x3300,
+	.l_reg = 0x3308,
+	.m_reg = 0x330c,
+	.n_reg = 0x3310,
+	.config_reg = 0x3304,
+	.status_reg = 0x331c,
+	.config_val = 0x7845c665,
+	.droop_reg = 0x3314,
+	.droop_val = 0x0108c000,
+	.min_rate = 600000000UL,
+	.max_rate = 1800000000UL,
+};
+
+static struct clk_hfpll hfpll1 = {
+	.d = &hfpll1_data,
+	.clkr.hw.init = &(struct clk_init_data){
+		.parent_names = (const char *[]){ "pxo" },
+		.num_parents = 1,
+		.name = "hfpll1",
+		.ops = &clk_ops_hfpll,
+		.flags = CLK_IGNORE_UNUSED,
+	},
+	.lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
+};
+
+static struct hfpll_data hfpll2_data = {
+	.mode_reg = 0x3280,
+	.l_reg = 0x3288,
+	.m_reg = 0x328c,
+	.n_reg = 0x3290,
+	.config_reg = 0x3284,
+	.status_reg = 0x329c,
+	.config_val = 0x7845c665,
+	.droop_reg = 0x3294,
+	.droop_val = 0x0108c000,
+	.min_rate = 600000000UL,
+	.max_rate = 1800000000UL,
+};
+
+static struct clk_hfpll hfpll2 = {
+	.d = &hfpll2_data,
+	.clkr.hw.init = &(struct clk_init_data){
+		.parent_names = (const char *[]){ "pxo" },
+		.num_parents = 1,
+		.name = "hfpll2",
+		.ops = &clk_ops_hfpll,
+		.flags = CLK_IGNORE_UNUSED,
+	},
+	.lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
+};
+
+static struct hfpll_data hfpll3_data = {
+	.mode_reg = 0x32c0,
+	.l_reg = 0x32c8,
+	.m_reg = 0x32cc,
+	.n_reg = 0x32d0,
+	.config_reg = 0x32c4,
+	.status_reg = 0x32dc,
+	.config_val = 0x7845c665,
+	.droop_reg = 0x32d4,
+	.droop_val = 0x0108c000,
+	.min_rate = 600000000UL,
+	.max_rate = 1800000000UL,
+};
+
+static struct clk_hfpll hfpll3 = {
+	.d = &hfpll3_data,
+	.clkr.hw.init = &(struct clk_init_data){
+		.parent_names = (const char *[]){ "pxo" },
+		.num_parents = 1,
+		.name = "hfpll3",
+		.ops = &clk_ops_hfpll,
+		.flags = CLK_IGNORE_UNUSED,
+	},
+	.lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
+};
+
+static struct hfpll_data hfpll_l2_8064_data = {
+	.mode_reg = 0x3300,
+	.l_reg = 0x3308,
+	.m_reg = 0x330c,
+	.n_reg = 0x3310,
+	.config_reg = 0x3304,
+	.status_reg = 0x331c,
+	.config_val = 0x7845c665,
+	.droop_reg = 0x3314,
+	.droop_val = 0x0108c000,
+	.min_rate = 600000000UL,
+	.max_rate = 1800000000UL,
+};
+
+static struct hfpll_data hfpll_l2_data = {
+	.mode_reg = 0x3400,
+	.l_reg = 0x3408,
+	.m_reg = 0x340c,
+	.n_reg = 0x3410,
+	.config_reg = 0x3404,
+	.status_reg = 0x341c,
+	.config_val = 0x7845c665,
+	.droop_reg = 0x3414,
+	.droop_val = 0x0108c000,
+	.min_rate = 600000000UL,
+	.max_rate = 1800000000UL,
+};
+
+static struct clk_hfpll hfpll_l2 = {
+	.d = &hfpll_l2_data,
+	.clkr.hw.init = &(struct clk_init_data){
+		.parent_names = (const char *[]){ "pxo" },
+		.num_parents = 1,
+		.name = "hfpll_l2",
+		.ops = &clk_ops_hfpll,
+		.flags = CLK_IGNORE_UNUSED,
+	},
+	.lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
+};
+
 static struct clk_pll pll14 = {
 	.l_reg = 0x31c4,
 	.m_reg = 0x31c8,
@@ -3107,6 +3266,9 @@ enum {
 	[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
 	[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
 	[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
+	[PLL9] = &hfpll0.clkr,
+	[PLL10] = &hfpll1.clkr,
+	[PLL12] = &hfpll_l2.clkr,
 };
 
 static const struct qcom_reset_map gcc_msm8960_resets[] = {
@@ -3318,6 +3480,11 @@ enum {
 	[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
 	[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
 	[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
+	[PLL9] = &hfpll0.clkr,
+	[PLL10] = &hfpll1.clkr,
+	[PLL12] = &hfpll_l2.clkr,
+	[PLL16] = &hfpll2.clkr,
+	[PLL17] = &hfpll3.clkr,
 };
 
 static const struct qcom_reset_map gcc_apq8064_resets[] = {
@@ -3477,6 +3644,11 @@ static int gcc_msm8960_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
+	if (match->data == &gcc_apq8064_desc) {
+		hfpll1.d = &hfpll1_8064_data;
+		hfpll_l2.d = &hfpll_l2_8064_data;
+	}
+
 	tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
 					      NULL, 0);
 	if (IS_ERR(tsens))
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8960.h b/include/dt-bindings/clock/qcom,gcc-msm8960.h
index 7d20eed..e02742f 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8960.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8960.h
@@ -319,5 +319,7 @@
 #define CE3_SRC					303
 #define CE3_CORE_CLK				304
 #define CE3_H_CLK				305
+#define PLL16					306
+#define PLL17					307
 
 #endif
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH v12 06/14] clk: qcom: Add IPQ806X's HFPLLs
  2018-08-14 12:12 [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
                   ` (4 preceding siblings ...)
  2018-08-14 12:12 ` [PATCH v12 05/14] clk: qcom: Add MSM8960/APQ8064's HFPLLs Sricharan R
@ 2018-08-14 12:12 ` Sricharan R
  2018-08-14 12:12 ` [PATCH v12 07/14] clk: qcom: Add support for Krait clocks Sricharan R
                   ` (8 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Sricharan R @ 2018-08-14 12:12 UTC (permalink / raw)
  To: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel
  Cc: sricharan

From: Stephen Boyd <sboyd@codeaurora.org>

Describe the HFPLLs present on IPQ806X devices.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq806x.c | 82 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 5f61225..33d1bc5 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -30,6 +30,7 @@
 #include "clk-pll.h"
 #include "clk-rcg.h"
 #include "clk-branch.h"
+#include "clk-hfpll.h"
 #include "reset.h"
 
 static struct clk_pll pll0 = {
@@ -113,6 +114,84 @@
 	},
 };
 
+static struct hfpll_data hfpll0_data = {
+	.mode_reg = 0x3200,
+	.l_reg = 0x3208,
+	.m_reg = 0x320c,
+	.n_reg = 0x3210,
+	.config_reg = 0x3204,
+	.status_reg = 0x321c,
+	.config_val = 0x7845c665,
+	.droop_reg = 0x3214,
+	.droop_val = 0x0108c000,
+	.min_rate = 600000000UL,
+	.max_rate = 1800000000UL,
+};
+
+static struct clk_hfpll hfpll0 = {
+	.d = &hfpll0_data,
+	.clkr.hw.init = &(struct clk_init_data){
+		.parent_names = (const char *[]){ "pxo" },
+		.num_parents = 1,
+		.name = "hfpll0",
+		.ops = &clk_ops_hfpll,
+		.flags = CLK_IGNORE_UNUSED,
+	},
+	.lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
+};
+
+static struct hfpll_data hfpll1_data = {
+	.mode_reg = 0x3240,
+	.l_reg = 0x3248,
+	.m_reg = 0x324c,
+	.n_reg = 0x3250,
+	.config_reg = 0x3244,
+	.status_reg = 0x325c,
+	.config_val = 0x7845c665,
+	.droop_reg = 0x3314,
+	.droop_val = 0x0108c000,
+	.min_rate = 600000000UL,
+	.max_rate = 1800000000UL,
+};
+
+static struct clk_hfpll hfpll1 = {
+	.d = &hfpll1_data,
+	.clkr.hw.init = &(struct clk_init_data){
+		.parent_names = (const char *[]){ "pxo" },
+		.num_parents = 1,
+		.name = "hfpll1",
+		.ops = &clk_ops_hfpll,
+		.flags = CLK_IGNORE_UNUSED,
+	},
+	.lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
+};
+
+static struct hfpll_data hfpll_l2_data = {
+	.mode_reg = 0x3300,
+	.l_reg = 0x3308,
+	.m_reg = 0x330c,
+	.n_reg = 0x3310,
+	.config_reg = 0x3304,
+	.status_reg = 0x331c,
+	.config_val = 0x7845c665,
+	.droop_reg = 0x3314,
+	.droop_val = 0x0108c000,
+	.min_rate = 600000000UL,
+	.max_rate = 1800000000UL,
+};
+
+static struct clk_hfpll hfpll_l2 = {
+	.d = &hfpll_l2_data,
+	.clkr.hw.init = &(struct clk_init_data){
+		.parent_names = (const char *[]){ "pxo" },
+		.num_parents = 1,
+		.name = "hfpll_l2",
+		.ops = &clk_ops_hfpll,
+		.flags = CLK_IGNORE_UNUSED,
+	},
+	.lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
+};
+
 static struct clk_pll pll14 = {
 	.l_reg = 0x31c4,
 	.m_reg = 0x31c8,
@@ -2797,6 +2876,9 @@ enum {
 	[UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
 	[NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
 	[NSSTCM_CLK] = &nss_tcm_clk.clkr,
+	[PLL9] = &hfpll0.clkr,
+	[PLL10] = &hfpll1.clkr,
+	[PLL12] = &hfpll_l2.clkr,
 };
 
 static const struct qcom_reset_map gcc_ipq806x_resets[] = {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH v12 07/14] clk: qcom: Add support for Krait clocks
  2018-08-14 12:12 [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
                   ` (5 preceding siblings ...)
  2018-08-14 12:12 ` [PATCH v12 06/14] clk: qcom: Add IPQ806X's HFPLLs Sricharan R
@ 2018-08-14 12:12 ` Sricharan R
  2018-08-14 12:12 ` [PATCH v12 08/14] clk: qcom: Add KPSS ACC/GCC driver Sricharan R
                   ` (7 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Sricharan R @ 2018-08-14 12:12 UTC (permalink / raw)
  To: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel
  Cc: sricharan

From: Stephen Boyd <sboyd@codeaurora.org>

The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
 drivers/clk/qcom/Kconfig     |   4 ++
 drivers/clk/qcom/Makefile    |   1 +
 drivers/clk/qcom/clk-krait.c | 124 +++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/qcom/clk-krait.h |  37 +++++++++++++
 4 files changed, 166 insertions(+)
 create mode 100644 drivers/clk/qcom/clk-krait.c
 create mode 100644 drivers/clk/qcom/clk-krait.h

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 21aec10..ada4160 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -280,3 +280,7 @@ config QCOM_HFPLL
 	  Support for the high-frequency PLLs present on Qualcomm devices.
 	  Say Y if you want to support CPU frequency scaling on devices
 	  such as MSM8974, APQ8084, etc.
+
+config KRAIT_CLOCKS
+	bool
+	select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index f82eeac..506c4cf 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -11,6 +11,7 @@ clk-qcom-y += clk-branch.o
 clk-qcom-y += clk-regmap-divider.o
 clk-qcom-y += clk-regmap-mux.o
 clk-qcom-y += clk-regmap-mux-div.o
+clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
 clk-qcom-y += clk-hfpll.o
 clk-qcom-y += reset.o
 clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
new file mode 100644
index 0000000..2e41767
--- /dev/null
+++ b/drivers/clk/qcom/clk-krait.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/clk-provider.h>
+#include <linux/spinlock.h>
+
+#include <asm/krait-l2-accessors.h>
+
+#include "clk-krait.h"
+
+/* Secondary and primary muxes share the same cp15 register */
+static DEFINE_SPINLOCK(krait_clock_reg_lock);
+
+#define LPL_SHIFT	8
+static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel)
+{
+	unsigned long flags;
+	u32 regval;
+
+	spin_lock_irqsave(&krait_clock_reg_lock, flags);
+	regval = krait_get_l2_indirect_reg(mux->offset);
+	regval &= ~(mux->mask << mux->shift);
+	regval |= (sel & mux->mask) << mux->shift;
+	if (mux->lpl) {
+		regval &= ~(mux->mask << (mux->shift + LPL_SHIFT));
+		regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT);
+	}
+	krait_set_l2_indirect_reg(mux->offset, regval);
+	spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
+
+	/* Wait for switch to complete. */
+	mb();
+	udelay(1);
+}
+
+static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct krait_mux_clk *mux = to_krait_mux_clk(hw);
+	u32 sel;
+
+	sel = clk_mux_reindex(index, mux->parent_map, 0);
+	mux->en_mask = sel;
+	/* Don't touch mux if CPU is off as it won't work */
+	if (__clk_is_enabled(hw->clk))
+		__krait_mux_set_sel(mux, sel);
+
+	return 0;
+}
+
+static u8 krait_mux_get_parent(struct clk_hw *hw)
+{
+	struct krait_mux_clk *mux = to_krait_mux_clk(hw);
+	u32 sel;
+
+	sel = krait_get_l2_indirect_reg(mux->offset);
+	sel >>= mux->shift;
+	sel &= mux->mask;
+	mux->en_mask = sel;
+
+	return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
+}
+
+const struct clk_ops krait_mux_clk_ops = {
+	.set_parent = krait_mux_set_parent,
+	.get_parent = krait_mux_get_parent,
+	.determine_rate = __clk_mux_determine_rate_closest,
+};
+EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
+
+/* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
+static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
+				  unsigned long *parent_rate)
+{
+	*parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
+	return DIV_ROUND_UP(*parent_rate, 2);
+}
+
+static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
+			       unsigned long parent_rate)
+{
+	struct krait_div2_clk *d = to_krait_div2_clk(hw);
+	unsigned long flags;
+	u32 val;
+	u32 mask = BIT(d->width) - 1;
+
+	if (d->lpl)
+		mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
+
+	spin_lock_irqsave(&krait_clock_reg_lock, flags);
+	val = krait_get_l2_indirect_reg(d->offset);
+	val &= ~mask;
+	krait_set_l2_indirect_reg(d->offset, val);
+	spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
+
+	return 0;
+}
+
+static unsigned long
+krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+	struct krait_div2_clk *d = to_krait_div2_clk(hw);
+	u32 mask = BIT(d->width) - 1;
+	u32 div;
+
+	div = krait_get_l2_indirect_reg(d->offset);
+	div >>= d->shift;
+	div &= mask;
+	div = (div + 1) * 2;
+
+	return DIV_ROUND_UP(parent_rate, div);
+}
+
+const struct clk_ops krait_div2_clk_ops = {
+	.round_rate = krait_div2_round_rate,
+	.set_rate = krait_div2_set_rate,
+	.recalc_rate = krait_div2_recalc_rate,
+};
+EXPORT_SYMBOL_GPL(krait_div2_clk_ops);
diff --git a/drivers/clk/qcom/clk-krait.h b/drivers/clk/qcom/clk-krait.h
new file mode 100644
index 0000000..441ba1e
--- /dev/null
+++ b/drivers/clk/qcom/clk-krait.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __QCOM_CLK_KRAIT_H
+#define __QCOM_CLK_KRAIT_H
+
+#include <linux/clk-provider.h>
+
+struct krait_mux_clk {
+	unsigned int	*parent_map;
+	u32		offset;
+	u32		mask;
+	u32		shift;
+	u32		en_mask;
+	bool		lpl;
+
+	struct clk_hw	hw;
+	struct notifier_block   clk_nb;
+};
+
+#define to_krait_mux_clk(_hw) container_of(_hw, struct krait_mux_clk, hw)
+
+extern const struct clk_ops krait_mux_clk_ops;
+
+struct krait_div2_clk {
+	u32		offset;
+	u8		width;
+	u32		shift;
+	bool		lpl;
+
+	struct clk_hw	hw;
+};
+
+#define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw)
+
+extern const struct clk_ops krait_div2_clk_ops;
+
+#endif
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH v12 08/14] clk: qcom: Add KPSS ACC/GCC driver
  2018-08-14 12:12 [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
                   ` (6 preceding siblings ...)
  2018-08-14 12:12 ` [PATCH v12 07/14] clk: qcom: Add support for Krait clocks Sricharan R
@ 2018-08-14 12:12 ` Sricharan R
  2018-08-14 12:12 ` [PATCH v12 09/14] dt-bindings: arm: Document qcom,kpss-gcc Sricharan R
                   ` (6 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Sricharan R @ 2018-08-14 12:12 UTC (permalink / raw)
  To: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel
  Cc: sricharan

From: Stephen Boyd <sboyd@codeaurora.org>

The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
 drivers/clk/qcom/Kconfig    |  8 +++++
 drivers/clk/qcom/Makefile   |  1 +
 drivers/clk/qcom/kpss-xcc.c | 87 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 96 insertions(+)
 create mode 100644 drivers/clk/qcom/kpss-xcc.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index ada4160..7a99627 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -281,6 +281,14 @@ config QCOM_HFPLL
 	  Say Y if you want to support CPU frequency scaling on devices
 	  such as MSM8974, APQ8084, etc.
 
+config KPSS_XCC
+	tristate "KPSS Clock Controller"
+	depends on COMMON_CLK_QCOM
+	help
+	  Support for the Krait ACC and GCC clock controllers. Say Y
+	  if you want to support CPU frequency scaling on devices such
+	  as MSM8960, APQ8064, etc.
+
 config KRAIT_CLOCKS
 	bool
 	select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 506c4cf..92310ee 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -45,4 +45,5 @@ obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
 obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
 obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
 obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
+obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/kpss-xcc.c b/drivers/clk/qcom/kpss-xcc.c
new file mode 100644
index 0000000..8590b5e
--- /dev/null
+++ b/drivers/clk/qcom/kpss-xcc.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+
+static const char *aux_parents[] = {
+	"pll8_vote",
+	"pxo",
+};
+
+static unsigned int aux_parent_map[] = {
+	3,
+	0,
+};
+
+static const struct of_device_id kpss_xcc_match_table[] = {
+	{ .compatible = "qcom,kpss-acc-v1", .data = (void *)1UL },
+	{ .compatible = "qcom,kpss-gcc" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, kpss_xcc_match_table);
+
+static int kpss_xcc_driver_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *id;
+	struct clk *clk;
+	struct resource *res;
+	void __iomem *base;
+	const char *name;
+
+	id = of_match_device(kpss_xcc_match_table, &pdev->dev);
+	if (!id)
+		return -ENODEV;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	if (id->data) {
+		if (of_property_read_string_index(pdev->dev.of_node,
+						  "clock-output-names",
+						  0, &name))
+			return -ENODEV;
+		base += 0x14;
+	} else {
+		name = "acpu_l2_aux";
+		base += 0x28;
+	}
+
+	clk = clk_register_mux_table(&pdev->dev, name, aux_parents,
+				     ARRAY_SIZE(aux_parents), 0, base, 0, 0x3,
+				     0, aux_parent_map, NULL);
+
+	platform_set_drvdata(pdev, clk);
+
+	return PTR_ERR_OR_ZERO(clk);
+}
+
+static int kpss_xcc_driver_remove(struct platform_device *pdev)
+{
+	clk_unregister_mux(platform_get_drvdata(pdev));
+	return 0;
+}
+
+static struct platform_driver kpss_xcc_driver = {
+	.probe = kpss_xcc_driver_probe,
+	.remove = kpss_xcc_driver_remove,
+	.driver = {
+		.name = "kpss-xcc",
+		.of_match_table = kpss_xcc_match_table,
+	},
+};
+module_platform_driver(kpss_xcc_driver);
+
+MODULE_DESCRIPTION("Krait Processor Sub System (KPSS) Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:kpss-xcc");
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH v12 09/14] dt-bindings: arm: Document qcom,kpss-gcc
  2018-08-14 12:12 [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
                   ` (7 preceding siblings ...)
  2018-08-14 12:12 ` [PATCH v12 08/14] clk: qcom: Add KPSS ACC/GCC driver Sricharan R
@ 2018-08-14 12:12 ` Sricharan R
  2018-08-14 12:12 ` [PATCH v12 10/14] clk: qcom: Add Krait clock controller driver Sricharan R
                   ` (5 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Sricharan R @ 2018-08-14 12:12 UTC (permalink / raw)
  To: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel
  Cc: sricharan

From: Stephen Boyd <sboyd@codeaurora.org>

The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
 .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt  | 19 ++++++++++
 .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt  | 44 ++++++++++++++++++++++
 2 files changed, 63 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
index 1333db9..7f69636 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
@@ -21,10 +21,29 @@ PROPERTIES
 		    the register region. An optional second element specifies
 		    the base address and size of the alias register region.
 
+- clocks:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: reference to the pll parents.
+
+- clock-names:
+        Usage: required
+        Value type: <stringlist>
+        Definition: must be "pll8_vote", "pxo".
+
+- clock-output-names:
+	Usage: optional
+	Value type: <string>
+	Definition: Name of the output clock. Typically acpuX_aux where X is a
+		    CPU number starting at 0.
+
 Example:
 
 	clock-controller@2088000 {
 		compatible = "qcom,kpss-acc-v2";
 		reg = <0x02088000 0x1000>,
 		      <0x02008000 0x1000>;
+		clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
+		clock-names = "pll8_vote", "pxo";
+		clock-output-names = "acpu0_aux";
 	};
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
new file mode 100644
index 0000000..e628758
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
@@ -0,0 +1,44 @@
+Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
+
+PROPERTIES
+
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: should be one of the following. The generic compatible
+			"qcom,kpss-gcc" should also be included.
+			"qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
+			"qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
+			"qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
+			"qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
+
+- reg:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: base address and size of the register region
+
+- clocks:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: reference to the pll parents.
+
+- clock-names:
+	Usage: required
+	Value type: <stringlist>
+	Definition: must be "pll8_vote", "pxo".
+
+- clock-output-names:
+	Usage: required
+	Value type: <string>
+	Definition: Name of the output clock. Typically acpu_l2_aux indicating
+		    an L2 cache auxiliary clock.
+
+Example:
+
+	l2cc: clock-controller@2011000 {
+		compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";
+		reg = <0x2011000 0x1000>;
+		clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
+		clock-names = "pll8_vote", "pxo";
+		clock-output-names = "acpu_l2_aux";
+	};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH v12 10/14] clk: qcom: Add Krait clock controller driver
  2018-08-14 12:12 [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
                   ` (8 preceding siblings ...)
  2018-08-14 12:12 ` [PATCH v12 09/14] dt-bindings: arm: Document qcom,kpss-gcc Sricharan R
@ 2018-08-14 12:12 ` Sricharan R
  2018-08-14 12:12 ` [PATCH v12 11/14] dt-bindings: clock: Document qcom,krait-cc Sricharan R
                   ` (4 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Sricharan R @ 2018-08-14 12:12 UTC (permalink / raw)
  To: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel
  Cc: sricharan

From: Stephen Boyd <sboyd@codeaurora.org>

The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
 drivers/clk/qcom/Kconfig     |   8 +
 drivers/clk/qcom/Makefile    |   1 +
 drivers/clk/qcom/clk-krait.c |   4 +-
 drivers/clk/qcom/krait-cc.c  | 341 +++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 352 insertions(+), 2 deletions(-)
 create mode 100644 drivers/clk/qcom/krait-cc.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 7a99627..7c7ca65 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -289,6 +289,14 @@ config KPSS_XCC
 	  if you want to support CPU frequency scaling on devices such
 	  as MSM8960, APQ8064, etc.
 
+config KRAITCC
+	tristate "Krait Clock Controller"
+	depends on COMMON_CLK_QCOM && ARM
+	select KRAIT_CLOCKS
+	help
+	  Support for the Krait CPU clocks on Qualcomm devices.
+	  Say Y if you want to support CPU frequency scaling.
+
 config KRAIT_CLOCKS
 	bool
 	select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 92310ee..949829b 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -47,3 +47,4 @@ obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
 obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
 obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
+obj-$(CONFIG_KRAITCC) += krait-cc.o
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
index 2e41767..7ede744 100644
--- a/drivers/clk/qcom/clk-krait.c
+++ b/drivers/clk/qcom/clk-krait.c
@@ -44,7 +44,7 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
 	struct krait_mux_clk *mux = to_krait_mux_clk(hw);
 	u32 sel;
 
-	sel = clk_mux_reindex(index, mux->parent_map, 0);
+	sel = clk_mux_index_to_val(mux->parent_map, 0, index);
 	mux->en_mask = sel;
 	/* Don't touch mux if CPU is off as it won't work */
 	if (__clk_is_enabled(hw->clk))
@@ -63,7 +63,7 @@ static u8 krait_mux_get_parent(struct clk_hw *hw)
 	sel &= mux->mask;
 	mux->en_mask = sel;
 
-	return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
+	return clk_mux_val_to_index(hw, mux->parent_map, 0, sel);
 }
 
 const struct clk_ops krait_mux_clk_ops = {
diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
new file mode 100644
index 0000000..7c9dfb0
--- /dev/null
+++ b/drivers/clk/qcom/krait-cc.c
@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+
+#include "clk-krait.h"
+
+static unsigned int sec_mux_map[] = {
+	2,
+	0,
+};
+
+static unsigned int pri_mux_map[] = {
+	1,
+	2,
+	0,
+};
+
+static int
+krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
+{
+	struct krait_div2_clk *div;
+	struct clk_init_data init = {
+		.num_parents = 1,
+		.ops = &krait_div2_clk_ops,
+		.flags = CLK_SET_RATE_PARENT,
+	};
+	const char *p_names[1];
+	struct clk *clk;
+
+	div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
+	if (!div)
+		return -ENOMEM;
+
+	div->width = 2;
+	div->shift = 6;
+	div->lpl = id >= 0;
+	div->offset = offset;
+	div->hw.init = &init;
+
+	init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
+	if (!init.name)
+		return -ENOMEM;
+
+	init.parent_names = p_names;
+	p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
+	if (!p_names[0]) {
+		kfree(init.name);
+		return -ENOMEM;
+	}
+
+	clk = devm_clk_register(dev, &div->hw);
+	kfree(p_names[0]);
+	kfree(init.name);
+
+	return PTR_ERR_OR_ZERO(clk);
+}
+
+static int
+krait_add_sec_mux(struct device *dev, int id, const char *s,
+		  unsigned int offset, bool unique_aux)
+{
+	struct krait_mux_clk *mux;
+	static const char *sec_mux_list[] = {
+		"acpu_aux",
+		"qsb",
+	};
+	struct clk_init_data init = {
+		.parent_names = sec_mux_list,
+		.num_parents = ARRAY_SIZE(sec_mux_list),
+		.ops = &krait_mux_clk_ops,
+		.flags = CLK_SET_RATE_PARENT,
+	};
+	struct clk *clk;
+
+	mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+	if (!mux)
+		return -ENOMEM;
+
+	mux->offset = offset;
+	mux->lpl = id >= 0;
+	mux->mask = 0x3;
+	mux->shift = 2;
+	mux->parent_map = sec_mux_map;
+	mux->hw.init = &init;
+
+	init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
+	if (!init.name)
+		return -ENOMEM;
+
+	if (unique_aux) {
+		sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
+		if (!sec_mux_list[0]) {
+			clk = ERR_PTR(-ENOMEM);
+			goto err_aux;
+		}
+	}
+
+	clk = devm_clk_register(dev, &mux->hw);
+
+	if (unique_aux)
+		kfree(sec_mux_list[0]);
+err_aux:
+	kfree(init.name);
+	return PTR_ERR_OR_ZERO(clk);
+}
+
+static struct clk *
+krait_add_pri_mux(struct device *dev, int id, const char *s,
+		  unsigned int offset)
+{
+	struct krait_mux_clk *mux;
+	const char *p_names[3];
+	struct clk_init_data init = {
+		.parent_names = p_names,
+		.num_parents = ARRAY_SIZE(p_names),
+		.ops = &krait_mux_clk_ops,
+		.flags = CLK_SET_RATE_PARENT,
+	};
+	struct clk *clk;
+
+	mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+	if (!mux)
+		return ERR_PTR(-ENOMEM);
+
+	mux->mask = 0x3;
+	mux->shift = 0;
+	mux->offset = offset;
+	mux->lpl = id >= 0;
+	mux->parent_map = pri_mux_map;
+	mux->hw.init = &init;
+
+	init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
+	if (!init.name)
+		return ERR_PTR(-ENOMEM);
+
+	p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
+	if (!p_names[0]) {
+		clk = ERR_PTR(-ENOMEM);
+		goto err_p0;
+	}
+
+	p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
+	if (!p_names[1]) {
+		clk = ERR_PTR(-ENOMEM);
+		goto err_p1;
+	}
+
+	p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
+	if (!p_names[2]) {
+		clk = ERR_PTR(-ENOMEM);
+		goto err_p2;
+	}
+
+	clk = devm_clk_register(dev, &mux->hw);
+
+	kfree(p_names[2]);
+err_p2:
+	kfree(p_names[1]);
+err_p1:
+	kfree(p_names[0]);
+err_p0:
+	kfree(init.name);
+	return clk;
+}
+
+/* id < 0 for L2, otherwise id == physical CPU number */
+static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
+{
+	int ret;
+	unsigned int offset;
+	void *p = NULL;
+	const char *s;
+	struct clk *clk;
+
+	if (id >= 0) {
+		offset = 0x4501 + (0x1000 * id);
+		s = p = kasprintf(GFP_KERNEL, "%d", id);
+		if (!s)
+			return ERR_PTR(-ENOMEM);
+	} else {
+		offset = 0x500;
+		s = "_l2";
+	}
+
+	ret = krait_add_div(dev, id, s, offset);
+	if (ret) {
+		clk = ERR_PTR(ret);
+		goto err;
+	}
+
+	ret = krait_add_sec_mux(dev, id, s, offset, unique_aux);
+	if (ret) {
+		clk = ERR_PTR(ret);
+		goto err;
+	}
+
+	clk = krait_add_pri_mux(dev, id, s, offset);
+err:
+	kfree(p);
+	return clk;
+}
+
+static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
+{
+	unsigned int idx = clkspec->args[0];
+	struct clk **clks = data;
+
+	if (idx >= 5) {
+		pr_err("%s: invalid clock index %d\n", __func__, idx);
+		return ERR_PTR(-EINVAL);
+	}
+
+	return clks[idx] ? : ERR_PTR(-ENODEV);
+}
+
+static const struct of_device_id krait_cc_match_table[] = {
+	{ .compatible = "qcom,krait-cc-v1", (void *)1UL },
+	{ .compatible = "qcom,krait-cc-v2" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, krait_cc_match_table);
+
+static int krait_cc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	const struct of_device_id *id;
+	unsigned long cur_rate, aux_rate;
+	int cpu;
+	struct clk *clk;
+	struct clk **clks;
+	struct clk *l2_pri_mux_clk;
+
+	id = of_match_device(krait_cc_match_table, dev);
+	if (!id)
+		return -ENODEV;
+
+	/* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
+	clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
+
+	if (!id->data) {
+		clk = clk_register_fixed_factor(dev, "acpu_aux",
+						"gpll0_vote", 0, 1, 2);
+		if (IS_ERR(clk))
+			return PTR_ERR(clk);
+	}
+
+	/* Krait configurations have at most 4 CPUs and one L2 */
+	clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL);
+	if (!clks)
+		return -ENOMEM;
+
+	for_each_possible_cpu(cpu) {
+		clk = krait_add_clks(dev, cpu, id->data);
+		if (IS_ERR(clk))
+			return PTR_ERR(clk);
+		clks[cpu] = clk;
+	}
+
+	l2_pri_mux_clk = krait_add_clks(dev, -1, id->data);
+	if (IS_ERR(l2_pri_mux_clk))
+		return PTR_ERR(l2_pri_mux_clk);
+	clks[4] = l2_pri_mux_clk;
+
+	/*
+	 * We don't want the CPU or L2 clocks to be turned off at late init
+	 * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the
+	 * refcount of these clocks. Any cpufreq/hotplug manager can assume
+	 * that the clocks have already been prepared and enabled by the time
+	 * they take over.
+	 */
+	for_each_online_cpu(cpu) {
+		clk_prepare_enable(l2_pri_mux_clk);
+		WARN(clk_prepare_enable(clks[cpu]),
+		     "Unable to turn on CPU%d clock", cpu);
+	}
+
+	/*
+	 * Force reinit of HFPLLs and muxes to overwrite any potential
+	 * incorrect configuration of HFPLLs and muxes by the bootloader.
+	 * While at it, also make sure the cores are running at known rates
+	 * and print the current rate.
+	 *
+	 * The clocks are set to aux clock rate first to make sure the
+	 * secondary mux is not sourcing off of QSB. The rate is then set to
+	 * two different rates to force a HFPLL reinit under all
+	 * circumstances.
+	 */
+	cur_rate = clk_get_rate(l2_pri_mux_clk);
+	aux_rate = 384000000;
+	if (cur_rate == 1) {
+		pr_info("L2 @ QSB rate. Forcing new rate.\n");
+		cur_rate = aux_rate;
+	}
+	clk_set_rate(l2_pri_mux_clk, aux_rate);
+	clk_set_rate(l2_pri_mux_clk, 2);
+	clk_set_rate(l2_pri_mux_clk, cur_rate);
+	pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
+	for_each_possible_cpu(cpu) {
+		clk = clks[cpu];
+		cur_rate = clk_get_rate(clk);
+		if (cur_rate == 1) {
+			pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu);
+			cur_rate = aux_rate;
+		}
+
+		clk_set_rate(clk, aux_rate);
+		clk_set_rate(clk, 2);
+		clk_set_rate(clk, cur_rate);
+		pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
+	}
+
+	of_clk_add_provider(dev->of_node, krait_of_get, clks);
+
+	return 0;
+}
+
+static struct platform_driver krait_cc_driver = {
+	.probe = krait_cc_probe,
+	.driver = {
+		.name = "krait-cc",
+		.of_match_table = krait_cc_match_table,
+	},
+};
+module_platform_driver(krait_cc_driver);
+
+MODULE_DESCRIPTION("Krait CPU Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:krait-cc");
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH v12 11/14] dt-bindings: clock: Document qcom,krait-cc
  2018-08-14 12:12 [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
                   ` (9 preceding siblings ...)
  2018-08-14 12:12 ` [PATCH v12 10/14] clk: qcom: Add Krait clock controller driver Sricharan R
@ 2018-08-14 12:12 ` Sricharan R
  2018-08-14 12:12 ` [PATCH v12 12/14] clk: qcom: Add safe switch hook for krait mux clocks Sricharan R
                   ` (3 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Sricharan R @ 2018-08-14 12:12 UTC (permalink / raw)
  To: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel
  Cc: sricharan

From: Stephen Boyd <sboyd@codeaurora.org>

The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
 .../devicetree/bindings/clock/qcom,krait-cc.txt    | 34 ++++++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt

diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
new file mode 100644
index 0000000..030ba60
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
@@ -0,0 +1,34 @@
+Krait Clock Controller
+
+PROPERTIES
+
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: must be one of:
+			"qcom,krait-cc-v1"
+			"qcom,krait-cc-v2"
+
+- #clock-cells:
+	Usage: required
+	Value type: <u32>
+	Definition: must be 1
+
+- clocks:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: reference to the clock parents of hfpll, secondary muxes.
+
+- clock-names:
+	Usage: required
+	Value type: <stringlist>
+	Definition: must be "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb".
+
+Example:
+
+	kraitcc: clock-controller {
+		compatible = "qcom,krait-cc-v1";
+		clocks = <&hfpll0>, <&hfpll1>, <&acpu0_aux>, <&acpu1_aux>, <qsb>;
+		clock-names = "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb";
+		#clock-cells = <1>;
+	};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH v12 12/14] clk: qcom: Add safe switch hook for krait mux clocks
  2018-08-14 12:12 [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
                   ` (10 preceding siblings ...)
  2018-08-14 12:12 ` [PATCH v12 11/14] dt-bindings: clock: Document qcom,krait-cc Sricharan R
@ 2018-08-14 12:12 ` Sricharan R
  2018-08-14 12:12 ` [PATCH v12 13/14] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs Sricharan R
                   ` (2 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Sricharan R @ 2018-08-14 12:12 UTC (permalink / raw)
  To: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel
  Cc: sricharan

When the Hfplls are reprogrammed during the rate change,
the primary muxes which are sourced from the same hfpll
for higher frequencies, needs to be switched to the 'safe
secondary mux' as the parent for that small window. This
is done by registering a clk notifier for the muxes and
switching to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.

Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
 drivers/clk/qcom/clk-krait.c |  2 ++
 drivers/clk/qcom/clk-krait.h |  3 +++
 drivers/clk/qcom/krait-cc.c  | 56 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 61 insertions(+)

diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
index 7ede744..59f1af4 100644
--- a/drivers/clk/qcom/clk-krait.c
+++ b/drivers/clk/qcom/clk-krait.c
@@ -50,6 +50,8 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
 	if (__clk_is_enabled(hw->clk))
 		__krait_mux_set_sel(mux, sel);
 
+	mux->reparent = true;
+
 	return 0;
 }
 
diff --git a/drivers/clk/qcom/clk-krait.h b/drivers/clk/qcom/clk-krait.h
index 441ba1e..9120bd2 100644
--- a/drivers/clk/qcom/clk-krait.h
+++ b/drivers/clk/qcom/clk-krait.h
@@ -12,6 +12,9 @@ struct krait_mux_clk {
 	u32		shift;
 	u32		en_mask;
 	bool		lpl;
+	u8		safe_sel;
+	u8		old_index;
+	bool		reparent;
 
 	struct clk_hw	hw;
 	struct notifier_block   clk_nb;
diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
index 7c9dfb0..4d4b657 100644
--- a/drivers/clk/qcom/krait-cc.c
+++ b/drivers/clk/qcom/krait-cc.c
@@ -26,6 +26,49 @@
 	0,
 };
 
+/*
+ * Notifier function for switching the muxes to safe parent
+ * while the hfpll is getting reprogrammed.
+ */
+static int krait_notifier_cb(struct notifier_block *nb,
+			     unsigned long event,
+			     void *data)
+{
+	int ret = 0;
+	struct krait_mux_clk *mux = container_of(nb, struct krait_mux_clk,
+						 clk_nb);
+	/* Switch to safe parent */
+	if (event == PRE_RATE_CHANGE) {
+		mux->old_index = krait_mux_clk_ops.get_parent(&mux->hw);
+		ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel);
+		mux->reparent = false;
+	/*
+	 * By the time POST_RATE_CHANGE notifier is called,
+	 * clk framework itself would have changed the parent for the new rate.
+	 * Only otherwise, put back to the old parent.
+	 */
+	} else if (event == POST_RATE_CHANGE) {
+		if (!mux->reparent)
+			ret = krait_mux_clk_ops.set_parent(&mux->hw,
+							   mux->old_index);
+	}
+
+	return notifier_from_errno(ret);
+}
+
+static int krait_notifier_register(struct device *dev, struct clk *clk,
+				   struct krait_mux_clk *mux)
+{
+	int ret = 0;
+
+	mux->clk_nb.notifier_call = krait_notifier_cb;
+	ret = clk_notifier_register(clk, &mux->clk_nb);
+	if (ret)
+		dev_err(dev, "failed to register clock notifier: %d\n", ret);
+
+	return ret;
+}
+
 static int
 krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
 {
@@ -70,6 +113,7 @@
 krait_add_sec_mux(struct device *dev, int id, const char *s,
 		  unsigned int offset, bool unique_aux)
 {
+	int ret;
 	struct krait_mux_clk *mux;
 	static const char *sec_mux_list[] = {
 		"acpu_aux",
@@ -93,6 +137,7 @@
 	mux->shift = 2;
 	mux->parent_map = sec_mux_map;
 	mux->hw.init = &init;
+	mux->safe_sel = 0;
 
 	init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
 	if (!init.name)
@@ -108,6 +153,11 @@
 
 	clk = devm_clk_register(dev, &mux->hw);
 
+	ret = krait_notifier_register(dev, clk, mux);
+	if (ret)
+		goto unique_aux;
+
+unique_aux:
 	if (unique_aux)
 		kfree(sec_mux_list[0]);
 err_aux:
@@ -119,6 +169,7 @@
 krait_add_pri_mux(struct device *dev, int id, const char *s,
 		  unsigned int offset)
 {
+	int ret;
 	struct krait_mux_clk *mux;
 	const char *p_names[3];
 	struct clk_init_data init = {
@@ -139,6 +190,7 @@
 	mux->lpl = id >= 0;
 	mux->parent_map = pri_mux_map;
 	mux->hw.init = &init;
+	mux->safe_sel = 2;
 
 	init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
 	if (!init.name)
@@ -164,6 +216,10 @@
 
 	clk = devm_clk_register(dev, &mux->hw);
 
+	ret = krait_notifier_register(dev, clk, mux);
+	if (ret)
+		goto err_p3;
+err_p3:
 	kfree(p_names[2]);
 err_p2:
 	kfree(p_names[1]);
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH v12 13/14] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs
  2018-08-14 12:12 [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
                   ` (11 preceding siblings ...)
  2018-08-14 12:12 ` [PATCH v12 12/14] clk: qcom: Add safe switch hook for krait mux clocks Sricharan R
@ 2018-08-14 12:12 ` Sricharan R
  2018-08-17 15:09   ` Rob Herring
  2018-08-14 12:12 ` [PATCH v12 14/14] cpufreq: qcom: Add support for krait based socs Sricharan R
  2018-08-14 12:20 ` [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
  14 siblings, 1 reply; 32+ messages in thread
From: Sricharan R @ 2018-08-14 12:12 UTC (permalink / raw)
  To: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel
  Cc: sricharan

The kryo cpufreq driver reads the nvmem cell and uses that data to
populate the opps. There are other qcom cpufreq socs like krait which
does similar thing. Except for the interpretation of the read data,
rest of the driver is same for both the cases. So pull the common things
out for reuse.

Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
 .../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt}   |   6 +-
 drivers/cpufreq/Kconfig.arm                        |   4 +-
 drivers/cpufreq/Makefile                           |   2 +-
 .../{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c}  | 124 ++++++++++++---------
 4 files changed, 80 insertions(+), 56 deletions(-)
 rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} (99%)
 rename drivers/cpufreq/{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} (65%)

diff --git a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
similarity index 99%
rename from Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
rename to Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
index c2127b9..6dcdfcd 100644
--- a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
@@ -19,7 +19,7 @@ In 'cpus' nodes:
 
 In 'operating-points-v2' table:
 - compatible: Should be
-	- 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
+	- 'operating-points-v2-qcom-cpu' for apq8096 and msm8996.
 - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
 		efuse registers that has information about the
 		speedbin that is used to select the right frequency/voltage
@@ -127,7 +127,7 @@ Example 1:
 	};
 
 	cluster0_opp: opp_table0 {
-		compatible = "operating-points-v2-kryo-cpu";
+		compatible = "operating-points-v2-qcom-cpu";
 		nvmem-cells = <&speedbin_efuse>;
 		opp-shared;
 
@@ -338,7 +338,7 @@ Example 1:
 	};
 
 	cluster1_opp: opp_table1 {
-		compatible = "operating-points-v2-kryo-cpu";
+		compatible = "operating-points-v2-qcom-cpu";
 		nvmem-cells = <&speedbin_efuse>;
 		opp-shared;
 
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 52f5f1a..13fbd97 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -124,8 +124,8 @@ config ARM_OMAP2PLUS_CPUFREQ
 	depends on ARCH_OMAP2PLUS
 	default ARCH_OMAP2PLUS
 
-config ARM_QCOM_CPUFREQ_KRYO
-	tristate "Qualcomm Kryo based CPUFreq"
+config ARM_QCOM_CPUFREQ_NVMEM
+	tristate "Qualcomm nvmem based CPUFreq"
 	depends on ARM64
 	depends on QCOM_QFPROM
 	depends on QCOM_SMEM
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index fb4a2ec..5544441 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -65,7 +65,7 @@ obj-$(CONFIG_MACH_MVEBU_V7)		+= mvebu-cpufreq.o
 obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)	+= omap-cpufreq.o
 obj-$(CONFIG_ARM_PXA2xx_CPUFREQ)	+= pxa2xx-cpufreq.o
 obj-$(CONFIG_PXA3xx)			+= pxa3xx-cpufreq.o
-obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO)	+= qcom-cpufreq-kryo.o
+obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM)	+= qcom-cpufreq-nvmem.o
 obj-$(CONFIG_ARM_S3C2410_CPUFREQ)	+= s3c2410-cpufreq.o
 obj-$(CONFIG_ARM_S3C2412_CPUFREQ)	+= s3c2412-cpufreq.o
 obj-$(CONFIG_ARM_S3C2416_CPUFREQ)	+= s3c2416-cpufreq.o
diff --git a/drivers/cpufreq/qcom-cpufreq-kryo.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
similarity index 65%
rename from drivers/cpufreq/qcom-cpufreq-kryo.c
rename to drivers/cpufreq/qcom-cpufreq-nvmem.c
index efc9a7a..0ad8e5b 100644
--- a/drivers/cpufreq/qcom-cpufreq-kryo.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -9,7 +9,7 @@
  * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
  * defines the voltage and frequency value based on the msm-id in SMEM
  * and speedbin blown in the efuse combination.
- * The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
+ * The qcom-cpufreq driver reads the msm-id and efuse value from the SoC
  * to provide the OPP framework with required information.
  * This is used to determine the voltage and frequency value for each OPP of
  * operating-points-v2 table when it is parsed by the OPP framework.
@@ -22,6 +22,7 @@
 #include <linux/module.h>
 #include <linux/nvmem-consumer.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/pm_opp.h>
 #include <linux/slab.h>
@@ -42,9 +43,9 @@ enum _msm8996_version {
 	NUM_OF_MSM8996_VERSIONS,
 };
 
-struct platform_device *cpufreq_dt_pdev, *kryo_cpufreq_pdev;
+static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
 
-static enum _msm8996_version __init qcom_cpufreq_kryo_get_msm_id(void)
+static enum _msm8996_version __init qcom_cpufreq_get_msm_id(void)
 {
 	size_t len;
 	u32 *msm_id;
@@ -73,34 +74,70 @@ static enum _msm8996_version __init qcom_cpufreq_kryo_get_msm_id(void)
 	return version;
 }
 
-static int qcom_cpufreq_kryo_probe(struct platform_device *pdev)
+static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
+					  struct nvmem_cell *speedbin_nvmem,
+					  char **pvs_name,
+					  u32 *versions)
 {
-	struct opp_table *opp_tables[NR_CPUS] = {0};
+	size_t len;
+	u8 *speedbin;
 	enum _msm8996_version msm8996_version;
+
+	msm8996_version = qcom_cpufreq_get_msm_id();
+	if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
+		dev_err(cpu_dev, "Not Snapdragon 820/821!");
+		return -ENODEV;
+	}
+
+	speedbin = nvmem_cell_read(speedbin_nvmem, &len);
+	if (IS_ERR(speedbin))
+		return PTR_ERR(speedbin);
+
+	switch (msm8996_version) {
+	case MSM8996_V3:
+		*versions = 1 << (unsigned int)(*speedbin);
+		break;
+	case MSM8996_SG:
+		*versions = 1 << ((unsigned int)(*speedbin) + 4);
+		break;
+	default:
+		BUG();
+		break;
+	}
+
+	kfree(speedbin);
+	return 0;
+}
+
+static int qcom_cpufreq_probe(struct platform_device *pdev)
+{
+	struct opp_table *opp_tables[NR_CPUS] = { NULL };
+	int (*get_version)(struct device *cpu_dev,
+			   struct nvmem_cell *speedbin_nvmem,
+			   char **name, int *versions);
 	struct nvmem_cell *speedbin_nvmem;
 	struct device_node *np;
 	struct device *cpu_dev;
 	unsigned cpu;
-	u8 *speedbin;
 	u32 versions;
-	size_t len;
+	char *pvs_name = NULL;
+	const struct of_device_id *match;
 	int ret;
 
 	cpu_dev = get_cpu_device(0);
 	if (!cpu_dev)
 		return -ENODEV;
 
-	msm8996_version = qcom_cpufreq_kryo_get_msm_id();
-	if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
-		dev_err(cpu_dev, "Not Snapdragon 820/821!");
+	match = pdev->dev.platform_data;
+	get_version = match->data;
+	if (!get_version)
 		return -ENODEV;
-	}
 
 	np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
 	if (!np)
 		return -ENOENT;
 
-	ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
+	ret = of_device_is_compatible(np, "operating-points-v2-qcom-cpu");
 	if (!ret) {
 		of_node_put(np);
 		return -ENOENT;
@@ -114,23 +151,10 @@ static int qcom_cpufreq_kryo_probe(struct platform_device *pdev)
 		return PTR_ERR(speedbin_nvmem);
 	}
 
-	speedbin = nvmem_cell_read(speedbin_nvmem, &len);
+	ret = get_version(cpu_dev, speedbin_nvmem, &pvs_name, &versions);
 	nvmem_cell_put(speedbin_nvmem);
-	if (IS_ERR(speedbin))
-		return PTR_ERR(speedbin);
-
-	switch (msm8996_version) {
-	case MSM8996_V3:
-		versions = 1 << (unsigned int)(*speedbin);
-		break;
-	case MSM8996_SG:
-		versions = 1 << ((unsigned int)(*speedbin) + 4);
-		break;
-	default:
-		BUG();
-		break;
-	}
-	kfree(speedbin);
+	if (ret)
+		return ret;
 
 	for_each_possible_cpu(cpu) {
 		cpu_dev = get_cpu_device(cpu);
@@ -166,24 +190,24 @@ static int qcom_cpufreq_kryo_probe(struct platform_device *pdev)
 	return ret;
 }
 
-static int qcom_cpufreq_kryo_remove(struct platform_device *pdev)
+static int qcom_cpufreq_remove(struct platform_device *pdev)
 {
 	platform_device_unregister(cpufreq_dt_pdev);
 	return 0;
 }
 
-static struct platform_driver qcom_cpufreq_kryo_driver = {
-	.probe = qcom_cpufreq_kryo_probe,
-	.remove = qcom_cpufreq_kryo_remove,
+static struct platform_driver qcom_cpufreq_driver = {
+	.probe = qcom_cpufreq_probe,
+	.remove = qcom_cpufreq_remove,
 	.driver = {
-		.name = "qcom-cpufreq-kryo",
+		.name = "qcom-cpufreq",
 	},
 };
 
-static const struct of_device_id qcom_cpufreq_kryo_match_list[] __initconst = {
-	{ .compatible = "qcom,apq8096", },
-	{ .compatible = "qcom,msm8996", },
-	{}
+static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
+	{ .compatible = "qcom,apq8096", .data = qcom_cpufreq_kryo_name_version},
+	{ .compatible = "qcom,msm8996", .data = qcom_cpufreq_kryo_name_version},
+	{},
 };
 
 /*
@@ -192,7 +216,7 @@ static int qcom_cpufreq_kryo_remove(struct platform_device *pdev)
  * which may be defered as well. The init here is only registering
  * the driver and the platform device.
  */
-static int __init qcom_cpufreq_kryo_init(void)
+static int __init qcom_cpufreq_init(void)
 {
 	struct device_node *np = of_find_node_by_path("/");
 	const struct of_device_id *match;
@@ -201,32 +225,32 @@ static int __init qcom_cpufreq_kryo_init(void)
 	if (!np)
 		return -ENODEV;
 
-	match = of_match_node(qcom_cpufreq_kryo_match_list, np);
+	match = of_match_node(qcom_cpufreq_match_list, np);
 	of_node_put(np);
 	if (!match)
 		return -ENODEV;
 
-	ret = platform_driver_register(&qcom_cpufreq_kryo_driver);
+	ret = platform_driver_register(&qcom_cpufreq_driver);
 	if (unlikely(ret < 0))
 		return ret;
 
-	kryo_cpufreq_pdev = platform_device_register_simple(
-		"qcom-cpufreq-kryo", -1, NULL, 0);
-	ret = PTR_ERR_OR_ZERO(kryo_cpufreq_pdev);
+	cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq",
+						     -1, match, sizeof(*match));
+	ret = PTR_ERR_OR_ZERO(cpufreq_pdev);
 	if (0 == ret)
 		return 0;
 
-	platform_driver_unregister(&qcom_cpufreq_kryo_driver);
+	platform_driver_unregister(&qcom_cpufreq_driver);
 	return ret;
 }
-module_init(qcom_cpufreq_kryo_init);
+module_init(qcom_cpufreq_init);
 
-static void __init qcom_cpufreq_kryo_exit(void)
+static void __init qcom_cpufreq_exit(void)
 {
-	platform_device_unregister(kryo_cpufreq_pdev);
-	platform_driver_unregister(&qcom_cpufreq_kryo_driver);
+	platform_device_unregister(cpufreq_pdev);
+	platform_driver_unregister(&qcom_cpufreq_driver);
 }
-module_exit(qcom_cpufreq_kryo_exit);
+module_exit(qcom_cpufreq_exit);
 
-MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Kryo CPUfreq driver");
+MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver");
 MODULE_LICENSE("GPL v2");
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [PATCH v12 14/14] cpufreq: qcom: Add support for krait based socs
  2018-08-14 12:12 [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
                   ` (12 preceding siblings ...)
  2018-08-14 12:12 ` [PATCH v12 13/14] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs Sricharan R
@ 2018-08-14 12:12 ` Sricharan R
  2018-08-17 15:09   ` Rob Herring
                     ` (2 more replies)
  2018-08-14 12:20 ` [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
  14 siblings, 3 replies; 32+ messages in thread
From: Sricharan R @ 2018-08-14 12:12 UTC (permalink / raw)
  To: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel
  Cc: sricharan

In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
that has KRAIT processors the voltage/current value of each OPP
varies based on the silicon variant in use.

The required OPP related data is determined based on
the efuse value. This is similar to the existing code for
kryo cores. So adding support for krait cores here.

Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
 .../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt |   3 +-
 drivers/cpufreq/Kconfig.arm                        |   2 +-
 drivers/cpufreq/cpufreq-dt-platdev.c               |   5 +
 drivers/cpufreq/qcom-cpufreq-nvmem.c               | 151 +++++++++++++++++++--
 4 files changed, 149 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
index 6dcdfcd..7bc0f1a 100644
--- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
@@ -19,7 +19,8 @@ In 'cpus' nodes:
 
 In 'operating-points-v2' table:
 - compatible: Should be
-	- 'operating-points-v2-qcom-cpu' for apq8096 and msm8996.
+	- 'operating-points-v2-qcom-cpu' for apq8096, msm8996, msm8974,
+					     apq8064, msm8960 and ipq8074.
 - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
 		efuse registers that has information about the
 		speedbin that is used to select the right frequency/voltage
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 13fbd97..497ae89 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -126,7 +126,7 @@ config ARM_OMAP2PLUS_CPUFREQ
 
 config ARM_QCOM_CPUFREQ_NVMEM
 	tristate "Qualcomm nvmem based CPUFreq"
-	depends on ARM64
+	depends on ARCH_QCOM
 	depends on QCOM_QFPROM
 	depends on QCOM_SMEM
 	select PM_OPP
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index fe14c57..917cdc2 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -128,6 +128,11 @@
 	{ .compatible = "ti,am43", },
 	{ .compatible = "ti,dra7", },
 
+	{ .compatible = "qcom,ipq8064", },
+	{ .compatible = "qcom,apq8064", },
+	{ .compatible = "qcom,msm8974", },
+	{ .compatible = "qcom,msm8960", },
+
 	{ }
 };
 
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 0ad8e5b..5f2add0 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -45,6 +45,82 @@ enum _msm8996_version {
 
 static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
 
+static void __init get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver,
+					  struct nvmem_cell *pvs_nvmem, u8 *buf)
+{
+	u32 pte_efuse;
+
+	pte_efuse = *((u32 *)buf);
+
+	*speed = pte_efuse & 0xf;
+	if (*speed == 0xf)
+		*speed = (pte_efuse >> 4) & 0xf;
+
+	if (*speed == 0xf) {
+		*speed = 0;
+		pr_warn("Speed bin: Defaulting to %d\n", *speed);
+	} else {
+		pr_info("Speed bin: %d\n", *speed);
+	}
+
+	*pvs = (pte_efuse >> 10) & 0x7;
+	if (*pvs == 0x7)
+		*pvs = (pte_efuse >> 13) & 0x7;
+
+	if (*pvs == 0x7) {
+		*pvs = 0;
+		pr_warn("PVS bin: Defaulting to %d\n", *pvs);
+	} else {
+		pr_info("PVS bin: %d\n", *pvs);
+	}
+
+	kfree(buf);
+}
+
+static void __init get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver,
+					  struct nvmem_cell *pvs_nvmem, u8 *buf)
+{
+	u32 pte_efuse, redundant_sel;
+
+	pte_efuse = *((u32 *)buf);
+	redundant_sel = (pte_efuse >> 24) & 0x7;
+	*speed = pte_efuse & 0x7;
+
+	/* 4 bits of PVS are in efuse register bits 31, 8-6. */
+	*pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
+	*pvs_ver = (pte_efuse >> 4) & 0x3;
+
+	switch (redundant_sel) {
+	case 1:
+		*speed = (pte_efuse >> 27) & 0xf;
+		break;
+	case 2:
+		*pvs = (pte_efuse >> 27) & 0xf;
+		break;
+	}
+
+	/* Check SPEED_BIN_BLOW_STATUS */
+	if (pte_efuse & BIT(3)) {
+		pr_info("Speed bin: %d\n", *speed);
+	} else {
+		pr_warn("Speed bin not set. Defaulting to 0!\n");
+		*speed = 0;
+	}
+
+	/* Check PVS_BLOW_STATUS */
+	pte_efuse = *(((u32 *)buf) + 4);
+	pte_efuse &= BIT(21);
+	if (pte_efuse) {
+		pr_info("PVS bin: %d\n", *pvs);
+	} else {
+		pr_warn("PVS bin not set. Defaulting to 0!\n");
+		*pvs = 0;
+	}
+
+	pr_info("PVS version: %d\n", *pvs_ver);
+	kfree(buf);
+}
+
 static enum _msm8996_version __init qcom_cpufreq_get_msm_id(void)
 {
 	size_t len;
@@ -74,6 +150,35 @@ static enum _msm8996_version __init qcom_cpufreq_get_msm_id(void)
 	return version;
 }
 
+static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
+					   struct nvmem_cell *speedbin_nvmem,
+					   char **name,
+					   u32 *versions)
+{
+	int speed = 0, pvs = 0, pvs_ver = 0;
+	u8 *buf;
+	size_t len;
+
+	buf = nvmem_cell_read(speedbin_nvmem, &len);
+	if (len == 4) {
+		get_krait_bin_format_a(&speed, &pvs, &pvs_ver,
+				       speedbin_nvmem, buf);
+	} else if (len == 8) {
+		get_krait_bin_format_b(&speed, &pvs, &pvs_ver,
+				       speedbin_nvmem, buf);
+	} else {
+		dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
+		return -ENODEV;
+	}
+
+	snprintf(*name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
+		 speed, pvs, pvs_ver);
+
+	*versions = (1 << speed);
+
+	return 0;
+}
+
 static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
 					  struct nvmem_cell *speedbin_nvmem,
 					  char **pvs_name,
@@ -83,6 +188,7 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
 	u8 *speedbin;
 	enum _msm8996_version msm8996_version;
 
+	*pvs_name = NULL;
 	msm8996_version = qcom_cpufreq_get_msm_id();
 	if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
 		dev_err(cpu_dev, "Not Snapdragon 820/821!");
@@ -111,7 +217,7 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
 
 static int qcom_cpufreq_probe(struct platform_device *pdev)
 {
-	struct opp_table *opp_tables[NR_CPUS] = { NULL };
+	struct opp_table *tbl1[NR_CPUS] = { NULL }, *tbl2[NR_CPUS] = { NULL };
 	int (*get_version)(struct device *cpu_dev,
 			   struct nvmem_cell *speedbin_nvmem,
 			   char **name, int *versions);
@@ -120,8 +226,8 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
 	struct device *cpu_dev;
 	unsigned cpu;
 	u32 versions;
-	char *pvs_name = NULL;
 	const struct of_device_id *match;
+	char *pvs_name = "speedXX-pvsXX-vXX";
 	int ret;
 
 	cpu_dev = get_cpu_device(0);
@@ -163,10 +269,19 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
 			goto free_opp;
 		}
 
-		opp_tables[cpu] = dev_pm_opp_set_supported_hw(cpu_dev,
-							      &versions, 1);
-		if (IS_ERR(opp_tables[cpu])) {
-			ret = PTR_ERR(opp_tables[cpu]);
+		if (pvs_name) {
+			tbl1[cpu] = dev_pm_opp_set_prop_name(cpu_dev, pvs_name);
+			if (IS_ERR(tbl1[cpu])) {
+				ret = PTR_ERR(tbl1[cpu]);
+				dev_err(cpu_dev, "Failed to add OPP name %s\n",
+					pvs_name);
+				goto free_opp;
+			}
+		}
+
+		tbl2[cpu] = dev_pm_opp_set_supported_hw(cpu_dev, &versions, 1);
+		if (IS_ERR(tbl2[cpu])) {
+			ret = PTR_ERR(tbl2[cpu]);
 			dev_err(cpu_dev, "Failed to set supported hardware\n");
 			goto free_opp;
 		}
@@ -182,9 +297,15 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
 
 free_opp:
 	for_each_possible_cpu(cpu) {
-		if (IS_ERR_OR_NULL(opp_tables[cpu]))
+		if (IS_ERR_OR_NULL(tbl1[cpu]))
+			break;
+		dev_pm_opp_put_prop_name(tbl1[cpu]);
+	}
+
+	for_each_possible_cpu(cpu) {
+		if (IS_ERR_OR_NULL(tbl2[cpu]))
 			break;
-		dev_pm_opp_put_supported_hw(opp_tables[cpu]);
+		dev_pm_opp_put_supported_hw(tbl2[cpu]);
 	}
 
 	return ret;
@@ -205,8 +326,18 @@ static int qcom_cpufreq_remove(struct platform_device *pdev)
 };
 
 static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
-	{ .compatible = "qcom,apq8096", .data = qcom_cpufreq_kryo_name_version},
-	{ .compatible = "qcom,msm8996", .data = qcom_cpufreq_kryo_name_version},
+	{ .compatible = "qcom,apq8096",
+	  .data = qcom_cpufreq_kryo_name_version},
+	{ .compatible = "qcom,msm8996",
+	  .data = qcom_cpufreq_kryo_name_version},
+	{ .compatible = "qcom,ipq8064",
+	  .data = qcom_cpufreq_krait_name_version },
+	{ .compatible = "qcom,apq8064",
+	  .data = qcom_cpufreq_krait_name_version },
+	{ .compatible = "qcom,msm8974",
+	  .data = qcom_cpufreq_krait_name_version },
+	{ .compatible = "qcom,msm8960",
+	  .data = qcom_cpufreq_krait_name_version },
 	{},
 };
 
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
  2018-08-14 12:12 [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
                   ` (13 preceding siblings ...)
  2018-08-14 12:12 ` [PATCH v12 14/14] cpufreq: qcom: Add support for krait based socs Sricharan R
@ 2018-08-14 12:20 ` Sricharan R
  2018-09-07  9:57   ` Sricharan R
  14 siblings, 1 reply; 32+ messages in thread
From: Sricharan R @ 2018-08-14 12:20 UTC (permalink / raw)
  To: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel

Hi Craig,

On 8/14/2018 5:42 PM, Sricharan R wrote:
> [v12]
>   * Added my signed-off that was missing in some patches.
>   * Added Bjorn's acked that i missed earlier.
> 

  Can you give this a try on your 8974 device and check if the
  pvs version reporting, scaling for higher frequencies are fine ?
  Sorry, i could not get hold of a 8974 device. So in-case if you still
  have the issues with higher frequencies, can you give a quick debug
  and report. That would be of great help.

Regards,
 Sricharan


> [v11]
>   * Dropped patch 13 and 14 from v10 and
>     merged the qcom-cpufreq-krait driver to the existing qcom-cpufreq-kryo.c
>   * Rebased on top of clk-next
>   * Fixed a bug while populating the pvs version for krait.
> 
> [v10]
>   * Addressed Stephen's comments to add clocks bindings properties
>     to the newly introduced nodes.
>   * Added a change to include opp-supported-hw to qcom-cpufreq.c
>   * Rebased on top of clk-next
>   * Although there were minor changes to bindings and the driver
>     retained the acked-by tags from Rob and Viresh respectively.    
> 
> [v9]
>   * Fixed a rebase issue in Makefile and added Tag from Robh.
> 
> [v8]
>   * Fixed a bug in path#14 pointed out by Viresh and also added tags.
>     No change in any other patch.
> 
> [v7]
>   * Fixed comments from Viresh for cleaning up the error handling
>     in qcom-cpufreq.c. Also changed the init function to lateinit
>     call. This is required because nvmem which gets initialised with
>     module_init needs to go first.
>   * Fixed Rob's comments for bindings documentation
>   * Fixed kbuild build issue in clk-lpc32xx.c
>   * Rebased on top of clk-next
> 
> [v6]
>   * Adrressed comments from Viresh for patch #14 in v5 [5]
>   * Introduced a new binding operating-points-v2-krait-cpu
>     as per discussion with Rob
>   * Added Review tags
> 
> [v5]
>   * Addressed comments from Rob for bindings
>   * Addressed comments from Viresh to use dev_pm_opp_set_prop_name, accordingly
>     dropped patch #12 and corrected patch #11 from previous patch set in [4]
>   * Converted to use #spdx tags for newly introduced files
> 
> Mostly a resend of the v3 posted by Stephen quite some time back [1]
> except for few changes.
>   Based on reading some feedback from list,
>   * Dropped the patch "clk: Add safe switch hook" from v3 [2].
>     Now this is taken care by patch#10 in this series only for Krait.
>   * Dropped the path "clk: Avoid sending high rates to downstream
> 		      clocks during set_rate" from v3 [3].
>   * Rebased on top of clk-next.
>   * Dropped the DT update from the series. Will send separately
>   * Now with cpufreq-dt+opp supporting voltage scaling, registering the
>     krait cpu supplies in DT should be sufficient. But one issue is,
>     the qcom-cpufreq drivers reads the efuse and based on that registers
>     the opp data and then registers the cpufreq-dt device. So when
>     cpufreq-dt driver probes and registers the regulator to the OPP framework,
>     it expects that the opp data for the device should not be registered before
>     the regulator. Will send a RFC patch removing that check, to find out the
>     right way of doing it.
> 
> These patches provide cpufreq scaling on devices with Krait CPUs.
> In Krait CPU designs there's one PLL and two muxes per CPU, allowing
> us to switch CPU frequencies independently.
> 
> 				 secondary
> 	 +-----+                    +
> 	 | QSB |-------+------------|\
> 	 +-----+       |            | |-+
> 		       |    +-------|/  |
> 		       |    |       +   |
> 	 +-----+       |    |           |
> 	 | PLL |----+-------+           |   primary
> 	 +-----+    |  |                |     +
> 		    |  |                +-----|\       +------+
> 	 +-------+  |  |                      | \      |      |
> 	 | HFPLL |----------+-----------------|  |-----| CPU0 |
> 	 +-------+  |  |    |                 |  |     |      |
> 		    |  |    | +-----+         | /      +------+
> 		    |  |    +-| / 2 |---------|/
> 		    |  |      +-----+         +
> 		    |  |         secondary
> 		    |  |            +
> 		    |  +------------|\
> 		    |               | |-+
> 		    +---------------|/  |   primary
> 				    +   |     +
> 					+-----|\       +------+
> 	 +-------+                            | \      |      |
> 	 | HFPLL |----------------------------|  |-----| CPU1 |
> 	 +-------+          |                 |  |     |      |
> 			    | +-----+         | /      +------+
> 			    +-| / 2 |---------|/
> 			      +-----+         +
> 
> To support this in the common clock framework we model the muxes,
> dividers, and PLLs as different clocks. CPUfreq only interacts
> with the primary mux (farthest right in the diagram). When CPUfreq
> sets a rate, the mux code finds the best parent that can provide the rate.
> Due to the design, QSB and the top PLL are always a fixed rate and thus
> only support one frequency each. These sources provide the lowest
> frequencies for the CPUs. The HFPLLs are where we can make the CPU go
> faster (GHz range). Sometimes we need to run the HFPLL twice as
> fast and divide it by two to get a particular frequency.
> 
> When switching rates we can't leave the CPU clocked by the HFPLL because
> we need to turn off the output of the PLL when changing its frequency.
> This means we have to switch over to the secondary mux and use one of the
> fixed sources. This is why we need something like the safe parent patch.
> 
> [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332607.html
> [2] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332615.html
> [3] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
> [4] https://lwn.net/Articles/740994/ 
> [5] https://lkml.org/lkml/2017/12/19/537
> 
> 
> Sricharan R (3):
>   clk: qcom: Add safe switch hook for krait mux clocks
>   cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem
>     based qcom socs
>   cpufreq: qcom: Add support for krait based socs
> 
> Stephen Boyd (11):
>   ARM: Add Krait L2 register accessor functions
>   clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
>   clk: qcom: Add HFPLL driver
>   dt-bindings: clock: Document qcom,hfpll
>   clk: qcom: Add MSM8960/APQ8064's HFPLLs
>   clk: qcom: Add IPQ806X's HFPLLs
>   clk: qcom: Add support for Krait clocks
>   clk: qcom: Add KPSS ACC/GCC driver
>   dt-bindings: arm: Document qcom,kpss-gcc
>   clk: qcom: Add Krait clock controller driver
>   dt-bindings: clock: Document qcom,krait-cc
> 
>  .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt  |  19 +
>  .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt  |  44 +++
>  .../devicetree/bindings/clock/qcom,hfpll.txt       |  60 ++++
>  .../devicetree/bindings/clock/qcom,krait-cc.txt    |  34 ++
>  .../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt}   |   7 +-
>  arch/arm/common/Kconfig                            |   3 +
>  arch/arm/common/Makefile                           |   1 +
>  arch/arm/common/krait-l2-accessors.c               |  48 +++
>  arch/arm/include/asm/krait-l2-accessors.h          |   9 +
>  drivers/clk/qcom/Kconfig                           |  28 ++
>  drivers/clk/qcom/Makefile                          |   5 +
>  drivers/clk/qcom/clk-hfpll.c                       | 244 +++++++++++++
>  drivers/clk/qcom/clk-hfpll.h                       |  44 +++
>  drivers/clk/qcom/clk-krait.c                       | 126 +++++++
>  drivers/clk/qcom/clk-krait.h                       |  40 +++
>  drivers/clk/qcom/gcc-ipq806x.c                     |  82 +++++
>  drivers/clk/qcom/gcc-msm8960.c                     | 172 +++++++++
>  drivers/clk/qcom/hfpll.c                           |  96 +++++
>  drivers/clk/qcom/kpss-xcc.c                        |  87 +++++
>  drivers/clk/qcom/krait-cc.c                        | 397 +++++++++++++++++++++
>  drivers/cpufreq/Kconfig.arm                        |   6 +-
>  drivers/cpufreq/Makefile                           |   2 +-
>  drivers/cpufreq/cpufreq-dt-platdev.c               |   5 +
>  drivers/cpufreq/qcom-cpufreq-kryo.c                | 232 ------------
>  drivers/cpufreq/qcom-cpufreq-nvmem.c               | 387 ++++++++++++++++++++
>  include/dt-bindings/clock/qcom,gcc-msm8960.h       |   2 +
>  26 files changed, 1941 insertions(+), 239 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
>  rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} (98%)
>  create mode 100644 arch/arm/common/krait-l2-accessors.c
>  create mode 100644 arch/arm/include/asm/krait-l2-accessors.h
>  create mode 100644 drivers/clk/qcom/clk-hfpll.c
>  create mode 100644 drivers/clk/qcom/clk-hfpll.h
>  create mode 100644 drivers/clk/qcom/clk-krait.c
>  create mode 100644 drivers/clk/qcom/clk-krait.h
>  create mode 100644 drivers/clk/qcom/hfpll.c
>  create mode 100644 drivers/clk/qcom/kpss-xcc.c
>  create mode 100644 drivers/clk/qcom/krait-cc.c
>  delete mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
>  create mode 100644 drivers/cpufreq/qcom-cpufreq-nvmem.c
> 

-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [PATCH v12 13/14] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs
  2018-08-14 12:12 ` [PATCH v12 13/14] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs Sricharan R
@ 2018-08-17 15:09   ` Rob Herring
  2018-08-20 12:45     ` Sricharan R
  0 siblings, 1 reply; 32+ messages in thread
From: Rob Herring @ 2018-08-17 15:09 UTC (permalink / raw)
  To: Sricharan R
  Cc: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel, sricharan

Hi, this email is from Rob's (experimental) review bot. I found a couple
of common problems with your patch. Please see below.

On Tue, 14 Aug 2018 17:42:32 +0530, Sricharan R wrote:
> The kryo cpufreq driver reads the nvmem cell and uses that data to
> populate the opps. There are other qcom cpufreq socs like krait which
> does similar thing. Except for the interpretation of the read data,
> rest of the driver is same for both the cases. So pull the common things
> out for reuse.
> 
> Signed-off-by: Sricharan R <sricharan@codeaurora.org>

The preferred subject prefix is "dt-bindings: <binding dir>: ...".

> ---
>  .../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt}   |   6 +-
>  drivers/cpufreq/Kconfig.arm                        |   4 +-
>  drivers/cpufreq/Makefile                           |   2 +-
>  .../{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c}  | 124 ++++++++++++---------
>  4 files changed, 80 insertions(+), 56 deletions(-)
>  rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} (99%)
>  rename drivers/cpufreq/{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} (65%)
> 

DT bindings (including binding headers) should be a separate patch. See
Documentation/devicetree/bindings/submitting-patches.txt.

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [PATCH v12 14/14] cpufreq: qcom: Add support for krait based socs
  2018-08-14 12:12 ` [PATCH v12 14/14] cpufreq: qcom: Add support for krait based socs Sricharan R
@ 2018-08-17 15:09   ` Rob Herring
  2018-08-24 15:21   ` Niklas Cassel
  2018-08-24 19:15   ` Niklas Cassel
  2 siblings, 0 replies; 32+ messages in thread
From: Rob Herring @ 2018-08-17 15:09 UTC (permalink / raw)
  To: Sricharan R
  Cc: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel, sricharan

Hi, this email is from Rob's (experimental) review bot. I found a couple
of common problems with your patch. Please see below.

On Tue, 14 Aug 2018 17:42:33 +0530, Sricharan R wrote:
> In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
> that has KRAIT processors the voltage/current value of each OPP
> varies based on the silicon variant in use.
> 
> The required OPP related data is determined based on
> the efuse value. This is similar to the existing code for
> kryo cores. So adding support for krait cores here.
> 
> Signed-off-by: Sricharan R <sricharan@codeaurora.org>

The preferred subject prefix is "dt-bindings: <binding dir>: ...".

> ---
>  .../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt |   3 +-
>  drivers/cpufreq/Kconfig.arm                        |   2 +-
>  drivers/cpufreq/cpufreq-dt-platdev.c               |   5 +
>  drivers/cpufreq/qcom-cpufreq-nvmem.c               | 151 +++++++++++++++++++--
>  4 files changed, 149 insertions(+), 12 deletions(-)
> 

DT bindings (including binding headers) should be a separate patch. See
Documentation/devicetree/bindings/submitting-patches.txt.

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [PATCH v12 13/14] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs
  2018-08-17 15:09   ` Rob Herring
@ 2018-08-20 12:45     ` Sricharan R
  0 siblings, 0 replies; 32+ messages in thread
From: Sricharan R @ 2018-08-20 12:45 UTC (permalink / raw)
  To: Rob Herring
  Cc: mark.rutland, sudeep.holla, linux, ctatlor97, rjw, viresh.kumar,
	mturquette, linux-pm, sboyd, linux, thierry.escande,
	linux-kernel, david.brown, devicetree, linux-arm-msm, andy.gross,
	linux-soc, linux-clk, linux-arm-kernel, niklas.cassel

Hi Rob,

On 8/17/2018 8:39 PM, Rob Herring wrote:
> Hi, this email is from Rob's (experimental) review bot. I found a couple
> of common problems with your patch. Please see below.
> 
> On Tue, 14 Aug 2018 17:42:32 +0530, Sricharan R wrote:
>> The kryo cpufreq driver reads the nvmem cell and uses that data to
>> populate the opps. There are other qcom cpufreq socs like krait which
>> does similar thing. Except for the interpretation of the read data,
>> rest of the driver is same for both the cases. So pull the common things
>> out for reuse.
>>
>> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
> 
> The preferred subject prefix is "dt-bindings: <binding dir>: ...".
> 

 ok, will change and keep the bindings update part out for this and the next
 patch.

Regards,
 Sricharan

-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [PATCH v12 14/14] cpufreq: qcom: Add support for krait based socs
  2018-08-14 12:12 ` [PATCH v12 14/14] cpufreq: qcom: Add support for krait based socs Sricharan R
  2018-08-17 15:09   ` Rob Herring
@ 2018-08-24 15:21   ` Niklas Cassel
  2018-08-24 19:15   ` Niklas Cassel
  2 siblings, 0 replies; 32+ messages in thread
From: Niklas Cassel @ 2018-08-24 15:21 UTC (permalink / raw)
  To: Sricharan R
  Cc: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel

On Tue, Aug 14, 2018 at 05:42:33PM +0530, Sricharan R wrote:
> In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
> that has KRAIT processors the voltage/current value of each OPP
> varies based on the silicon variant in use.
> 
> The required OPP related data is determined based on
> the efuse value. This is similar to the existing code for
> kryo cores. So adding support for krait cores here.
> 
> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
> ---
>  .../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt |   3 +-
>  drivers/cpufreq/Kconfig.arm                        |   2 +-
>  drivers/cpufreq/cpufreq-dt-platdev.c               |   5 +
>  drivers/cpufreq/qcom-cpufreq-nvmem.c               | 151 +++++++++++++++++++--
>  4 files changed, 149 insertions(+), 12 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
> index 6dcdfcd..7bc0f1a 100644
> --- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
> +++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
> @@ -19,7 +19,8 @@ In 'cpus' nodes:
>  
>  In 'operating-points-v2' table:
>  - compatible: Should be
> -	- 'operating-points-v2-qcom-cpu' for apq8096 and msm8996.
> +	- 'operating-points-v2-qcom-cpu' for apq8096, msm8996, msm8974,
> +					     apq8064, msm8960 and ipq8074.
>  - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
>  		efuse registers that has information about the
>  		speedbin that is used to select the right frequency/voltage

Hello Sricharan,

I see several references to kryo in this file that should probably be removed
or renamed.

Also, the documentation for opp-supported-hw lists how the different
bitmap values maps to the different compatible HW. It might be good to add a
note that the table is only for msm8996, and for orther SoCs, there is a 1:1
speedbin to opp-supported-hw mapping.


Kind regards,
Niklas


> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> index 13fbd97..497ae89 100644
> --- a/drivers/cpufreq/Kconfig.arm
> +++ b/drivers/cpufreq/Kconfig.arm
> @@ -126,7 +126,7 @@ config ARM_OMAP2PLUS_CPUFREQ
>  
>  config ARM_QCOM_CPUFREQ_NVMEM
>  	tristate "Qualcomm nvmem based CPUFreq"
> -	depends on ARM64
> +	depends on ARCH_QCOM
>  	depends on QCOM_QFPROM
>  	depends on QCOM_SMEM
>  	select PM_OPP
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
> index fe14c57..917cdc2 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -128,6 +128,11 @@
>  	{ .compatible = "ti,am43", },
>  	{ .compatible = "ti,dra7", },
>  
> +	{ .compatible = "qcom,ipq8064", },
> +	{ .compatible = "qcom,apq8064", },
> +	{ .compatible = "qcom,msm8974", },
> +	{ .compatible = "qcom,msm8960", },
> +
>  	{ }
>  };
>  
> diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> index 0ad8e5b..5f2add0 100644
> --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
> +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> @@ -45,6 +45,82 @@ enum _msm8996_version {
>  
>  static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
>  
> +static void __init get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver,
> +					  struct nvmem_cell *pvs_nvmem, u8 *buf)
> +{
> +	u32 pte_efuse;
> +
> +	pte_efuse = *((u32 *)buf);
> +
> +	*speed = pte_efuse & 0xf;
> +	if (*speed == 0xf)
> +		*speed = (pte_efuse >> 4) & 0xf;
> +
> +	if (*speed == 0xf) {
> +		*speed = 0;
> +		pr_warn("Speed bin: Defaulting to %d\n", *speed);
> +	} else {
> +		pr_info("Speed bin: %d\n", *speed);
> +	}
> +
> +	*pvs = (pte_efuse >> 10) & 0x7;
> +	if (*pvs == 0x7)
> +		*pvs = (pte_efuse >> 13) & 0x7;
> +
> +	if (*pvs == 0x7) {
> +		*pvs = 0;
> +		pr_warn("PVS bin: Defaulting to %d\n", *pvs);
> +	} else {
> +		pr_info("PVS bin: %d\n", *pvs);
> +	}
> +
> +	kfree(buf);
> +}
> +
> +static void __init get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver,
> +					  struct nvmem_cell *pvs_nvmem, u8 *buf)
> +{
> +	u32 pte_efuse, redundant_sel;
> +
> +	pte_efuse = *((u32 *)buf);
> +	redundant_sel = (pte_efuse >> 24) & 0x7;
> +	*speed = pte_efuse & 0x7;
> +
> +	/* 4 bits of PVS are in efuse register bits 31, 8-6. */
> +	*pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
> +	*pvs_ver = (pte_efuse >> 4) & 0x3;
> +
> +	switch (redundant_sel) {
> +	case 1:
> +		*speed = (pte_efuse >> 27) & 0xf;
> +		break;
> +	case 2:
> +		*pvs = (pte_efuse >> 27) & 0xf;
> +		break;
> +	}
> +
> +	/* Check SPEED_BIN_BLOW_STATUS */
> +	if (pte_efuse & BIT(3)) {
> +		pr_info("Speed bin: %d\n", *speed);
> +	} else {
> +		pr_warn("Speed bin not set. Defaulting to 0!\n");
> +		*speed = 0;
> +	}
> +
> +	/* Check PVS_BLOW_STATUS */
> +	pte_efuse = *(((u32 *)buf) + 4);
> +	pte_efuse &= BIT(21);
> +	if (pte_efuse) {
> +		pr_info("PVS bin: %d\n", *pvs);
> +	} else {
> +		pr_warn("PVS bin not set. Defaulting to 0!\n");
> +		*pvs = 0;
> +	}
> +
> +	pr_info("PVS version: %d\n", *pvs_ver);
> +	kfree(buf);
> +}
> +
>  static enum _msm8996_version __init qcom_cpufreq_get_msm_id(void)
>  {
>  	size_t len;
> @@ -74,6 +150,35 @@ static enum _msm8996_version __init qcom_cpufreq_get_msm_id(void)
>  	return version;
>  }
>  
> +static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
> +					   struct nvmem_cell *speedbin_nvmem,
> +					   char **name,
> +					   u32 *versions)
> +{
> +	int speed = 0, pvs = 0, pvs_ver = 0;
> +	u8 *buf;
> +	size_t len;
> +
> +	buf = nvmem_cell_read(speedbin_nvmem, &len);
> +	if (len == 4) {
> +		get_krait_bin_format_a(&speed, &pvs, &pvs_ver,
> +				       speedbin_nvmem, buf);
> +	} else if (len == 8) {
> +		get_krait_bin_format_b(&speed, &pvs, &pvs_ver,
> +				       speedbin_nvmem, buf);
> +	} else {
> +		dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
> +		return -ENODEV;
> +	}
> +
> +	snprintf(*name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
> +		 speed, pvs, pvs_ver);
> +
> +	*versions = (1 << speed);
> +
> +	return 0;
> +}
> +
>  static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
>  					  struct nvmem_cell *speedbin_nvmem,
>  					  char **pvs_name,
> @@ -83,6 +188,7 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
>  	u8 *speedbin;
>  	enum _msm8996_version msm8996_version;
>  
> +	*pvs_name = NULL;
>  	msm8996_version = qcom_cpufreq_get_msm_id();
>  	if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
>  		dev_err(cpu_dev, "Not Snapdragon 820/821!");
> @@ -111,7 +217,7 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
>  
>  static int qcom_cpufreq_probe(struct platform_device *pdev)
>  {
> -	struct opp_table *opp_tables[NR_CPUS] = { NULL };
> +	struct opp_table *tbl1[NR_CPUS] = { NULL }, *tbl2[NR_CPUS] = { NULL };
>  	int (*get_version)(struct device *cpu_dev,
>  			   struct nvmem_cell *speedbin_nvmem,
>  			   char **name, int *versions);
> @@ -120,8 +226,8 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
>  	struct device *cpu_dev;
>  	unsigned cpu;
>  	u32 versions;
> -	char *pvs_name = NULL;
>  	const struct of_device_id *match;
> +	char *pvs_name = "speedXX-pvsXX-vXX";
>  	int ret;
>  
>  	cpu_dev = get_cpu_device(0);
> @@ -163,10 +269,19 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
>  			goto free_opp;
>  		}
>  
> -		opp_tables[cpu] = dev_pm_opp_set_supported_hw(cpu_dev,
> -							      &versions, 1);
> -		if (IS_ERR(opp_tables[cpu])) {
> -			ret = PTR_ERR(opp_tables[cpu]);
> +		if (pvs_name) {
> +			tbl1[cpu] = dev_pm_opp_set_prop_name(cpu_dev, pvs_name);
> +			if (IS_ERR(tbl1[cpu])) {
> +				ret = PTR_ERR(tbl1[cpu]);
> +				dev_err(cpu_dev, "Failed to add OPP name %s\n",
> +					pvs_name);
> +				goto free_opp;
> +			}
> +		}
> +
> +		tbl2[cpu] = dev_pm_opp_set_supported_hw(cpu_dev, &versions, 1);
> +		if (IS_ERR(tbl2[cpu])) {
> +			ret = PTR_ERR(tbl2[cpu]);
>  			dev_err(cpu_dev, "Failed to set supported hardware\n");
>  			goto free_opp;
>  		}
> @@ -182,9 +297,15 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
>  
>  free_opp:
>  	for_each_possible_cpu(cpu) {
> -		if (IS_ERR_OR_NULL(opp_tables[cpu]))
> +		if (IS_ERR_OR_NULL(tbl1[cpu]))
> +			break;
> +		dev_pm_opp_put_prop_name(tbl1[cpu]);
> +	}
> +
> +	for_each_possible_cpu(cpu) {
> +		if (IS_ERR_OR_NULL(tbl2[cpu]))
>  			break;
> -		dev_pm_opp_put_supported_hw(opp_tables[cpu]);
> +		dev_pm_opp_put_supported_hw(tbl2[cpu]);
>  	}
>  
>  	return ret;
> @@ -205,8 +326,18 @@ static int qcom_cpufreq_remove(struct platform_device *pdev)
>  };
>  
>  static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
> -	{ .compatible = "qcom,apq8096", .data = qcom_cpufreq_kryo_name_version},
> -	{ .compatible = "qcom,msm8996", .data = qcom_cpufreq_kryo_name_version},
> +	{ .compatible = "qcom,apq8096",
> +	  .data = qcom_cpufreq_kryo_name_version},
> +	{ .compatible = "qcom,msm8996",
> +	  .data = qcom_cpufreq_kryo_name_version},
> +	{ .compatible = "qcom,ipq8064",
> +	  .data = qcom_cpufreq_krait_name_version },
> +	{ .compatible = "qcom,apq8064",
> +	  .data = qcom_cpufreq_krait_name_version },
> +	{ .compatible = "qcom,msm8974",
> +	  .data = qcom_cpufreq_krait_name_version },
> +	{ .compatible = "qcom,msm8960",
> +	  .data = qcom_cpufreq_krait_name_version },
>  	{},
>  };
>  
> -- 
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
> 

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [PATCH v12 14/14] cpufreq: qcom: Add support for krait based socs
  2018-08-14 12:12 ` [PATCH v12 14/14] cpufreq: qcom: Add support for krait based socs Sricharan R
  2018-08-17 15:09   ` Rob Herring
  2018-08-24 15:21   ` Niklas Cassel
@ 2018-08-24 19:15   ` Niklas Cassel
  2 siblings, 0 replies; 32+ messages in thread
From: Niklas Cassel @ 2018-08-24 19:15 UTC (permalink / raw)
  To: Sricharan R
  Cc: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel

On Tue, Aug 14, 2018 at 05:42:33PM +0530, Sricharan R wrote:
> In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
> that has KRAIT processors the voltage/current value of each OPP
> varies based on the silicon variant in use.
> 
> The required OPP related data is determined based on
> the efuse value. This is similar to the existing code for
> kryo cores. So adding support for krait cores here.
> 
> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
> ---
>  .../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt |   3 +-
>  drivers/cpufreq/Kconfig.arm                        |   2 +-
>  drivers/cpufreq/cpufreq-dt-platdev.c               |   5 +
>  drivers/cpufreq/qcom-cpufreq-nvmem.c               | 151 +++++++++++++++++++--
>  4 files changed, 149 insertions(+), 12 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
> index 6dcdfcd..7bc0f1a 100644
> --- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
> +++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
> @@ -19,7 +19,8 @@ In 'cpus' nodes:
>  
>  In 'operating-points-v2' table:
>  - compatible: Should be
> -	- 'operating-points-v2-qcom-cpu' for apq8096 and msm8996.
> +	- 'operating-points-v2-qcom-cpu' for apq8096, msm8996, msm8974,
> +					     apq8064, msm8960 and ipq8074.
>  - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
>  		efuse registers that has information about the
>  		speedbin that is used to select the right frequency/voltage
> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> index 13fbd97..497ae89 100644
> --- a/drivers/cpufreq/Kconfig.arm
> +++ b/drivers/cpufreq/Kconfig.arm
> @@ -126,7 +126,7 @@ config ARM_OMAP2PLUS_CPUFREQ
>  
>  config ARM_QCOM_CPUFREQ_NVMEM
>  	tristate "Qualcomm nvmem based CPUFreq"
> -	depends on ARM64
> +	depends on ARCH_QCOM
>  	depends on QCOM_QFPROM
>  	depends on QCOM_SMEM
>  	select PM_OPP
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
> index fe14c57..917cdc2 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -128,6 +128,11 @@
>  	{ .compatible = "ti,am43", },
>  	{ .compatible = "ti,dra7", },
>  
> +	{ .compatible = "qcom,ipq8064", },
> +	{ .compatible = "qcom,apq8064", },
> +	{ .compatible = "qcom,msm8974", },
> +	{ .compatible = "qcom,msm8960", },
> +
>  	{ }
>  };
>  
> diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> index 0ad8e5b..5f2add0 100644
> --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
> +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> @@ -45,6 +45,82 @@ enum _msm8996_version {
>  
>  static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
>  
> +static void __init get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver,
> +					  struct nvmem_cell *pvs_nvmem, u8 *buf)

Hello Sricharan,

pvs_nvmem seems to be unused both here and in get_krait_bin_format_b().

Kind regards,
Niklas

> +{
> +	u32 pte_efuse;
> +
> +	pte_efuse = *((u32 *)buf);
> +
> +	*speed = pte_efuse & 0xf;
> +	if (*speed == 0xf)
> +		*speed = (pte_efuse >> 4) & 0xf;
> +
> +	if (*speed == 0xf) {
> +		*speed = 0;
> +		pr_warn("Speed bin: Defaulting to %d\n", *speed);
> +	} else {
> +		pr_info("Speed bin: %d\n", *speed);
> +	}
> +
> +	*pvs = (pte_efuse >> 10) & 0x7;
> +	if (*pvs == 0x7)
> +		*pvs = (pte_efuse >> 13) & 0x7;
> +
> +	if (*pvs == 0x7) {
> +		*pvs = 0;
> +		pr_warn("PVS bin: Defaulting to %d\n", *pvs);
> +	} else {
> +		pr_info("PVS bin: %d\n", *pvs);
> +	}
> +
> +	kfree(buf);
> +}
> +
> +static void __init get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver,
> +					  struct nvmem_cell *pvs_nvmem, u8 *buf)
> +{
> +	u32 pte_efuse, redundant_sel;
> +
> +	pte_efuse = *((u32 *)buf);
> +	redundant_sel = (pte_efuse >> 24) & 0x7;
> +	*speed = pte_efuse & 0x7;
> +
> +	/* 4 bits of PVS are in efuse register bits 31, 8-6. */
> +	*pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
> +	*pvs_ver = (pte_efuse >> 4) & 0x3;
> +
> +	switch (redundant_sel) {
> +	case 1:
> +		*speed = (pte_efuse >> 27) & 0xf;
> +		break;
> +	case 2:
> +		*pvs = (pte_efuse >> 27) & 0xf;
> +		break;
> +	}
> +
> +	/* Check SPEED_BIN_BLOW_STATUS */
> +	if (pte_efuse & BIT(3)) {
> +		pr_info("Speed bin: %d\n", *speed);
> +	} else {
> +		pr_warn("Speed bin not set. Defaulting to 0!\n");
> +		*speed = 0;
> +	}
> +
> +	/* Check PVS_BLOW_STATUS */
> +	pte_efuse = *(((u32 *)buf) + 4);
> +	pte_efuse &= BIT(21);
> +	if (pte_efuse) {
> +		pr_info("PVS bin: %d\n", *pvs);
> +	} else {
> +		pr_warn("PVS bin not set. Defaulting to 0!\n");
> +		*pvs = 0;
> +	}
> +
> +	pr_info("PVS version: %d\n", *pvs_ver);
> +	kfree(buf);
> +}
> +
>  static enum _msm8996_version __init qcom_cpufreq_get_msm_id(void)
>  {
>  	size_t len;
> @@ -74,6 +150,35 @@ static enum _msm8996_version __init qcom_cpufreq_get_msm_id(void)
>  	return version;
>  }
>  
> +static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
> +					   struct nvmem_cell *speedbin_nvmem,
> +					   char **name,
> +					   u32 *versions)
> +{
> +	int speed = 0, pvs = 0, pvs_ver = 0;
> +	u8 *buf;
> +	size_t len;
> +
> +	buf = nvmem_cell_read(speedbin_nvmem, &len);
> +	if (len == 4) {
> +		get_krait_bin_format_a(&speed, &pvs, &pvs_ver,
> +				       speedbin_nvmem, buf);
> +	} else if (len == 8) {
> +		get_krait_bin_format_b(&speed, &pvs, &pvs_ver,
> +				       speedbin_nvmem, buf);
> +	} else {
> +		dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
> +		return -ENODEV;
> +	}
> +
> +	snprintf(*name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
> +		 speed, pvs, pvs_ver);
> +
> +	*versions = (1 << speed);
> +
> +	return 0;
> +}
> +
>  static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
>  					  struct nvmem_cell *speedbin_nvmem,
>  					  char **pvs_name,
> @@ -83,6 +188,7 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
>  	u8 *speedbin;
>  	enum _msm8996_version msm8996_version;
>  
> +	*pvs_name = NULL;
>  	msm8996_version = qcom_cpufreq_get_msm_id();
>  	if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
>  		dev_err(cpu_dev, "Not Snapdragon 820/821!");
> @@ -111,7 +217,7 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
>  
>  static int qcom_cpufreq_probe(struct platform_device *pdev)
>  {
> -	struct opp_table *opp_tables[NR_CPUS] = { NULL };
> +	struct opp_table *tbl1[NR_CPUS] = { NULL }, *tbl2[NR_CPUS] = { NULL };
>  	int (*get_version)(struct device *cpu_dev,
>  			   struct nvmem_cell *speedbin_nvmem,
>  			   char **name, int *versions);
> @@ -120,8 +226,8 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
>  	struct device *cpu_dev;
>  	unsigned cpu;
>  	u32 versions;
> -	char *pvs_name = NULL;
>  	const struct of_device_id *match;
> +	char *pvs_name = "speedXX-pvsXX-vXX";
>  	int ret;
>  
>  	cpu_dev = get_cpu_device(0);
> @@ -163,10 +269,19 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
>  			goto free_opp;
>  		}
>  
> -		opp_tables[cpu] = dev_pm_opp_set_supported_hw(cpu_dev,
> -							      &versions, 1);
> -		if (IS_ERR(opp_tables[cpu])) {
> -			ret = PTR_ERR(opp_tables[cpu]);
> +		if (pvs_name) {
> +			tbl1[cpu] = dev_pm_opp_set_prop_name(cpu_dev, pvs_name);
> +			if (IS_ERR(tbl1[cpu])) {
> +				ret = PTR_ERR(tbl1[cpu]);
> +				dev_err(cpu_dev, "Failed to add OPP name %s\n",
> +					pvs_name);
> +				goto free_opp;
> +			}
> +		}
> +
> +		tbl2[cpu] = dev_pm_opp_set_supported_hw(cpu_dev, &versions, 1);
> +		if (IS_ERR(tbl2[cpu])) {
> +			ret = PTR_ERR(tbl2[cpu]);
>  			dev_err(cpu_dev, "Failed to set supported hardware\n");
>  			goto free_opp;
>  		}
> @@ -182,9 +297,15 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
>  
>  free_opp:
>  	for_each_possible_cpu(cpu) {
> -		if (IS_ERR_OR_NULL(opp_tables[cpu]))
> +		if (IS_ERR_OR_NULL(tbl1[cpu]))
> +			break;
> +		dev_pm_opp_put_prop_name(tbl1[cpu]);
> +	}
> +
> +	for_each_possible_cpu(cpu) {
> +		if (IS_ERR_OR_NULL(tbl2[cpu]))
>  			break;
> -		dev_pm_opp_put_supported_hw(opp_tables[cpu]);
> +		dev_pm_opp_put_supported_hw(tbl2[cpu]);
>  	}
>  
>  	return ret;
> @@ -205,8 +326,18 @@ static int qcom_cpufreq_remove(struct platform_device *pdev)
>  };
>  
>  static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
> -	{ .compatible = "qcom,apq8096", .data = qcom_cpufreq_kryo_name_version},
> -	{ .compatible = "qcom,msm8996", .data = qcom_cpufreq_kryo_name_version},
> +	{ .compatible = "qcom,apq8096",
> +	  .data = qcom_cpufreq_kryo_name_version},
> +	{ .compatible = "qcom,msm8996",
> +	  .data = qcom_cpufreq_kryo_name_version},
> +	{ .compatible = "qcom,ipq8064",
> +	  .data = qcom_cpufreq_krait_name_version },
> +	{ .compatible = "qcom,apq8064",
> +	  .data = qcom_cpufreq_krait_name_version },
> +	{ .compatible = "qcom,msm8974",
> +	  .data = qcom_cpufreq_krait_name_version },
> +	{ .compatible = "qcom,msm8960",
> +	  .data = qcom_cpufreq_krait_name_version },
>  	{},
>  };
>  
> -- 
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
> 

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
  2018-08-14 12:20 ` [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
@ 2018-09-07  9:57   ` Sricharan R
  2018-09-07 14:28     ` Craig Tatlor
  0 siblings, 1 reply; 32+ messages in thread
From: Sricharan R @ 2018-09-07  9:57 UTC (permalink / raw)
  To: mark.rutland, robh, sudeep.holla, linux, ctatlor97, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel

Hi Craig,


>> [v12]
>>   * Added my signed-off that was missing in some patches.
>>   * Added Bjorn's acked that i missed earlier.
>>
> 
>   Can you give this a try on your 8974 device and check if the
>   pvs version reporting, scaling for higher frequencies are fine ?
>   Sorry, i could not get hold of a 8974 device. So in-case if you still
>   have the issues with higher frequencies, can you give a quick debug
>   and report. That would be of great help.
> 
   Ping on this ..

Regards,
 Sricharan

> Regards,
>  Sricharan
> 
> 
>> [v11]
>>   * Dropped patch 13 and 14 from v10 and
>>     merged the qcom-cpufreq-krait driver to the existing qcom-cpufreq-kryo.c
>>   * Rebased on top of clk-next
>>   * Fixed a bug while populating the pvs version for krait.
>>
>> [v10]
>>   * Addressed Stephen's comments to add clocks bindings properties
>>     to the newly introduced nodes.
>>   * Added a change to include opp-supported-hw to qcom-cpufreq.c
>>   * Rebased on top of clk-next
>>   * Although there were minor changes to bindings and the driver
>>     retained the acked-by tags from Rob and Viresh respectively.    
>>
>> [v9]
>>   * Fixed a rebase issue in Makefile and added Tag from Robh.
>>
>> [v8]
>>   * Fixed a bug in path#14 pointed out by Viresh and also added tags.
>>     No change in any other patch.
>>
>> [v7]
>>   * Fixed comments from Viresh for cleaning up the error handling
>>     in qcom-cpufreq.c. Also changed the init function to lateinit
>>     call. This is required because nvmem which gets initialised with
>>     module_init needs to go first.
>>   * Fixed Rob's comments for bindings documentation
>>   * Fixed kbuild build issue in clk-lpc32xx.c
>>   * Rebased on top of clk-next
>>
>> [v6]
>>   * Adrressed comments from Viresh for patch #14 in v5 [5]
>>   * Introduced a new binding operating-points-v2-krait-cpu
>>     as per discussion with Rob
>>   * Added Review tags
>>
>> [v5]
>>   * Addressed comments from Rob for bindings
>>   * Addressed comments from Viresh to use dev_pm_opp_set_prop_name, accordingly
>>     dropped patch #12 and corrected patch #11 from previous patch set in [4]
>>   * Converted to use #spdx tags for newly introduced files
>>
>> Mostly a resend of the v3 posted by Stephen quite some time back [1]
>> except for few changes.
>>   Based on reading some feedback from list,
>>   * Dropped the patch "clk: Add safe switch hook" from v3 [2].
>>     Now this is taken care by patch#10 in this series only for Krait.
>>   * Dropped the path "clk: Avoid sending high rates to downstream
>> 		      clocks during set_rate" from v3 [3].
>>   * Rebased on top of clk-next.
>>   * Dropped the DT update from the series. Will send separately
>>   * Now with cpufreq-dt+opp supporting voltage scaling, registering the
>>     krait cpu supplies in DT should be sufficient. But one issue is,
>>     the qcom-cpufreq drivers reads the efuse and based on that registers
>>     the opp data and then registers the cpufreq-dt device. So when
>>     cpufreq-dt driver probes and registers the regulator to the OPP framework,
>>     it expects that the opp data for the device should not be registered before
>>     the regulator. Will send a RFC patch removing that check, to find out the
>>     right way of doing it.
>>
>> These patches provide cpufreq scaling on devices with Krait CPUs.
>> In Krait CPU designs there's one PLL and two muxes per CPU, allowing
>> us to switch CPU frequencies independently.
>>
>> 				 secondary
>> 	 +-----+                    +
>> 	 | QSB |-------+------------|\
>> 	 +-----+       |            | |-+
>> 		       |    +-------|/  |
>> 		       |    |       +   |
>> 	 +-----+       |    |           |
>> 	 | PLL |----+-------+           |   primary
>> 	 +-----+    |  |                |     +
>> 		    |  |                +-----|\       +------+
>> 	 +-------+  |  |                      | \      |      |
>> 	 | HFPLL |----------+-----------------|  |-----| CPU0 |
>> 	 +-------+  |  |    |                 |  |     |      |
>> 		    |  |    | +-----+         | /      +------+
>> 		    |  |    +-| / 2 |---------|/
>> 		    |  |      +-----+         +
>> 		    |  |         secondary
>> 		    |  |            +
>> 		    |  +------------|\
>> 		    |               | |-+
>> 		    +---------------|/  |   primary
>> 				    +   |     +
>> 					+-----|\       +------+
>> 	 +-------+                            | \      |      |
>> 	 | HFPLL |----------------------------|  |-----| CPU1 |
>> 	 +-------+          |                 |  |     |      |
>> 			    | +-----+         | /      +------+
>> 			    +-| / 2 |---------|/
>> 			      +-----+         +
>>
>> To support this in the common clock framework we model the muxes,
>> dividers, and PLLs as different clocks. CPUfreq only interacts
>> with the primary mux (farthest right in the diagram). When CPUfreq
>> sets a rate, the mux code finds the best parent that can provide the rate.
>> Due to the design, QSB and the top PLL are always a fixed rate and thus
>> only support one frequency each. These sources provide the lowest
>> frequencies for the CPUs. The HFPLLs are where we can make the CPU go
>> faster (GHz range). Sometimes we need to run the HFPLL twice as
>> fast and divide it by two to get a particular frequency.
>>
>> When switching rates we can't leave the CPU clocked by the HFPLL because
>> we need to turn off the output of the PLL when changing its frequency.
>> This means we have to switch over to the secondary mux and use one of the
>> fixed sources. This is why we need something like the safe parent patch.
>>
>> [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332607.html
>> [2] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332615.html
>> [3] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
>> [4] https://lwn.net/Articles/740994/ 
>> [5] https://lkml.org/lkml/2017/12/19/537
>>
>>
>> Sricharan R (3):
>>   clk: qcom: Add safe switch hook for krait mux clocks
>>   cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem
>>     based qcom socs
>>   cpufreq: qcom: Add support for krait based socs
>>
>> Stephen Boyd (11):
>>   ARM: Add Krait L2 register accessor functions
>>   clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
>>   clk: qcom: Add HFPLL driver
>>   dt-bindings: clock: Document qcom,hfpll
>>   clk: qcom: Add MSM8960/APQ8064's HFPLLs
>>   clk: qcom: Add IPQ806X's HFPLLs
>>   clk: qcom: Add support for Krait clocks
>>   clk: qcom: Add KPSS ACC/GCC driver
>>   dt-bindings: arm: Document qcom,kpss-gcc
>>   clk: qcom: Add Krait clock controller driver
>>   dt-bindings: clock: Document qcom,krait-cc
>>
>>  .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt  |  19 +
>>  .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt  |  44 +++
>>  .../devicetree/bindings/clock/qcom,hfpll.txt       |  60 ++++
>>  .../devicetree/bindings/clock/qcom,krait-cc.txt    |  34 ++
>>  .../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt}   |   7 +-
>>  arch/arm/common/Kconfig                            |   3 +
>>  arch/arm/common/Makefile                           |   1 +
>>  arch/arm/common/krait-l2-accessors.c               |  48 +++
>>  arch/arm/include/asm/krait-l2-accessors.h          |   9 +
>>  drivers/clk/qcom/Kconfig                           |  28 ++
>>  drivers/clk/qcom/Makefile                          |   5 +
>>  drivers/clk/qcom/clk-hfpll.c                       | 244 +++++++++++++
>>  drivers/clk/qcom/clk-hfpll.h                       |  44 +++
>>  drivers/clk/qcom/clk-krait.c                       | 126 +++++++
>>  drivers/clk/qcom/clk-krait.h                       |  40 +++
>>  drivers/clk/qcom/gcc-ipq806x.c                     |  82 +++++
>>  drivers/clk/qcom/gcc-msm8960.c                     | 172 +++++++++
>>  drivers/clk/qcom/hfpll.c                           |  96 +++++
>>  drivers/clk/qcom/kpss-xcc.c                        |  87 +++++
>>  drivers/clk/qcom/krait-cc.c                        | 397 +++++++++++++++++++++
>>  drivers/cpufreq/Kconfig.arm                        |   6 +-
>>  drivers/cpufreq/Makefile                           |   2 +-
>>  drivers/cpufreq/cpufreq-dt-platdev.c               |   5 +
>>  drivers/cpufreq/qcom-cpufreq-kryo.c                | 232 ------------
>>  drivers/cpufreq/qcom-cpufreq-nvmem.c               | 387 ++++++++++++++++++++
>>  include/dt-bindings/clock/qcom,gcc-msm8960.h       |   2 +
>>  26 files changed, 1941 insertions(+), 239 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
>>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
>>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
>>  rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} (98%)
>>  create mode 100644 arch/arm/common/krait-l2-accessors.c
>>  create mode 100644 arch/arm/include/asm/krait-l2-accessors.h
>>  create mode 100644 drivers/clk/qcom/clk-hfpll.c
>>  create mode 100644 drivers/clk/qcom/clk-hfpll.h
>>  create mode 100644 drivers/clk/qcom/clk-krait.c
>>  create mode 100644 drivers/clk/qcom/clk-krait.h
>>  create mode 100644 drivers/clk/qcom/hfpll.c
>>  create mode 100644 drivers/clk/qcom/kpss-xcc.c
>>  create mode 100644 drivers/clk/qcom/krait-cc.c
>>  delete mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
>>  create mode 100644 drivers/cpufreq/qcom-cpufreq-nvmem.c
>>
> 

-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
  2018-09-07  9:57   ` Sricharan R
@ 2018-09-07 14:28     ` Craig Tatlor
  2018-09-19 20:24       ` Craig
  0 siblings, 1 reply; 32+ messages in thread
From: Craig Tatlor @ 2018-09-07 14:28 UTC (permalink / raw)
  To: Sricharan R, mark.rutland, robh, sudeep.holla, linux, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel



On 7 September 2018 10:57:34 BST, Sricharan R <sricharan@codeaurora.org> wrote:
>Hi Craig,
>
>
>>> [v12]
>>>   * Added my signed-off that was missing in some patches.
>>>   * Added Bjorn's acked that i missed earlier.
>>>
>> 
>>   Can you give this a try on your 8974 device and check if the
>>   pvs version reporting, scaling for higher frequencies are fine ?
>>   Sorry, i could not get hold of a 8974 device. So in-case if you
>still
>>   have the issues with higher frequencies, can you give a quick debug
>>   and report. That would be of great help.
>> 
>   Ping on this ..

Hi, didn't see your last message,

Will have a try on mine in the weekend and report back.
>
>Regards,
> Sricharan
>
>> Regards,
>>  Sricharan
>> 
>> 
>>> [v11]
>>>   * Dropped patch 13 and 14 from v10 and
>>>     merged the qcom-cpufreq-krait driver to the existing
>qcom-cpufreq-kryo.c
>>>   * Rebased on top of clk-next
>>>   * Fixed a bug while populating the pvs version for krait.
>>>
>>> [v10]
>>>   * Addressed Stephen's comments to add clocks bindings properties
>>>     to the newly introduced nodes.
>>>   * Added a change to include opp-supported-hw to qcom-cpufreq.c
>>>   * Rebased on top of clk-next
>>>   * Although there were minor changes to bindings and the driver
>>>     retained the acked-by tags from Rob and Viresh respectively.    
>>>
>>> [v9]
>>>   * Fixed a rebase issue in Makefile and added Tag from Robh.
>>>
>>> [v8]
>>>   * Fixed a bug in path#14 pointed out by Viresh and also added
>tags.
>>>     No change in any other patch.
>>>
>>> [v7]
>>>   * Fixed comments from Viresh for cleaning up the error handling
>>>     in qcom-cpufreq.c. Also changed the init function to lateinit
>>>     call. This is required because nvmem which gets initialised with
>>>     module_init needs to go first.
>>>   * Fixed Rob's comments for bindings documentation
>>>   * Fixed kbuild build issue in clk-lpc32xx.c
>>>   * Rebased on top of clk-next
>>>
>>> [v6]
>>>   * Adrressed comments from Viresh for patch #14 in v5 [5]
>>>   * Introduced a new binding operating-points-v2-krait-cpu
>>>     as per discussion with Rob
>>>   * Added Review tags
>>>
>>> [v5]
>>>   * Addressed comments from Rob for bindings
>>>   * Addressed comments from Viresh to use dev_pm_opp_set_prop_name,
>accordingly
>>>     dropped patch #12 and corrected patch #11 from previous patch
>set in [4]
>>>   * Converted to use #spdx tags for newly introduced files
>>>
>>> Mostly a resend of the v3 posted by Stephen quite some time back [1]
>>> except for few changes.
>>>   Based on reading some feedback from list,
>>>   * Dropped the patch "clk: Add safe switch hook" from v3 [2].
>>>     Now this is taken care by patch#10 in this series only for
>Krait.
>>>   * Dropped the path "clk: Avoid sending high rates to downstream
>>> 		      clocks during set_rate" from v3 [3].
>>>   * Rebased on top of clk-next.
>>>   * Dropped the DT update from the series. Will send separately
>>>   * Now with cpufreq-dt+opp supporting voltage scaling, registering
>the
>>>     krait cpu supplies in DT should be sufficient. But one issue is,
>>>     the qcom-cpufreq drivers reads the efuse and based on that
>registers
>>>     the opp data and then registers the cpufreq-dt device. So when
>>>     cpufreq-dt driver probes and registers the regulator to the OPP
>framework,
>>>     it expects that the opp data for the device should not be
>registered before
>>>     the regulator. Will send a RFC patch removing that check, to
>find out the
>>>     right way of doing it.
>>>
>>> These patches provide cpufreq scaling on devices with Krait CPUs.
>>> In Krait CPU designs there's one PLL and two muxes per CPU, allowing
>>> us to switch CPU frequencies independently.
>>>
>>> 				 secondary
>>> 	 +-----+                    +
>>> 	 | QSB |-------+------------|\
>>> 	 +-----+       |            | |-+
>>> 		       |    +-------|/  |
>>> 		       |    |       +   |
>>> 	 +-----+       |    |           |
>>> 	 | PLL |----+-------+           |   primary
>>> 	 +-----+    |  |                |     +
>>> 		    |  |                +-----|\       +------+
>>> 	 +-------+  |  |                      | \      |      |
>>> 	 | HFPLL |----------+-----------------|  |-----| CPU0 |
>>> 	 +-------+  |  |    |                 |  |     |      |
>>> 		    |  |    | +-----+         | /      +------+
>>> 		    |  |    +-| / 2 |---------|/
>>> 		    |  |      +-----+         +
>>> 		    |  |         secondary
>>> 		    |  |            +
>>> 		    |  +------------|\
>>> 		    |               | |-+
>>> 		    +---------------|/  |   primary
>>> 				    +   |     +
>>> 					+-----|\       +------+
>>> 	 +-------+                            | \      |      |
>>> 	 | HFPLL |----------------------------|  |-----| CPU1 |
>>> 	 +-------+          |                 |  |     |      |
>>> 			    | +-----+         | /      +------+
>>> 			    +-| / 2 |---------|/
>>> 			      +-----+         +
>>>
>>> To support this in the common clock framework we model the muxes,
>>> dividers, and PLLs as different clocks. CPUfreq only interacts
>>> with the primary mux (farthest right in the diagram). When CPUfreq
>>> sets a rate, the mux code finds the best parent that can provide the
>rate.
>>> Due to the design, QSB and the top PLL are always a fixed rate and
>thus
>>> only support one frequency each. These sources provide the lowest
>>> frequencies for the CPUs. The HFPLLs are where we can make the CPU
>go
>>> faster (GHz range). Sometimes we need to run the HFPLL twice as
>>> fast and divide it by two to get a particular frequency.
>>>
>>> When switching rates we can't leave the CPU clocked by the HFPLL
>because
>>> we need to turn off the output of the PLL when changing its
>frequency.
>>> This means we have to switch over to the secondary mux and use one
>of the
>>> fixed sources. This is why we need something like the safe parent
>patch.
>>>
>>> [1]
>http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332607.html
>>> [2]
>http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332615.html
>>> [3]
>http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
>>> [4] https://lwn.net/Articles/740994/ 
>>> [5] https://lkml.org/lkml/2017/12/19/537
>>>
>>>
>>> Sricharan R (3):
>>>   clk: qcom: Add safe switch hook for krait mux clocks
>>>   cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem
>>>     based qcom socs
>>>   cpufreq: qcom: Add support for krait based socs
>>>
>>> Stephen Boyd (11):
>>>   ARM: Add Krait L2 register accessor functions
>>>   clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
>>>   clk: qcom: Add HFPLL driver
>>>   dt-bindings: clock: Document qcom,hfpll
>>>   clk: qcom: Add MSM8960/APQ8064's HFPLLs
>>>   clk: qcom: Add IPQ806X's HFPLLs
>>>   clk: qcom: Add support for Krait clocks
>>>   clk: qcom: Add KPSS ACC/GCC driver
>>>   dt-bindings: arm: Document qcom,kpss-gcc
>>>   clk: qcom: Add Krait clock controller driver
>>>   dt-bindings: clock: Document qcom,krait-cc
>>>
>>>  .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt  |  19 +
>>>  .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt  |  44 +++
>>>  .../devicetree/bindings/clock/qcom,hfpll.txt       |  60 ++++
>>>  .../devicetree/bindings/clock/qcom,krait-cc.txt    |  34 ++
>>>  .../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt}   |   7 +-
>>>  arch/arm/common/Kconfig                            |   3 +
>>>  arch/arm/common/Makefile                           |   1 +
>>>  arch/arm/common/krait-l2-accessors.c               |  48 +++
>>>  arch/arm/include/asm/krait-l2-accessors.h          |   9 +
>>>  drivers/clk/qcom/Kconfig                           |  28 ++
>>>  drivers/clk/qcom/Makefile                          |   5 +
>>>  drivers/clk/qcom/clk-hfpll.c                       | 244
>+++++++++++++
>>>  drivers/clk/qcom/clk-hfpll.h                       |  44 +++
>>>  drivers/clk/qcom/clk-krait.c                       | 126 +++++++
>>>  drivers/clk/qcom/clk-krait.h                       |  40 +++
>>>  drivers/clk/qcom/gcc-ipq806x.c                     |  82 +++++
>>>  drivers/clk/qcom/gcc-msm8960.c                     | 172 +++++++++
>>>  drivers/clk/qcom/hfpll.c                           |  96 +++++
>>>  drivers/clk/qcom/kpss-xcc.c                        |  87 +++++
>>>  drivers/clk/qcom/krait-cc.c                        | 397
>+++++++++++++++++++++
>>>  drivers/cpufreq/Kconfig.arm                        |   6 +-
>>>  drivers/cpufreq/Makefile                           |   2 +-
>>>  drivers/cpufreq/cpufreq-dt-platdev.c               |   5 +
>>>  drivers/cpufreq/qcom-cpufreq-kryo.c                | 232
>------------
>>>  drivers/cpufreq/qcom-cpufreq-nvmem.c               | 387
>++++++++++++++++++++
>>>  include/dt-bindings/clock/qcom,gcc-msm8960.h       |   2 +
>>>  26 files changed, 1941 insertions(+), 239 deletions(-)
>>>  create mode 100644
>Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
>>>  create mode 100644
>Documentation/devicetree/bindings/clock/qcom,hfpll.txt
>>>  create mode 100644
>Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
>>>  rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt =>
>qcom-nvmem-cpufreq.txt} (98%)
>>>  create mode 100644 arch/arm/common/krait-l2-accessors.c
>>>  create mode 100644 arch/arm/include/asm/krait-l2-accessors.h
>>>  create mode 100644 drivers/clk/qcom/clk-hfpll.c
>>>  create mode 100644 drivers/clk/qcom/clk-hfpll.h
>>>  create mode 100644 drivers/clk/qcom/clk-krait.c
>>>  create mode 100644 drivers/clk/qcom/clk-krait.h
>>>  create mode 100644 drivers/clk/qcom/hfpll.c
>>>  create mode 100644 drivers/clk/qcom/kpss-xcc.c
>>>  create mode 100644 drivers/clk/qcom/krait-cc.c
>>>  delete mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
>>>  create mode 100644 drivers/cpufreq/qcom-cpufreq-nvmem.c
>>>
>> 

-- 
Sent from my Android device with K-9 Mail. Please excuse my brevity.

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
  2018-09-07 14:28     ` Craig Tatlor
@ 2018-09-19 20:24       ` Craig
  2018-09-20 13:01         ` Sricharan R
  2018-09-20 13:03         ` Sricharan R
  0 siblings, 2 replies; 32+ messages in thread
From: Craig @ 2018-09-19 20:24 UTC (permalink / raw)
  To: Sricharan R, mark.rutland, robh, sudeep.holla, linux, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel

Yup, this patch seems to have fixed the higher frequencies from the quick test I did.

On 7 September 2018 15:28:53 BST, Craig Tatlor <ctatlor97@gmail.com> wrote:
>
>
>On 7 September 2018 10:57:34 BST, Sricharan R
><sricharan@codeaurora.org> wrote:
>>Hi Craig,
>>
>>
>>>> [v12]
>>>>   * Added my signed-off that was missing in some patches.
>>>>   * Added Bjorn's acked that i missed earlier.
>>>>
>>> 
>>>   Can you give this a try on your 8974 device and check if the
>>>   pvs version reporting, scaling for higher frequencies are fine ?
>>>   Sorry, i could not get hold of a 8974 device. So in-case if you
>>still
>>>   have the issues with higher frequencies, can you give a quick
>debug
>>>   and report. That would be of great help.
>>> 
>>   Ping on this ..
>
>Hi, didn't see your last message,
>
>Will have a try on mine in the weekend and report back.
>>
>>Regards,
>> Sricharan
>>
>>> Regards,
>>>  Sricharan
>>> 
>>> 
>>>> [v11]
>>>>   * Dropped patch 13 and 14 from v10 and
>>>>     merged the qcom-cpufreq-krait driver to the existing
>>qcom-cpufreq-kryo.c
>>>>   * Rebased on top of clk-next
>>>>   * Fixed a bug while populating the pvs version for krait.
>>>>
>>>> [v10]
>>>>   * Addressed Stephen's comments to add clocks bindings properties
>>>>     to the newly introduced nodes.
>>>>   * Added a change to include opp-supported-hw to qcom-cpufreq.c
>>>>   * Rebased on top of clk-next
>>>>   * Although there were minor changes to bindings and the driver
>>>>     retained the acked-by tags from Rob and Viresh respectively.   
>
>>>>
>>>> [v9]
>>>>   * Fixed a rebase issue in Makefile and added Tag from Robh.
>>>>
>>>> [v8]
>>>>   * Fixed a bug in path#14 pointed out by Viresh and also added
>>tags.
>>>>     No change in any other patch.
>>>>
>>>> [v7]
>>>>   * Fixed comments from Viresh for cleaning up the error handling
>>>>     in qcom-cpufreq.c. Also changed the init function to lateinit
>>>>     call. This is required because nvmem which gets initialised
>with
>>>>     module_init needs to go first.
>>>>   * Fixed Rob's comments for bindings documentation
>>>>   * Fixed kbuild build issue in clk-lpc32xx.c
>>>>   * Rebased on top of clk-next
>>>>
>>>> [v6]
>>>>   * Adrressed comments from Viresh for patch #14 in v5 [5]
>>>>   * Introduced a new binding operating-points-v2-krait-cpu
>>>>     as per discussion with Rob
>>>>   * Added Review tags
>>>>
>>>> [v5]
>>>>   * Addressed comments from Rob for bindings
>>>>   * Addressed comments from Viresh to use dev_pm_opp_set_prop_name,
>>accordingly
>>>>     dropped patch #12 and corrected patch #11 from previous patch
>>set in [4]
>>>>   * Converted to use #spdx tags for newly introduced files
>>>>
>>>> Mostly a resend of the v3 posted by Stephen quite some time back
>[1]
>>>> except for few changes.
>>>>   Based on reading some feedback from list,
>>>>   * Dropped the patch "clk: Add safe switch hook" from v3 [2].
>>>>     Now this is taken care by patch#10 in this series only for
>>Krait.
>>>>   * Dropped the path "clk: Avoid sending high rates to downstream
>>>> 		      clocks during set_rate" from v3 [3].
>>>>   * Rebased on top of clk-next.
>>>>   * Dropped the DT update from the series. Will send separately
>>>>   * Now with cpufreq-dt+opp supporting voltage scaling, registering
>>the
>>>>     krait cpu supplies in DT should be sufficient. But one issue
>is,
>>>>     the qcom-cpufreq drivers reads the efuse and based on that
>>registers
>>>>     the opp data and then registers the cpufreq-dt device. So when
>>>>     cpufreq-dt driver probes and registers the regulator to the OPP
>>framework,
>>>>     it expects that the opp data for the device should not be
>>registered before
>>>>     the regulator. Will send a RFC patch removing that check, to
>>find out the
>>>>     right way of doing it.
>>>>
>>>> These patches provide cpufreq scaling on devices with Krait CPUs.
>>>> In Krait CPU designs there's one PLL and two muxes per CPU,
>allowing
>>>> us to switch CPU frequencies independently.
>>>>
>>>> 				 secondary
>>>> 	 +-----+                    +
>>>> 	 | QSB |-------+------------|\
>>>> 	 +-----+       |            | |-+
>>>> 		       |    +-------|/  |
>>>> 		       |    |       +   |
>>>> 	 +-----+       |    |           |
>>>> 	 | PLL |----+-------+           |   primary
>>>> 	 +-----+    |  |                |     +
>>>> 		    |  |                +-----|\       +------+
>>>> 	 +-------+  |  |                      | \      |      |
>>>> 	 | HFPLL |----------+-----------------|  |-----| CPU0 |
>>>> 	 +-------+  |  |    |                 |  |     |      |
>>>> 		    |  |    | +-----+         | /      +------+
>>>> 		    |  |    +-| / 2 |---------|/
>>>> 		    |  |      +-----+         +
>>>> 		    |  |         secondary
>>>> 		    |  |            +
>>>> 		    |  +------------|\
>>>> 		    |               | |-+
>>>> 		    +---------------|/  |   primary
>>>> 				    +   |     +
>>>> 					+-----|\       +------+
>>>> 	 +-------+                            | \      |      |
>>>> 	 | HFPLL |----------------------------|  |-----| CPU1 |
>>>> 	 +-------+          |                 |  |     |      |
>>>> 			    | +-----+         | /      +------+
>>>> 			    +-| / 2 |---------|/
>>>> 			      +-----+         +
>>>>
>>>> To support this in the common clock framework we model the muxes,
>>>> dividers, and PLLs as different clocks. CPUfreq only interacts
>>>> with the primary mux (farthest right in the diagram). When CPUfreq
>>>> sets a rate, the mux code finds the best parent that can provide
>the
>>rate.
>>>> Due to the design, QSB and the top PLL are always a fixed rate and
>>thus
>>>> only support one frequency each. These sources provide the lowest
>>>> frequencies for the CPUs. The HFPLLs are where we can make the CPU
>>go
>>>> faster (GHz range). Sometimes we need to run the HFPLL twice as
>>>> fast and divide it by two to get a particular frequency.
>>>>
>>>> When switching rates we can't leave the CPU clocked by the HFPLL
>>because
>>>> we need to turn off the output of the PLL when changing its
>>frequency.
>>>> This means we have to switch over to the secondary mux and use one
>>of the
>>>> fixed sources. This is why we need something like the safe parent
>>patch.
>>>>
>>>> [1]
>>http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332607.html
>>>> [2]
>>http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332615.html
>>>> [3]
>>http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
>>>> [4] https://lwn.net/Articles/740994/ 
>>>> [5] https://lkml.org/lkml/2017/12/19/537
>>>>
>>>>
>>>> Sricharan R (3):
>>>>   clk: qcom: Add safe switch hook for krait mux clocks
>>>>   cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem
>>>>     based qcom socs
>>>>   cpufreq: qcom: Add support for krait based socs
>>>>
>>>> Stephen Boyd (11):
>>>>   ARM: Add Krait L2 register accessor functions
>>>>   clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
>>>>   clk: qcom: Add HFPLL driver
>>>>   dt-bindings: clock: Document qcom,hfpll
>>>>   clk: qcom: Add MSM8960/APQ8064's HFPLLs
>>>>   clk: qcom: Add IPQ806X's HFPLLs
>>>>   clk: qcom: Add support for Krait clocks
>>>>   clk: qcom: Add KPSS ACC/GCC driver
>>>>   dt-bindings: arm: Document qcom,kpss-gcc
>>>>   clk: qcom: Add Krait clock controller driver
>>>>   dt-bindings: clock: Document qcom,krait-cc
>>>>
>>>>  .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt  |  19 +
>>>>  .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt  |  44 +++
>>>>  .../devicetree/bindings/clock/qcom,hfpll.txt       |  60 ++++
>>>>  .../devicetree/bindings/clock/qcom,krait-cc.txt    |  34 ++
>>>>  .../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt}   |   7 +-
>>>>  arch/arm/common/Kconfig                            |   3 +
>>>>  arch/arm/common/Makefile                           |   1 +
>>>>  arch/arm/common/krait-l2-accessors.c               |  48 +++
>>>>  arch/arm/include/asm/krait-l2-accessors.h          |   9 +
>>>>  drivers/clk/qcom/Kconfig                           |  28 ++
>>>>  drivers/clk/qcom/Makefile                          |   5 +
>>>>  drivers/clk/qcom/clk-hfpll.c                       | 244
>>+++++++++++++
>>>>  drivers/clk/qcom/clk-hfpll.h                       |  44 +++
>>>>  drivers/clk/qcom/clk-krait.c                       | 126 +++++++
>>>>  drivers/clk/qcom/clk-krait.h                       |  40 +++
>>>>  drivers/clk/qcom/gcc-ipq806x.c                     |  82 +++++
>>>>  drivers/clk/qcom/gcc-msm8960.c                     | 172 +++++++++
>>>>  drivers/clk/qcom/hfpll.c                           |  96 +++++
>>>>  drivers/clk/qcom/kpss-xcc.c                        |  87 +++++
>>>>  drivers/clk/qcom/krait-cc.c                        | 397
>>+++++++++++++++++++++
>>>>  drivers/cpufreq/Kconfig.arm                        |   6 +-
>>>>  drivers/cpufreq/Makefile                           |   2 +-
>>>>  drivers/cpufreq/cpufreq-dt-platdev.c               |   5 +
>>>>  drivers/cpufreq/qcom-cpufreq-kryo.c                | 232
>>------------
>>>>  drivers/cpufreq/qcom-cpufreq-nvmem.c               | 387
>>++++++++++++++++++++
>>>>  include/dt-bindings/clock/qcom,gcc-msm8960.h       |   2 +
>>>>  26 files changed, 1941 insertions(+), 239 deletions(-)
>>>>  create mode 100644
>>Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
>>>>  create mode 100644
>>Documentation/devicetree/bindings/clock/qcom,hfpll.txt
>>>>  create mode 100644
>>Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
>>>>  rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt =>
>>qcom-nvmem-cpufreq.txt} (98%)
>>>>  create mode 100644 arch/arm/common/krait-l2-accessors.c
>>>>  create mode 100644 arch/arm/include/asm/krait-l2-accessors.h
>>>>  create mode 100644 drivers/clk/qcom/clk-hfpll.c
>>>>  create mode 100644 drivers/clk/qcom/clk-hfpll.h
>>>>  create mode 100644 drivers/clk/qcom/clk-krait.c
>>>>  create mode 100644 drivers/clk/qcom/clk-krait.h
>>>>  create mode 100644 drivers/clk/qcom/hfpll.c
>>>>  create mode 100644 drivers/clk/qcom/kpss-xcc.c
>>>>  create mode 100644 drivers/clk/qcom/krait-cc.c
>>>>  delete mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
>>>>  create mode 100644 drivers/cpufreq/qcom-cpufreq-nvmem.c
>>>>
>>> 

-- 
Sent from my Android device with K-9 Mail. Please excuse my brevity.

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
  2018-09-19 20:24       ` Craig
@ 2018-09-20 13:01         ` Sricharan R
  2018-09-20 14:27           ` Craig
  2018-09-20 13:03         ` Sricharan R
  1 sibling, 1 reply; 32+ messages in thread
From: Sricharan R @ 2018-09-20 13:01 UTC (permalink / raw)
  To: Craig, mark.rutland, robh, sudeep.holla, linux, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel



On 9/20/2018 1:54 AM, Craig wrote:
> Yup, this patch seems to have fixed the higher frequencies from the quick test I did.
> 
  Thanks !!. Can i take that as Craig Tatlor <ctatlor97@gmail.com> ?

Regards,
 Sricharan

       tested-by: 
> On 7 September 2018 15:28:53 BST, Craig Tatlor <ctatlor97@gmail.com> wrote:
>>
>>
>> On 7 September 2018 10:57:34 BST, Sricharan R
>> <sricharan@codeaurora.org> wrote:
>>> Hi Craig,
>>>
>>>
>>>>> [v12]
>>>>>   * Added my signed-off that was missing in some patches.
>>>>>   * Added Bjorn's acked that i missed earlier.
>>>>>
>>>>
>>>>   Can you give this a try on your 8974 device and check if the
>>>>   pvs version reporting, scaling for higher frequencies are fine ?
>>>>   Sorry, i could not get hold of a 8974 device. So in-case if you
>>> still
>>>>   have the issues with higher frequencies, can you give a quick
>> debug
>>>>   and report. That would be of great help.
>>>>
>>>   Ping on this ..
>>
>> Hi, didn't see your last message,
>>
>> Will have a try on mine in the weekend and report back.
>>>
>>> Regards,
>>> Sricharan
>>>
>>>> Regards,
>>>>  Sricharan
>>>>
>>>>
>>>>> [v11]
>>>>>   * Dropped patch 13 and 14 from v10 and
>>>>>     merged the qcom-cpufreq-krait driver to the existing
>>> qcom-cpufreq-kryo.c
>>>>>   * Rebased on top of clk-next
>>>>>   * Fixed a bug while populating the pvs version for krait.
>>>>>
>>>>> [v10]
>>>>>   * Addressed Stephen's comments to add clocks bindings properties
>>>>>     to the newly introduced nodes.
>>>>>   * Added a change to include opp-supported-hw to qcom-cpufreq.c
>>>>>   * Rebased on top of clk-next
>>>>>   * Although there were minor changes to bindings and the driver
>>>>>     retained the acked-by tags from Rob and Viresh respectively.   
>>
>>>>>
>>>>> [v9]
>>>>>   * Fixed a rebase issue in Makefile and added Tag from Robh.
>>>>>
>>>>> [v8]
>>>>>   * Fixed a bug in path#14 pointed out by Viresh and also added
>>> tags.
>>>>>     No change in any other patch.
>>>>>
>>>>> [v7]
>>>>>   * Fixed comments from Viresh for cleaning up the error handling
>>>>>     in qcom-cpufreq.c. Also changed the init function to lateinit
>>>>>     call. This is required because nvmem which gets initialised
>> with
>>>>>     module_init needs to go first.
>>>>>   * Fixed Rob's comments for bindings documentation
>>>>>   * Fixed kbuild build issue in clk-lpc32xx.c
>>>>>   * Rebased on top of clk-next
>>>>>
>>>>> [v6]
>>>>>   * Adrressed comments from Viresh for patch #14 in v5 [5]
>>>>>   * Introduced a new binding operating-points-v2-krait-cpu
>>>>>     as per discussion with Rob
>>>>>   * Added Review tags
>>>>>
>>>>> [v5]
>>>>>   * Addressed comments from Rob for bindings
>>>>>   * Addressed comments from Viresh to use dev_pm_opp_set_prop_name,
>>> accordingly
>>>>>     dropped patch #12 and corrected patch #11 from previous patch
>>> set in [4]
>>>>>   * Converted to use #spdx tags for newly introduced files
>>>>>
>>>>> Mostly a resend of the v3 posted by Stephen quite some time back
>> [1]
>>>>> except for few changes.
>>>>>   Based on reading some feedback from list,
>>>>>   * Dropped the patch "clk: Add safe switch hook" from v3 [2].
>>>>>     Now this is taken care by patch#10 in this series only for
>>> Krait.
>>>>>   * Dropped the path "clk: Avoid sending high rates to downstream
>>>>> 		      clocks during set_rate" from v3 [3].
>>>>>   * Rebased on top of clk-next.
>>>>>   * Dropped the DT update from the series. Will send separately
>>>>>   * Now with cpufreq-dt+opp supporting voltage scaling, registering
>>> the
>>>>>     krait cpu supplies in DT should be sufficient. But one issue
>> is,
>>>>>     the qcom-cpufreq drivers reads the efuse and based on that
>>> registers
>>>>>     the opp data and then registers the cpufreq-dt device. So when
>>>>>     cpufreq-dt driver probes and registers the regulator to the OPP
>>> framework,
>>>>>     it expects that the opp data for the device should not be
>>> registered before
>>>>>     the regulator. Will send a RFC patch removing that check, to
>>> find out the
>>>>>     right way of doing it.
>>>>>
>>>>> These patches provide cpufreq scaling on devices with Krait CPUs.
>>>>> In Krait CPU designs there's one PLL and two muxes per CPU,
>> allowing
>>>>> us to switch CPU frequencies independently.
>>>>>
>>>>> 				 secondary
>>>>> 	 +-----+                    +
>>>>> 	 | QSB |-------+------------|\
>>>>> 	 +-----+       |            | |-+
>>>>> 		       |    +-------|/  |
>>>>> 		       |    |       +   |
>>>>> 	 +-----+       |    |           |
>>>>> 	 | PLL |----+-------+           |   primary
>>>>> 	 +-----+    |  |                |     +
>>>>> 		    |  |                +-----|\       +------+
>>>>> 	 +-------+  |  |                      | \      |      |
>>>>> 	 | HFPLL |----------+-----------------|  |-----| CPU0 |
>>>>> 	 +-------+  |  |    |                 |  |     |      |
>>>>> 		    |  |    | +-----+         | /      +------+
>>>>> 		    |  |    +-| / 2 |---------|/
>>>>> 		    |  |      +-----+         +
>>>>> 		    |  |         secondary
>>>>> 		    |  |            +
>>>>> 		    |  +------------|\
>>>>> 		    |               | |-+
>>>>> 		    +---------------|/  |   primary
>>>>> 				    +   |     +
>>>>> 					+-----|\       +------+
>>>>> 	 +-------+                            | \      |      |
>>>>> 	 | HFPLL |----------------------------|  |-----| CPU1 |
>>>>> 	 +-------+          |                 |  |     |      |
>>>>> 			    | +-----+         | /      +------+
>>>>> 			    +-| / 2 |---------|/
>>>>> 			      +-----+         +
>>>>>
>>>>> To support this in the common clock framework we model the muxes,
>>>>> dividers, and PLLs as different clocks. CPUfreq only interacts
>>>>> with the primary mux (farthest right in the diagram). When CPUfreq
>>>>> sets a rate, the mux code finds the best parent that can provide
>> the
>>> rate.
>>>>> Due to the design, QSB and the top PLL are always a fixed rate and
>>> thus
>>>>> only support one frequency each. These sources provide the lowest
>>>>> frequencies for the CPUs. The HFPLLs are where we can make the CPU
>>> go
>>>>> faster (GHz range). Sometimes we need to run the HFPLL twice as
>>>>> fast and divide it by two to get a particular frequency.
>>>>>
>>>>> When switching rates we can't leave the CPU clocked by the HFPLL
>>> because
>>>>> we need to turn off the output of the PLL when changing its
>>> frequency.
>>>>> This means we have to switch over to the secondary mux and use one
>>> of the
>>>>> fixed sources. This is why we need something like the safe parent
>>> patch.
>>>>>
>>>>> [1]
>>> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332607.html
>>>>> [2]
>>> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332615.html
>>>>> [3]
>>> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
>>>>> [4] https://lwn.net/Articles/740994/ 
>>>>> [5] https://lkml.org/lkml/2017/12/19/537
>>>>>
>>>>>
>>>>> Sricharan R (3):
>>>>>   clk: qcom: Add safe switch hook for krait mux clocks
>>>>>   cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem
>>>>>     based qcom socs
>>>>>   cpufreq: qcom: Add support for krait based socs
>>>>>
>>>>> Stephen Boyd (11):
>>>>>   ARM: Add Krait L2 register accessor functions
>>>>>   clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
>>>>>   clk: qcom: Add HFPLL driver
>>>>>   dt-bindings: clock: Document qcom,hfpll
>>>>>   clk: qcom: Add MSM8960/APQ8064's HFPLLs
>>>>>   clk: qcom: Add IPQ806X's HFPLLs
>>>>>   clk: qcom: Add support for Krait clocks
>>>>>   clk: qcom: Add KPSS ACC/GCC driver
>>>>>   dt-bindings: arm: Document qcom,kpss-gcc
>>>>>   clk: qcom: Add Krait clock controller driver
>>>>>   dt-bindings: clock: Document qcom,krait-cc
>>>>>
>>>>>  .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt  |  19 +
>>>>>  .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt  |  44 +++
>>>>>  .../devicetree/bindings/clock/qcom,hfpll.txt       |  60 ++++
>>>>>  .../devicetree/bindings/clock/qcom,krait-cc.txt    |  34 ++
>>>>>  .../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt}   |   7 +-
>>>>>  arch/arm/common/Kconfig                            |   3 +
>>>>>  arch/arm/common/Makefile                           |   1 +
>>>>>  arch/arm/common/krait-l2-accessors.c               |  48 +++
>>>>>  arch/arm/include/asm/krait-l2-accessors.h          |   9 +
>>>>>  drivers/clk/qcom/Kconfig                           |  28 ++
>>>>>  drivers/clk/qcom/Makefile                          |   5 +
>>>>>  drivers/clk/qcom/clk-hfpll.c                       | 244
>>> +++++++++++++
>>>>>  drivers/clk/qcom/clk-hfpll.h                       |  44 +++
>>>>>  drivers/clk/qcom/clk-krait.c                       | 126 +++++++
>>>>>  drivers/clk/qcom/clk-krait.h                       |  40 +++
>>>>>  drivers/clk/qcom/gcc-ipq806x.c                     |  82 +++++
>>>>>  drivers/clk/qcom/gcc-msm8960.c                     | 172 +++++++++
>>>>>  drivers/clk/qcom/hfpll.c                           |  96 +++++
>>>>>  drivers/clk/qcom/kpss-xcc.c                        |  87 +++++
>>>>>  drivers/clk/qcom/krait-cc.c                        | 397
>>> +++++++++++++++++++++
>>>>>  drivers/cpufreq/Kconfig.arm                        |   6 +-
>>>>>  drivers/cpufreq/Makefile                           |   2 +-
>>>>>  drivers/cpufreq/cpufreq-dt-platdev.c               |   5 +
>>>>>  drivers/cpufreq/qcom-cpufreq-kryo.c                | 232
>>> ------------
>>>>>  drivers/cpufreq/qcom-cpufreq-nvmem.c               | 387
>>> ++++++++++++++++++++
>>>>>  include/dt-bindings/clock/qcom,gcc-msm8960.h       |   2 +
>>>>>  26 files changed, 1941 insertions(+), 239 deletions(-)
>>>>>  create mode 100644
>>> Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
>>>>>  create mode 100644
>>> Documentation/devicetree/bindings/clock/qcom,hfpll.txt
>>>>>  create mode 100644
>>> Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
>>>>>  rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt =>
>>> qcom-nvmem-cpufreq.txt} (98%)
>>>>>  create mode 100644 arch/arm/common/krait-l2-accessors.c
>>>>>  create mode 100644 arch/arm/include/asm/krait-l2-accessors.h
>>>>>  create mode 100644 drivers/clk/qcom/clk-hfpll.c
>>>>>  create mode 100644 drivers/clk/qcom/clk-hfpll.h
>>>>>  create mode 100644 drivers/clk/qcom/clk-krait.c
>>>>>  create mode 100644 drivers/clk/qcom/clk-krait.h
>>>>>  create mode 100644 drivers/clk/qcom/hfpll.c
>>>>>  create mode 100644 drivers/clk/qcom/kpss-xcc.c
>>>>>  create mode 100644 drivers/clk/qcom/krait-cc.c
>>>>>  delete mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
>>>>>  create mode 100644 drivers/cpufreq/qcom-cpufreq-nvmem.c
>>>>>
>>>>
> 

-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
  2018-09-19 20:24       ` Craig
  2018-09-20 13:01         ` Sricharan R
@ 2018-09-20 13:03         ` Sricharan R
  2018-10-17 15:44           ` Stephen Boyd
  1 sibling, 1 reply; 32+ messages in thread
From: Sricharan R @ 2018-09-20 13:03 UTC (permalink / raw)
  To: Craig, mark.rutland, robh, sudeep.holla, linux, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel



On 9/20/2018 1:54 AM, Craig wrote:
> Yup, this patch seems to have fixed the higher frequencies from the quick test I did.
>
      Thanks !!. Can i take that as 
          Tested-by: Craig Tatlor <ctatlor97@gmail.com>  ?

Regards,
 Sricharan
 
> On 7 September 2018 15:28:53 BST, Craig Tatlor <ctatlor97@gmail.com> wrote:
>>
>>
>> On 7 September 2018 10:57:34 BST, Sricharan R
>> <sricharan@codeaurora.org> wrote:
>>> Hi Craig,
>>>
>>>
>>>>> [v12]
>>>>>   * Added my signed-off that was missing in some patches.
>>>>>   * Added Bjorn's acked that i missed earlier.
>>>>>
>>>>
>>>>   Can you give this a try on your 8974 device and check if the
>>>>   pvs version reporting, scaling for higher frequencies are fine ?
>>>>   Sorry, i could not get hold of a 8974 device. So in-case if you
>>> still
>>>>   have the issues with higher frequencies, can you give a quick
>> debug
>>>>   and report. That would be of great help.
>>>>
>>>   Ping on this ..
>>
>> Hi, didn't see your last message,
>>
>> Will have a try on mine in the weekend and report back.
>>>
>>> Regards,
>>> Sricharan
>>>
>>>> Regards,
>>>>  Sricharan
>>>>
>>>>
>>>>> [v11]
>>>>>   * Dropped patch 13 and 14 from v10 and
>>>>>     merged the qcom-cpufreq-krait driver to the existing
>>> qcom-cpufreq-kryo.c
>>>>>   * Rebased on top of clk-next
>>>>>   * Fixed a bug while populating the pvs version for krait.
>>>>>
>>>>> [v10]
>>>>>   * Addressed Stephen's comments to add clocks bindings properties
>>>>>     to the newly introduced nodes.
>>>>>   * Added a change to include opp-supported-hw to qcom-cpufreq.c
>>>>>   * Rebased on top of clk-next
>>>>>   * Although there were minor changes to bindings and the driver
>>>>>     retained the acked-by tags from Rob and Viresh respectively.   
>>
>>>>>
>>>>> [v9]
>>>>>   * Fixed a rebase issue in Makefile and added Tag from Robh.
>>>>>
>>>>> [v8]
>>>>>   * Fixed a bug in path#14 pointed out by Viresh and also added
>>> tags.
>>>>>     No change in any other patch.
>>>>>
>>>>> [v7]
>>>>>   * Fixed comments from Viresh for cleaning up the error handling
>>>>>     in qcom-cpufreq.c. Also changed the init function to lateinit
>>>>>     call. This is required because nvmem which gets initialised
>> with
>>>>>     module_init needs to go first.
>>>>>   * Fixed Rob's comments for bindings documentation
>>>>>   * Fixed kbuild build issue in clk-lpc32xx.c
>>>>>   * Rebased on top of clk-next
>>>>>
>>>>> [v6]
>>>>>   * Adrressed comments from Viresh for patch #14 in v5 [5]
>>>>>   * Introduced a new binding operating-points-v2-krait-cpu
>>>>>     as per discussion with Rob
>>>>>   * Added Review tags
>>>>>
>>>>> [v5]
>>>>>   * Addressed comments from Rob for bindings
>>>>>   * Addressed comments from Viresh to use dev_pm_opp_set_prop_name,
>>> accordingly
>>>>>     dropped patch #12 and corrected patch #11 from previous patch
>>> set in [4]
>>>>>   * Converted to use #spdx tags for newly introduced files
>>>>>
>>>>> Mostly a resend of the v3 posted by Stephen quite some time back
>> [1]
>>>>> except for few changes.
>>>>>   Based on reading some feedback from list,
>>>>>   * Dropped the patch "clk: Add safe switch hook" from v3 [2].
>>>>>     Now this is taken care by patch#10 in this series only for
>>> Krait.
>>>>>   * Dropped the path "clk: Avoid sending high rates to downstream
>>>>> 		      clocks during set_rate" from v3 [3].
>>>>>   * Rebased on top of clk-next.
>>>>>   * Dropped the DT update from the series. Will send separately
>>>>>   * Now with cpufreq-dt+opp supporting voltage scaling, registering
>>> the
>>>>>     krait cpu supplies in DT should be sufficient. But one issue
>> is,
>>>>>     the qcom-cpufreq drivers reads the efuse and based on that
>>> registers
>>>>>     the opp data and then registers the cpufreq-dt device. So when
>>>>>     cpufreq-dt driver probes and registers the regulator to the OPP
>>> framework,
>>>>>     it expects that the opp data for the device should not be
>>> registered before
>>>>>     the regulator. Will send a RFC patch removing that check, to
>>> find out the
>>>>>     right way of doing it.
>>>>>
>>>>> These patches provide cpufreq scaling on devices with Krait CPUs.
>>>>> In Krait CPU designs there's one PLL and two muxes per CPU,
>> allowing
>>>>> us to switch CPU frequencies independently.
>>>>>
>>>>> 				 secondary
>>>>> 	 +-----+                    +
>>>>> 	 | QSB |-------+------------|\
>>>>> 	 +-----+       |            | |-+
>>>>> 		       |    +-------|/  |
>>>>> 		       |    |       +   |
>>>>> 	 +-----+       |    |           |
>>>>> 	 | PLL |----+-------+           |   primary
>>>>> 	 +-----+    |  |                |     +
>>>>> 		    |  |                +-----|\       +------+
>>>>> 	 +-------+  |  |                      | \      |      |
>>>>> 	 | HFPLL |----------+-----------------|  |-----| CPU0 |
>>>>> 	 +-------+  |  |    |                 |  |     |      |
>>>>> 		    |  |    | +-----+         | /      +------+
>>>>> 		    |  |    +-| / 2 |---------|/
>>>>> 		    |  |      +-----+         +
>>>>> 		    |  |         secondary
>>>>> 		    |  |            +
>>>>> 		    |  +------------|\
>>>>> 		    |               | |-+
>>>>> 		    +---------------|/  |   primary
>>>>> 				    +   |     +
>>>>> 					+-----|\       +------+
>>>>> 	 +-------+                            | \      |      |
>>>>> 	 | HFPLL |----------------------------|  |-----| CPU1 |
>>>>> 	 +-------+          |                 |  |     |      |
>>>>> 			    | +-----+         | /      +------+
>>>>> 			    +-| / 2 |---------|/
>>>>> 			      +-----+         +
>>>>>
>>>>> To support this in the common clock framework we model the muxes,
>>>>> dividers, and PLLs as different clocks. CPUfreq only interacts
>>>>> with the primary mux (farthest right in the diagram). When CPUfreq
>>>>> sets a rate, the mux code finds the best parent that can provide
>> the
>>> rate.
>>>>> Due to the design, QSB and the top PLL are always a fixed rate and
>>> thus
>>>>> only support one frequency each. These sources provide the lowest
>>>>> frequencies for the CPUs. The HFPLLs are where we can make the CPU
>>> go
>>>>> faster (GHz range). Sometimes we need to run the HFPLL twice as
>>>>> fast and divide it by two to get a particular frequency.
>>>>>
>>>>> When switching rates we can't leave the CPU clocked by the HFPLL
>>> because
>>>>> we need to turn off the output of the PLL when changing its
>>> frequency.
>>>>> This means we have to switch over to the secondary mux and use one
>>> of the
>>>>> fixed sources. This is why we need something like the safe parent
>>> patch.
>>>>>
>>>>> [1]
>>> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332607.html
>>>>> [2]
>>> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332615.html
>>>>> [3]
>>> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
>>>>> [4] https://lwn.net/Articles/740994/ 
>>>>> [5] https://lkml.org/lkml/2017/12/19/537
>>>>>
>>>>>
>>>>> Sricharan R (3):
>>>>>   clk: qcom: Add safe switch hook for krait mux clocks
>>>>>   cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem
>>>>>     based qcom socs
>>>>>   cpufreq: qcom: Add support for krait based socs
>>>>>
>>>>> Stephen Boyd (11):
>>>>>   ARM: Add Krait L2 register accessor functions
>>>>>   clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
>>>>>   clk: qcom: Add HFPLL driver
>>>>>   dt-bindings: clock: Document qcom,hfpll
>>>>>   clk: qcom: Add MSM8960/APQ8064's HFPLLs
>>>>>   clk: qcom: Add IPQ806X's HFPLLs
>>>>>   clk: qcom: Add support for Krait clocks
>>>>>   clk: qcom: Add KPSS ACC/GCC driver
>>>>>   dt-bindings: arm: Document qcom,kpss-gcc
>>>>>   clk: qcom: Add Krait clock controller driver
>>>>>   dt-bindings: clock: Document qcom,krait-cc
>>>>>
>>>>>  .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt  |  19 +
>>>>>  .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt  |  44 +++
>>>>>  .../devicetree/bindings/clock/qcom,hfpll.txt       |  60 ++++
>>>>>  .../devicetree/bindings/clock/qcom,krait-cc.txt    |  34 ++
>>>>>  .../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt}   |   7 +-
>>>>>  arch/arm/common/Kconfig                            |   3 +
>>>>>  arch/arm/common/Makefile                           |   1 +
>>>>>  arch/arm/common/krait-l2-accessors.c               |  48 +++
>>>>>  arch/arm/include/asm/krait-l2-accessors.h          |   9 +
>>>>>  drivers/clk/qcom/Kconfig                           |  28 ++
>>>>>  drivers/clk/qcom/Makefile                          |   5 +
>>>>>  drivers/clk/qcom/clk-hfpll.c                       | 244
>>> +++++++++++++
>>>>>  drivers/clk/qcom/clk-hfpll.h                       |  44 +++
>>>>>  drivers/clk/qcom/clk-krait.c                       | 126 +++++++
>>>>>  drivers/clk/qcom/clk-krait.h                       |  40 +++
>>>>>  drivers/clk/qcom/gcc-ipq806x.c                     |  82 +++++
>>>>>  drivers/clk/qcom/gcc-msm8960.c                     | 172 +++++++++
>>>>>  drivers/clk/qcom/hfpll.c                           |  96 +++++
>>>>>  drivers/clk/qcom/kpss-xcc.c                        |  87 +++++
>>>>>  drivers/clk/qcom/krait-cc.c                        | 397
>>> +++++++++++++++++++++
>>>>>  drivers/cpufreq/Kconfig.arm                        |   6 +-
>>>>>  drivers/cpufreq/Makefile                           |   2 +-
>>>>>  drivers/cpufreq/cpufreq-dt-platdev.c               |   5 +
>>>>>  drivers/cpufreq/qcom-cpufreq-kryo.c                | 232
>>> ------------
>>>>>  drivers/cpufreq/qcom-cpufreq-nvmem.c               | 387
>>> ++++++++++++++++++++
>>>>>  include/dt-bindings/clock/qcom,gcc-msm8960.h       |   2 +
>>>>>  26 files changed, 1941 insertions(+), 239 deletions(-)
>>>>>  create mode 100644
>>> Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
>>>>>  create mode 100644
>>> Documentation/devicetree/bindings/clock/qcom,hfpll.txt
>>>>>  create mode 100644
>>> Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
>>>>>  rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt =>
>>> qcom-nvmem-cpufreq.txt} (98%)
>>>>>  create mode 100644 arch/arm/common/krait-l2-accessors.c
>>>>>  create mode 100644 arch/arm/include/asm/krait-l2-accessors.h
>>>>>  create mode 100644 drivers/clk/qcom/clk-hfpll.c
>>>>>  create mode 100644 drivers/clk/qcom/clk-hfpll.h
>>>>>  create mode 100644 drivers/clk/qcom/clk-krait.c
>>>>>  create mode 100644 drivers/clk/qcom/clk-krait.h
>>>>>  create mode 100644 drivers/clk/qcom/hfpll.c
>>>>>  create mode 100644 drivers/clk/qcom/kpss-xcc.c
>>>>>  create mode 100644 drivers/clk/qcom/krait-cc.c
>>>>>  delete mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
>>>>>  create mode 100644 drivers/cpufreq/qcom-cpufreq-nvmem.c
>>>>>
>>>>
> 

-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
  2018-09-20 13:01         ` Sricharan R
@ 2018-09-20 14:27           ` Craig
  0 siblings, 0 replies; 32+ messages in thread
From: Craig @ 2018-09-20 14:27 UTC (permalink / raw)
  To: Sricharan R, mark.rutland, robh, sudeep.holla, linux, rjw,
	viresh.kumar, mturquette, linux-pm, sboyd, linux,
	thierry.escande, linux-kernel, david.brown, devicetree,
	linux-arm-msm, andy.gross, linux-soc, linux-clk,
	linux-arm-kernel, niklas.cassel



On 20 September 2018 14:01:57 BST, Sricharan R <sricharan@codeaurora.org> wrote:
>
>
>On 9/20/2018 1:54 AM, Craig wrote:
>> Yup, this patch seems to have fixed the higher frequencies from the
>quick test I did.
>> 
>  Thanks !!. Can i take that as Craig Tatlor <ctatlor97@gmail.com> ?
Sure, no problem
>
>Regards,
> Sricharan
>
>       tested-by: 
>> On 7 September 2018 15:28:53 BST, Craig Tatlor <ctatlor97@gmail.com>
>wrote:
>>>
>>>
>>> On 7 September 2018 10:57:34 BST, Sricharan R
>>> <sricharan@codeaurora.org> wrote:
>>>> Hi Craig,
>>>>
>>>>
>>>>>> [v12]
>>>>>>   * Added my signed-off that was missing in some patches.
>>>>>>   * Added Bjorn's acked that i missed earlier.
>>>>>>
>>>>>
>>>>>   Can you give this a try on your 8974 device and check if the
>>>>>   pvs version reporting, scaling for higher frequencies are fine ?
>>>>>   Sorry, i could not get hold of a 8974 device. So in-case if you
>>>> still
>>>>>   have the issues with higher frequencies, can you give a quick
>>> debug
>>>>>   and report. That would be of great help.
>>>>>
>>>>   Ping on this ..
>>>
>>> Hi, didn't see your last message,
>>>
>>> Will have a try on mine in the weekend and report back.
>>>>
>>>> Regards,
>>>> Sricharan
>>>>
>>>>> Regards,
>>>>>  Sricharan
>>>>>
>>>>>
>>>>>> [v11]
>>>>>>   * Dropped patch 13 and 14 from v10 and
>>>>>>     merged the qcom-cpufreq-krait driver to the existing
>>>> qcom-cpufreq-kryo.c
>>>>>>   * Rebased on top of clk-next
>>>>>>   * Fixed a bug while populating the pvs version for krait.
>>>>>>
>>>>>> [v10]
>>>>>>   * Addressed Stephen's comments to add clocks bindings
>properties
>>>>>>     to the newly introduced nodes.
>>>>>>   * Added a change to include opp-supported-hw to qcom-cpufreq.c
>>>>>>   * Rebased on top of clk-next
>>>>>>   * Although there were minor changes to bindings and the driver
>>>>>>     retained the acked-by tags from Rob and Viresh respectively. 
> 
>>>
>>>>>>
>>>>>> [v9]
>>>>>>   * Fixed a rebase issue in Makefile and added Tag from Robh.
>>>>>>
>>>>>> [v8]
>>>>>>   * Fixed a bug in path#14 pointed out by Viresh and also added
>>>> tags.
>>>>>>     No change in any other patch.
>>>>>>
>>>>>> [v7]
>>>>>>   * Fixed comments from Viresh for cleaning up the error handling
>>>>>>     in qcom-cpufreq.c. Also changed the init function to lateinit
>>>>>>     call. This is required because nvmem which gets initialised
>>> with
>>>>>>     module_init needs to go first.
>>>>>>   * Fixed Rob's comments for bindings documentation
>>>>>>   * Fixed kbuild build issue in clk-lpc32xx.c
>>>>>>   * Rebased on top of clk-next
>>>>>>
>>>>>> [v6]
>>>>>>   * Adrressed comments from Viresh for patch #14 in v5 [5]
>>>>>>   * Introduced a new binding operating-points-v2-krait-cpu
>>>>>>     as per discussion with Rob
>>>>>>   * Added Review tags
>>>>>>
>>>>>> [v5]
>>>>>>   * Addressed comments from Rob for bindings
>>>>>>   * Addressed comments from Viresh to use
>dev_pm_opp_set_prop_name,
>>>> accordingly
>>>>>>     dropped patch #12 and corrected patch #11 from previous patch
>>>> set in [4]
>>>>>>   * Converted to use #spdx tags for newly introduced files
>>>>>>
>>>>>> Mostly a resend of the v3 posted by Stephen quite some time back
>>> [1]
>>>>>> except for few changes.
>>>>>>   Based on reading some feedback from list,
>>>>>>   * Dropped the patch "clk: Add safe switch hook" from v3 [2].
>>>>>>     Now this is taken care by patch#10 in this series only for
>>>> Krait.
>>>>>>   * Dropped the path "clk: Avoid sending high rates to downstream
>>>>>> 		      clocks during set_rate" from v3 [3].
>>>>>>   * Rebased on top of clk-next.
>>>>>>   * Dropped the DT update from the series. Will send separately
>>>>>>   * Now with cpufreq-dt+opp supporting voltage scaling,
>registering
>>>> the
>>>>>>     krait cpu supplies in DT should be sufficient. But one issue
>>> is,
>>>>>>     the qcom-cpufreq drivers reads the efuse and based on that
>>>> registers
>>>>>>     the opp data and then registers the cpufreq-dt device. So
>when
>>>>>>     cpufreq-dt driver probes and registers the regulator to the
>OPP
>>>> framework,
>>>>>>     it expects that the opp data for the device should not be
>>>> registered before
>>>>>>     the regulator. Will send a RFC patch removing that check, to
>>>> find out the
>>>>>>     right way of doing it.
>>>>>>
>>>>>> These patches provide cpufreq scaling on devices with Krait CPUs.
>>>>>> In Krait CPU designs there's one PLL and two muxes per CPU,
>>> allowing
>>>>>> us to switch CPU frequencies independently.
>>>>>>
>>>>>> 				 secondary
>>>>>> 	 +-----+                    +
>>>>>> 	 | QSB |-------+------------|\
>>>>>> 	 +-----+       |            | |-+
>>>>>> 		       |    +-------|/  |
>>>>>> 		       |    |       +   |
>>>>>> 	 +-----+       |    |           |
>>>>>> 	 | PLL |----+-------+           |   primary
>>>>>> 	 +-----+    |  |                |     +
>>>>>> 		    |  |                +-----|\       +------+
>>>>>> 	 +-------+  |  |                      | \      |      |
>>>>>> 	 | HFPLL |----------+-----------------|  |-----| CPU0 |
>>>>>> 	 +-------+  |  |    |                 |  |     |      |
>>>>>> 		    |  |    | +-----+         | /      +------+
>>>>>> 		    |  |    +-| / 2 |---------|/
>>>>>> 		    |  |      +-----+         +
>>>>>> 		    |  |         secondary
>>>>>> 		    |  |            +
>>>>>> 		    |  +------------|\
>>>>>> 		    |               | |-+
>>>>>> 		    +---------------|/  |   primary
>>>>>> 				    +   |     +
>>>>>> 					+-----|\       +------+
>>>>>> 	 +-------+                            | \      |      |
>>>>>> 	 | HFPLL |----------------------------|  |-----| CPU1 |
>>>>>> 	 +-------+          |                 |  |     |      |
>>>>>> 			    | +-----+         | /      +------+
>>>>>> 			    +-| / 2 |---------|/
>>>>>> 			      +-----+         +
>>>>>>
>>>>>> To support this in the common clock framework we model the muxes,
>>>>>> dividers, and PLLs as different clocks. CPUfreq only interacts
>>>>>> with the primary mux (farthest right in the diagram). When
>CPUfreq
>>>>>> sets a rate, the mux code finds the best parent that can provide
>>> the
>>>> rate.
>>>>>> Due to the design, QSB and the top PLL are always a fixed rate
>and
>>>> thus
>>>>>> only support one frequency each. These sources provide the lowest
>>>>>> frequencies for the CPUs. The HFPLLs are where we can make the
>CPU
>>>> go
>>>>>> faster (GHz range). Sometimes we need to run the HFPLL twice as
>>>>>> fast and divide it by two to get a particular frequency.
>>>>>>
>>>>>> When switching rates we can't leave the CPU clocked by the HFPLL
>>>> because
>>>>>> we need to turn off the output of the PLL when changing its
>>>> frequency.
>>>>>> This means we have to switch over to the secondary mux and use
>one
>>>> of the
>>>>>> fixed sources. This is why we need something like the safe parent
>>>> patch.
>>>>>>
>>>>>> [1]
>>>>
>http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332607.html
>>>>>> [2]
>>>>
>http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332615.html
>>>>>> [3]
>>>>
>http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
>>>>>> [4] https://lwn.net/Articles/740994/ 
>>>>>> [5] https://lkml.org/lkml/2017/12/19/537
>>>>>>
>>>>>>
>>>>>> Sricharan R (3):
>>>>>>   clk: qcom: Add safe switch hook for krait mux clocks
>>>>>>   cpufreq: qcom: Re-organise kryo cpufreq to use it for other
>nvmem
>>>>>>     based qcom socs
>>>>>>   cpufreq: qcom: Add support for krait based socs
>>>>>>
>>>>>> Stephen Boyd (11):
>>>>>>   ARM: Add Krait L2 register accessor functions
>>>>>>   clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
>>>>>>   clk: qcom: Add HFPLL driver
>>>>>>   dt-bindings: clock: Document qcom,hfpll
>>>>>>   clk: qcom: Add MSM8960/APQ8064's HFPLLs
>>>>>>   clk: qcom: Add IPQ806X's HFPLLs
>>>>>>   clk: qcom: Add support for Krait clocks
>>>>>>   clk: qcom: Add KPSS ACC/GCC driver
>>>>>>   dt-bindings: arm: Document qcom,kpss-gcc
>>>>>>   clk: qcom: Add Krait clock controller driver
>>>>>>   dt-bindings: clock: Document qcom,krait-cc
>>>>>>
>>>>>>  .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt  |  19 +
>>>>>>  .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt  |  44 +++
>>>>>>  .../devicetree/bindings/clock/qcom,hfpll.txt       |  60 ++++
>>>>>>  .../devicetree/bindings/clock/qcom,krait-cc.txt    |  34 ++
>>>>>>  .../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt}   |   7 +-
>>>>>>  arch/arm/common/Kconfig                            |   3 +
>>>>>>  arch/arm/common/Makefile                           |   1 +
>>>>>>  arch/arm/common/krait-l2-accessors.c               |  48 +++
>>>>>>  arch/arm/include/asm/krait-l2-accessors.h          |   9 +
>>>>>>  drivers/clk/qcom/Kconfig                           |  28 ++
>>>>>>  drivers/clk/qcom/Makefile                          |   5 +
>>>>>>  drivers/clk/qcom/clk-hfpll.c                       | 244
>>>> +++++++++++++
>>>>>>  drivers/clk/qcom/clk-hfpll.h                       |  44 +++
>>>>>>  drivers/clk/qcom/clk-krait.c                       | 126 +++++++
>>>>>>  drivers/clk/qcom/clk-krait.h                       |  40 +++
>>>>>>  drivers/clk/qcom/gcc-ipq806x.c                     |  82 +++++
>>>>>>  drivers/clk/qcom/gcc-msm8960.c                     | 172
>+++++++++
>>>>>>  drivers/clk/qcom/hfpll.c                           |  96 +++++
>>>>>>  drivers/clk/qcom/kpss-xcc.c                        |  87 +++++
>>>>>>  drivers/clk/qcom/krait-cc.c                        | 397
>>>> +++++++++++++++++++++
>>>>>>  drivers/cpufreq/Kconfig.arm                        |   6 +-
>>>>>>  drivers/cpufreq/Makefile                           |   2 +-
>>>>>>  drivers/cpufreq/cpufreq-dt-platdev.c               |   5 +
>>>>>>  drivers/cpufreq/qcom-cpufreq-kryo.c                | 232
>>>> ------------
>>>>>>  drivers/cpufreq/qcom-cpufreq-nvmem.c               | 387
>>>> ++++++++++++++++++++
>>>>>>  include/dt-bindings/clock/qcom,gcc-msm8960.h       |   2 +
>>>>>>  26 files changed, 1941 insertions(+), 239 deletions(-)
>>>>>>  create mode 100644
>>>> Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
>>>>>>  create mode 100644
>>>> Documentation/devicetree/bindings/clock/qcom,hfpll.txt
>>>>>>  create mode 100644
>>>> Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
>>>>>>  rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt
>=>
>>>> qcom-nvmem-cpufreq.txt} (98%)
>>>>>>  create mode 100644 arch/arm/common/krait-l2-accessors.c
>>>>>>  create mode 100644 arch/arm/include/asm/krait-l2-accessors.h
>>>>>>  create mode 100644 drivers/clk/qcom/clk-hfpll.c
>>>>>>  create mode 100644 drivers/clk/qcom/clk-hfpll.h
>>>>>>  create mode 100644 drivers/clk/qcom/clk-krait.c
>>>>>>  create mode 100644 drivers/clk/qcom/clk-krait.h
>>>>>>  create mode 100644 drivers/clk/qcom/hfpll.c
>>>>>>  create mode 100644 drivers/clk/qcom/kpss-xcc.c
>>>>>>  create mode 100644 drivers/clk/qcom/krait-cc.c
>>>>>>  delete mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
>>>>>>  create mode 100644 drivers/cpufreq/qcom-cpufreq-nvmem.c
>>>>>>
>>>>>
>> 

-- 
Please, Don't Panic

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
  2018-09-20 13:03         ` Sricharan R
@ 2018-10-17 15:44           ` Stephen Boyd
  2018-10-17 20:16             ` Stephen Boyd
  0 siblings, 1 reply; 32+ messages in thread
From: Stephen Boyd @ 2018-10-17 15:44 UTC (permalink / raw)
  To: Craig, Sricharan R, andy.gross, david.brown, devicetree,
	linux-arm-kernel, linux-arm-msm, linux-clk, linux-kernel,
	linux-pm, linux-soc, linux, linux, mark.rutland, mturquette,
	niklas.cassel, rjw, robh, sboyd, sudeep.holla, thierry.escande,
	viresh.kumar

Quoting Sricharan R (2018-09-20 06:03:31)
> 
> 
> On 9/20/2018 1:54 AM, Craig wrote:
> > Yup, this patch seems to have fixed the higher frequencies from the quick test I did.
> >
>       Thanks !!. Can i take that as 
>           Tested-by: Craig Tatlor <ctatlor97@gmail.com>  ?
> 

Is this patch series going to be resent?


^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
  2018-10-17 15:44           ` Stephen Boyd
@ 2018-10-17 20:16             ` Stephen Boyd
  2018-10-22  4:09               ` Sricharan R
  0 siblings, 1 reply; 32+ messages in thread
From: Stephen Boyd @ 2018-10-17 20:16 UTC (permalink / raw)
  To: Craig, Sricharan R, andy.gross, david.brown, devicetree,
	linux-arm-kernel, linux-arm-msm, linux-clk, linux-kernel,
	linux-pm, linux-soc, linux, linux, mark.rutland, mturquette,
	niklas.cassel, rjw, robh, sboyd, sudeep.holla, thierry.escande,
	viresh.kumar

Quoting Stephen Boyd (2018-10-17 08:44:12)
> Quoting Sricharan R (2018-09-20 06:03:31)
> > 
> > 
> > On 9/20/2018 1:54 AM, Craig wrote:
> > > Yup, this patch seems to have fixed the higher frequencies from the quick test I did.
> > >
> >       Thanks !!. Can i take that as 
> >           Tested-by: Craig Tatlor <ctatlor97@gmail.com>  ?
> > 
> 
> Is this patch series going to be resent?
> 

Nevermind. Looking at it I think I can apply all the clk ones and we're
good to go. If you can send a followup patch series to change the
registration and provider APIs to be clk_hw instead of clk based I would
appreciate it.


^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
  2018-10-17 20:16             ` Stephen Boyd
@ 2018-10-22  4:09               ` Sricharan R
  2018-10-22 15:30                 ` Niklas Cassel
  0 siblings, 1 reply; 32+ messages in thread
From: Sricharan R @ 2018-10-22  4:09 UTC (permalink / raw)
  To: Stephen Boyd, Craig, andy.gross, david.brown, devicetree,
	linux-arm-kernel, linux-arm-msm, linux-clk, linux-kernel,
	linux-pm, linux-soc, linux, linux, mark.rutland, mturquette,
	niklas.cassel, rjw, robh, sboyd, sudeep.holla, thierry.escande,
	viresh.kumar

Hi Stephen,

On 10/18/2018 1:46 AM, Stephen Boyd wrote:
> Quoting Stephen Boyd (2018-10-17 08:44:12)
>> Quoting Sricharan R (2018-09-20 06:03:31)
>>>
>>>
>>> On 9/20/2018 1:54 AM, Craig wrote:
>>>> Yup, this patch seems to have fixed the higher frequencies from the quick test I did.
>>>>
>>>       Thanks !!. Can i take that as 
>>>           Tested-by: Craig Tatlor <ctatlor97@gmail.com>  ?
>>>
>>
>> Is this patch series going to be resent?
>>
> 
> Nevermind. Looking at it I think I can apply all the clk ones and we're
> good to go. If you can send a followup patch series to change the
> registration and provider APIs to be clk_hw instead of clk based I would
> appreciate it.
> 

Sorry for the late response. Was away.
Only pending thing was separating out the binding documentation for the cpu-freq
driver and fixing the text in documentation.  That means, yes its fine to merge
the clk ones as you said. I will resend that. Also, will send a follow up series for clk_hw to
clk change as you mentioned separately.

Regards,
 Sricharan

-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
  2018-10-22  4:09               ` Sricharan R
@ 2018-10-22 15:30                 ` Niklas Cassel
  2018-10-24  4:11                   ` Sricharan R
  0 siblings, 1 reply; 32+ messages in thread
From: Niklas Cassel @ 2018-10-22 15:30 UTC (permalink / raw)
  To: Sricharan R
  Cc: Stephen Boyd, Craig, andy.gross, david.brown, devicetree,
	linux-arm-kernel, linux-arm-msm, linux-clk, linux-kernel,
	linux-pm, linux-soc, linux, linux, mark.rutland, mturquette, rjw,
	robh, sboyd, sudeep.holla, thierry.escande, viresh.kumar

On Mon, Oct 22, 2018 at 09:39:03AM +0530, Sricharan R wrote:
> Hi Stephen,
> 
> On 10/18/2018 1:46 AM, Stephen Boyd wrote:
> > Quoting Stephen Boyd (2018-10-17 08:44:12)
> >> Quoting Sricharan R (2018-09-20 06:03:31)
> >>>
> >>>
> >>> On 9/20/2018 1:54 AM, Craig wrote:
> >>>> Yup, this patch seems to have fixed the higher frequencies from the quick test I did.
> >>>>
> >>>       Thanks !!. Can i take that as 
> >>>           Tested-by: Craig Tatlor <ctatlor97@gmail.com>  ?
> >>>
> >>
> >> Is this patch series going to be resent?
> >>
> > 
> > Nevermind. Looking at it I think I can apply all the clk ones and we're
> > good to go. If you can send a followup patch series to change the
> > registration and provider APIs to be clk_hw instead of clk based I would
> > appreciate it.
> > 
> 
> Sorry for the late response. Was away.
> Only pending thing was separating out the binding documentation for the cpu-freq
> driver and fixing the text in documentation.  That means, yes its fine to merge
> the clk ones as you said. I will resend that. Also, will send a follow up series for clk_hw to
> clk change as you mentioned separately.

Hello Sricharan,

Great to see that the clk parts has been marged to clk-next!

Are you also planning on sending out a new version of the cpufreq driver
consolidation parts?

I'm planning on extending your consilidated cpufreq driver with support
for msm8916 (Cortex-A53), where I plan to read PVS/speedbin, in order to
set opp_supported_hw(), and also register with cpufreq (since Viresh/Ulf
suggested that we shouldn't register with cpufreq in the CPR power-domain
driver).


Kind regards,
Niklas

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [PATCH V12 00/14] Krait clocks + Krait CPUfreq
  2018-10-22 15:30                 ` Niklas Cassel
@ 2018-10-24  4:11                   ` Sricharan R
  0 siblings, 0 replies; 32+ messages in thread
From: Sricharan R @ 2018-10-24  4:11 UTC (permalink / raw)
  To: Niklas Cassel
  Cc: Stephen Boyd, Craig, andy.gross, david.brown, devicetree,
	linux-arm-kernel, linux-arm-msm, linux-clk, linux-kernel,
	linux-pm, linux-soc, linux, linux, mark.rutland, mturquette, rjw,
	robh, sboyd, sudeep.holla, thierry.escande, viresh.kumar

Hi Niklas,

On 10/22/2018 9:00 PM, Niklas Cassel wrote:
> On Mon, Oct 22, 2018 at 09:39:03AM +0530, Sricharan R wrote:
>> Hi Stephen,
>>
>> On 10/18/2018 1:46 AM, Stephen Boyd wrote:
>>> Quoting Stephen Boyd (2018-10-17 08:44:12)
>>>> Quoting Sricharan R (2018-09-20 06:03:31)
>>>>>
>>>>>
>>>>> On 9/20/2018 1:54 AM, Craig wrote:
>>>>>> Yup, this patch seems to have fixed the higher frequencies from the quick test I did.
>>>>>>
>>>>>       Thanks !!. Can i take that as 
>>>>>           Tested-by: Craig Tatlor <ctatlor97@gmail.com>  ?
>>>>>
>>>>
>>>> Is this patch series going to be resent?
>>>>
>>>
>>> Nevermind. Looking at it I think I can apply all the clk ones and we're
>>> good to go. If you can send a followup patch series to change the
>>> registration and provider APIs to be clk_hw instead of clk based I would
>>> appreciate it.
>>>
>>
>> Sorry for the late response. Was away.
>> Only pending thing was separating out the binding documentation for the cpu-freq
>> driver and fixing the text in documentation.  That means, yes its fine to merge
>> the clk ones as you said. I will resend that. Also, will send a follow up series for clk_hw to
>> clk change as you mentioned separately.
> 
> Hello Sricharan,
> 
> Great to see that the clk parts has been marged to clk-next!
> 
> Are you also planning on sending out a new version of the cpufreq driver
> consolidation parts?
> 
   yeah right, will send a new version, sometime next week.

> I'm planning on extending your consilidated cpufreq driver with support
> for msm8916 (Cortex-A53), where I plan to read PVS/speedbin, in order to
> set opp_supported_hw(), and also register with cpufreq (since Viresh/Ulf
> suggested that we shouldn't register with cpufreq in the CPR power-domain
> driver).

   ok sure.

Regards,
 Sricharan

-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 32+ messages in thread

end of thread, other threads:[~2018-10-24  4:11 UTC | newest]

Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-08-14 12:12 [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
2018-08-14 12:12 ` [PATCH v12 01/14] ARM: Add Krait L2 register accessor functions Sricharan R
2018-08-14 12:12 ` [PATCH v12 02/14] clk: qcom: Add support for High-Frequency PLLs (HFPLLs) Sricharan R
2018-08-14 12:12 ` [PATCH v12 03/14] clk: qcom: Add HFPLL driver Sricharan R
2018-08-14 12:12 ` [PATCH v12 04/14] dt-bindings: clock: Document qcom,hfpll Sricharan R
2018-08-14 12:12 ` [PATCH v12 05/14] clk: qcom: Add MSM8960/APQ8064's HFPLLs Sricharan R
2018-08-14 12:12 ` [PATCH v12 06/14] clk: qcom: Add IPQ806X's HFPLLs Sricharan R
2018-08-14 12:12 ` [PATCH v12 07/14] clk: qcom: Add support for Krait clocks Sricharan R
2018-08-14 12:12 ` [PATCH v12 08/14] clk: qcom: Add KPSS ACC/GCC driver Sricharan R
2018-08-14 12:12 ` [PATCH v12 09/14] dt-bindings: arm: Document qcom,kpss-gcc Sricharan R
2018-08-14 12:12 ` [PATCH v12 10/14] clk: qcom: Add Krait clock controller driver Sricharan R
2018-08-14 12:12 ` [PATCH v12 11/14] dt-bindings: clock: Document qcom,krait-cc Sricharan R
2018-08-14 12:12 ` [PATCH v12 12/14] clk: qcom: Add safe switch hook for krait mux clocks Sricharan R
2018-08-14 12:12 ` [PATCH v12 13/14] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs Sricharan R
2018-08-17 15:09   ` Rob Herring
2018-08-20 12:45     ` Sricharan R
2018-08-14 12:12 ` [PATCH v12 14/14] cpufreq: qcom: Add support for krait based socs Sricharan R
2018-08-17 15:09   ` Rob Herring
2018-08-24 15:21   ` Niklas Cassel
2018-08-24 19:15   ` Niklas Cassel
2018-08-14 12:20 ` [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
2018-09-07  9:57   ` Sricharan R
2018-09-07 14:28     ` Craig Tatlor
2018-09-19 20:24       ` Craig
2018-09-20 13:01         ` Sricharan R
2018-09-20 14:27           ` Craig
2018-09-20 13:03         ` Sricharan R
2018-10-17 15:44           ` Stephen Boyd
2018-10-17 20:16             ` Stephen Boyd
2018-10-22  4:09               ` Sricharan R
2018-10-22 15:30                 ` Niklas Cassel
2018-10-24  4:11                   ` Sricharan R

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