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Dong" To: "linux-clk@vger.kernel.org" CC: "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "sboyd@kernel.org" , "mturquette@baylibre.com" , "shawnguo@kernel.org" , Anson Huang , Jacky Bai , dl-linux-imx , "A.s. Dong" Subject: [PATCH RESEND V4 8/9] clk: imx: implement new clk_hw based APIs Thread-Topic: [PATCH RESEND V4 8/9] clk: imx: implement new clk_hw based APIs Thread-Index: AQHUaT+NZo5TTqpOaEC5sONxzw120A== Date: Sun, 21 Oct 2018 13:11:17 +0000 Message-ID: <1540127173-21346-9-git-send-email-aisheng.dong@nxp.com> References: <1540127173-21346-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1540127173-21346-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK0PR01CA0034.apcprd01.prod.exchangelabs.com (2603:1096:203:3e::22) To AM0PR04MB4211.eurprd04.prod.outlook.com (2603:10a6:208:66::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;AM0PR04MB4580;6:9RwwNoNxco8xyvqWK6DvMsHvz/qNsfu06hjlJM303zdF53UtIHH4CBwFfV4iLXVV6TWB9TMacNJoTcG0A1L5ur9ijqkmV+sLInrZ/ugVMofRixa3ylKS/acv2Uz+bqmJrgH5KysejIODcP4JLGmZ/3W77JU+EBnqdcpi0sBhZUz6/yES4bXOqA3+bvPt6pP9iGDbQ5EKdzCsy8mQ/kJbzf7gsGECWsQrIMgIKO7G5mNczX47d2e2XuOTzFfdXlj75UrHbPeloKcZT/3jvwmkPP+Opz8WA1jcSoY/G5un69cJmdbVj7QeAqesxP1QFxvOQaFvkkpIeufDoWQ6/9SxPTqrE3gebA8OdKECNNQdphke5piCs84VkfPskXMv4HngIHth3zhGnlr3LVC+bIU2a0q6CNPPI+9BPylnIrWE+XZt4xQ0sJyETksoKk+wVlsptNxTfpgDAic9eOF96oTOZw==;5:WzPZ/Mn/3vaJeTeEKksmE4MC2O8hH5GT1Ig7qdzXTg/RBv+VVZgB2B8wqHtwAcbG/6xNJlQf78spm1UJVPOJ3OVI/RdIXmynmXx6HMkuX9ntIaRUJ4gWc2oJEZyZIyjC1ehqahzWpC9ItZ6CDvfWkDaMXKeZo5KSUeibNUqYPVo=;7:rNIoJ05DA8t6l9QAlax72IYROT6xLPCt0fK9QBV/0etQJJRJo1s4jzW/kmhindxdtfSHVGOvToMQlka07+MudXiD4OqZAMFeqk/JFEHIyRjOYgKFPMBcd33ckT6ofl9hyESFYo7nLJndz5jGm1gvciobC4dfkWBRKefklKBr7vfLMtMRlFRIvh+BbYPgYXRgFym936z9m4WMdQFefw9eqvtcQJeM6slJzdQXi7VvFTlKOSL1zHCSW42R82GJi3Gj x-ms-office365-filtering-correlation-id: 7ac7bc46-0de9-4b5c-5d56-08d63756af70 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020);SRVR:AM0PR04MB4580; x-ms-traffictypediagnostic: AM0PR04MB4580: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(185117386973197); x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(93006095)(93001095)(10201501046)(3002001)(3231355)(944501410)(52105095)(6055026)(148016)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123562045)(20161123564045)(20161123560045)(201708071742011)(7699051)(76991095);SRVR:AM0PR04MB4580;BCL:0;PCL:0;RULEID:;SRVR:AM0PR04MB4580; x-forefront-prvs: 083289FD26 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(376002)(396003)(366004)(346002)(39850400004)(136003)(54534003)(199004)(189003)(476003)(2616005)(11346002)(446003)(66066001)(54906003)(316002)(26005)(52116002)(99286004)(486006)(186003)(7736002)(386003)(6506007)(305945005)(102836004)(105586002)(76176011)(50226002)(86362001)(106356001)(256004)(14444005)(81156014)(81166006)(217873002)(8936002)(8676002)(6916009)(5250100002)(25786009)(2900100001)(2501003)(68736007)(71190400001)(2906002)(5660300001)(14454004)(3846002)(4326008)(6116002)(6512007)(53936002)(2351001)(6486002)(36756003)(71200400001)(478600001)(5640700003)(97736004)(6436002);DIR:OUT;SFP:1101;SCL:1;SRVR:AM0PR04MB4580;H:AM0PR04MB4211.eurprd04.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: X6YSlSGUverZHUcVRRAp4lkc5ywo55FpB0ed3CPtfap0jhmVwobKscBLifadHypFoTLQRtEpuG0oIuyhFW64Tp5kHc12QNBASZ1Gcm1gkI7ctRx6reJNgp9YPZGTag33eed18lIuSx6UEA/6jQYsLrbIR8SA+LpqFf4dXtAKtKDyH/k3r5SzbaTrojPSTT3ueP9otCCN7Aks9yiW4wCz+EuI2B43N9lZzojCgRZUZEy5oJsTAjEWTE9rdFQWzXnjzi/1U+Z277eUhFCUlTdqN6Kcb7UVFAkT4A7e1ky/i0Uo+TbTerI+iIZ2Nm0wBH/7vpcd4BGkrylRiQjyZVE59qaOErrd4OFRLsguh1ZoIbY= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7ac7bc46-0de9-4b5c-5d56-08d63756af70 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Oct 2018 13:11:17.2408 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4580 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Clock providers are recommended to use the new struct clk_hw based API, so implement IMX clk_hw based provider helpers functions to the new approach. Signed-off-by: Dong Aisheng --- ChangeLog: v2->v4: * no changes v1->v2: new patches --- drivers/clk/imx/clk.c | 22 ++++++++++++++++++ drivers/clk/imx/clk.h | 62 +++++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 84 insertions(+) diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index 9074e69..1efed86 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -18,6 +18,16 @@ void __init imx_check_clocks(struct clk *clks[], unsigne= d int count) i, PTR_ERR(clks[i])); } =20 +void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count) +{ + unsigned int i; + + for (i =3D 0; i < count; i++) + if (IS_ERR(clks[i])) + pr_err("i.MX clk %u: register failed with %ld\n", + i, PTR_ERR(clks[i])); +} + static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name= ) { struct of_phandle_args phandle; @@ -49,6 +59,18 @@ struct clk * __init imx_obtain_fixed_clock( return clk; } =20 +struct clk_hw * __init imx_obtain_fixed_clk_hw(struct device_node *np, + const char *name) +{ + struct clk *clk; + + clk =3D of_clk_get_by_name(np, name); + if (IS_ERR(clk)) + return ERR_PTR(-ENOENT); + + return __clk_get_hw(clk); +} + /* * This fixups the register CCM_CSCMR1 write value. * The write/read/divider values of the aclk_podf field diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 7fca912..d3fcaa5 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -8,6 +8,7 @@ extern spinlock_t imx_ccm_lock; =20 void imx_check_clocks(struct clk *clks[], unsigned int count); +void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count); void imx_register_uart_clocks(struct clk ** const clks[]); =20 extern void imx_cscmr1_fixup(u32 *val); @@ -54,6 +55,9 @@ struct clk *clk_register_gate2(struct device *dev, const = char *name, struct clk * imx_obtain_fixed_clock( const char *name, unsigned long rate); =20 +struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np, + const char *name); + struct clk *imx_clk_gate_exclusive(const char *name, const char *parent, void __iomem *reg, u8 shift, u32 exclusive_mask); =20 @@ -90,6 +94,16 @@ static inline struct clk *imx_clk_fixed(const char *name= , int rate) return clk_register_fixed_rate(NULL, name, NULL, 0, rate); } =20 +static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate) +{ + return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); +} + +static inline struct clk_hw *imx_get_clk_hw_fixed(const char *name, int ra= te) +{ + return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); +} + static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *= reg, u8 shift, u8 width, const char * const *parents, int num_parents) @@ -113,6 +127,15 @@ static inline struct clk *imx_clk_divider(const char *= name, const char *parent, reg, shift, width, 0, &imx_ccm_lock); } =20 +static inline struct clk_hw *imx_clk_hw_divider(const char *name, + const char *parent, + void __iomem *reg, u8 shift, + u8 width) +{ + return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, + reg, shift, width, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_divider_flags(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, unsigned long flags) @@ -121,6 +144,15 @@ static inline struct clk *imx_clk_divider_flags(const = char *name, reg, shift, width, 0, &imx_ccm_lock); } =20 +static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name, + const char *parent, + void __iomem *reg, u8 shift, + u8 width, unsigned long flags) +{ + return clk_hw_register_divider(NULL, name, parent, flags, + reg, shift, width, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_divider2(const char *name, const char *p= arent, void __iomem *reg, u8 shift, u8 width) { @@ -143,6 +175,13 @@ static inline struct clk *imx_clk_gate_flags(const cha= r *name, const char *paren shift, 0, &imx_ccm_lock); } =20 +static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char = *parent, + void __iomem *reg, u8 shift) +{ + return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, + shift, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_gate_dis(const char *name, const char *p= arent, void __iomem *reg, u8 shift) { @@ -222,6 +261,17 @@ static inline struct clk *imx_clk_mux2(const char *nam= e, void __iomem *reg, reg, shift, width, 0, &imx_ccm_lock); } =20 +static inline struct clk_hw *imx_clk_hw_mux2(const char *name, void __iome= m *reg, + u8 shift, u8 width, + const char * const *parents, + int num_parents) +{ + return clk_hw_register_mux(NULL, name, parents, num_parents, + CLK_SET_RATE_NO_REPARENT | + CLK_OPS_PARENT_ENABLE, + reg, shift, width, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_mux_flags(const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents, @@ -232,6 +282,18 @@ static inline struct clk *imx_clk_mux_flags(const char= *name, &imx_ccm_lock); } =20 +static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name, + void __iomem *reg, u8 shift, + u8 width, + const char * const *parents, + int num_parents, + unsigned long flags) +{ + return clk_hw_register_mux(NULL, name, parents, num_parents, + flags | CLK_SET_RATE_NO_REPARENT, + reg, shift, width, 0, &imx_ccm_lock); +} + struct clk *imx_clk_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step); --=20 2.7.4