From: Luwei Kang <luwei.kang@intel.com>
To: kvm@vger.kernel.org, x86@kernel.org
Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
hpa@zytor.com, pbonzini@redhat.com, rkrcmar@redhat.com,
joro@8bytes.org, songliubraving@fb.com, peterz@infradead.org,
alexander.shishkin@linux.intel.com, kstewart@linuxfoundation.org,
gregkh@linuxfoundation.org, thomas.lendacky@amd.com,
konrad.wilk@oracle.com, mattst88@gmail.com,
Janakarajan.Natarajan@amd.com, dwmw@amazon.co.uk,
jpoimboe@redhat.com, marcorr@google.com, ubizjak@gmail.com,
sean.j.christopherson@intel.com, jmattson@google.com,
linux-kernel@vger.kernel.org, Luwei Kang <luwei.kang@intel.com>
Subject: [PATCH v13 05/12] perf/x86/intel/pt: add new capability for Intel PT
Date: Wed, 24 Oct 2018 16:05:09 +0800 [thread overview]
Message-ID: <1540368316-12998-6-git-send-email-luwei.kang@intel.com> (raw)
In-Reply-To: <1540368316-12998-1-git-send-email-luwei.kang@intel.com>
This adds support for "output to Trace Transport subsystem"
capability of Intel PT. It means that PT can output its
trace to an MMIO address range rather than system memory buffer.
Acked-by: Song Liu <songliubraving@fb.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
arch/x86/events/intel/pt.c | 1 +
arch/x86/include/asm/intel_pt.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index 53e481a..9597ea6 100644
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -68,6 +68,7 @@
PT_CAP(topa_output, 0, CPUID_ECX, BIT(0)),
PT_CAP(topa_multiple_entries, 0, CPUID_ECX, BIT(1)),
PT_CAP(single_range_output, 0, CPUID_ECX, BIT(2)),
+ PT_CAP(output_subsys, 0, CPUID_ECX, BIT(3)),
PT_CAP(payloads_lip, 0, CPUID_ECX, BIT(31)),
PT_CAP(num_address_ranges, 1, CPUID_EAX, 0x3),
PT_CAP(mtc_periods, 1, CPUID_EAX, 0xffff0000),
diff --git a/arch/x86/include/asm/intel_pt.h b/arch/x86/include/asm/intel_pt.h
index 00f4afb..634f99b 100644
--- a/arch/x86/include/asm/intel_pt.h
+++ b/arch/x86/include/asm/intel_pt.h
@@ -16,6 +16,7 @@ enum pt_capabilities {
PT_CAP_topa_output,
PT_CAP_topa_multiple_entries,
PT_CAP_single_range_output,
+ PT_CAP_output_subsys,
PT_CAP_payloads_lip,
PT_CAP_num_address_ranges,
PT_CAP_mtc_periods,
--
1.8.3.1
next prev parent reply other threads:[~2018-10-24 8:07 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-24 8:05 [PATCH v13 00/12] Intel Processor Trace virtualization enabling Luwei Kang
2018-10-24 8:05 ` [PATCH v13 01/12] perf/x86/intel/pt: Move Intel PT MSRs bit defines to global header Luwei Kang
2018-10-24 8:05 ` [PATCH v13 02/12] perf/x86/intel/pt: Export pt_cap_get() Luwei Kang
2018-10-24 8:05 ` [PATCH v13 03/12] perf/x86/intel/pt: Introduce intel_pt_validate_cap() Luwei Kang
2018-10-24 8:05 ` [PATCH v13 04/12] perf/x86/intel/pt: Add new bit definitions for PT MSRs Luwei Kang
2018-10-24 8:05 ` Luwei Kang [this message]
2018-10-30 9:57 ` [PATCH v13 05/12] perf/x86/intel/pt: add new capability for Intel PT Thomas Gleixner
2018-10-24 8:05 ` [PATCH v13 06/12] KVM: x86: Add Intel PT virtualization work mode Luwei Kang
2018-10-24 16:18 ` Jim Mattson
2018-10-25 0:35 ` Kang, Luwei
2018-10-30 9:30 ` Thomas Gleixner
2018-10-30 9:49 ` Paolo Bonzini
2018-10-30 10:13 ` Kang, Luwei
2018-10-30 10:23 ` Thomas Gleixner
2018-10-31 0:36 ` Kang, Luwei
2018-10-24 8:05 ` [PATCH v13 07/12] KVM: x86: Add Intel Processor Trace cpuid emulation Luwei Kang
2018-10-24 8:05 ` [PATCH v13 08/12] KVM: x86: Add Intel PT context switch for each vcpu Luwei Kang
2018-10-24 10:13 ` Alexander Shishkin
2018-10-25 0:06 ` Kang, Luwei
2018-10-29 17:48 ` Paolo Bonzini
2018-10-30 10:00 ` Thomas Gleixner
2018-10-31 10:43 ` Paolo Bonzini
2018-10-31 11:46 ` Alexander Shishkin
2018-10-30 11:26 ` Alexander Shishkin
2018-10-31 10:49 ` Paolo Bonzini
2018-10-31 11:38 ` Alexander Shishkin
2018-10-31 12:07 ` Paolo Bonzini
2018-10-31 14:21 ` Alexander Shishkin
2018-10-31 14:43 ` Paolo Bonzini
2018-10-24 8:05 ` [PATCH v13 09/12] KVM: x86: Introduce a function to initialize the PT configuration Luwei Kang
2018-10-24 8:05 ` [PATCH v13 10/12] KVM: x86: Implement Intel PT MSRs read/write emulation Luwei Kang
2018-10-24 8:05 ` [PATCH v13 11/12] KVM: x86: Set intercept for Intel PT MSRs read/write Luwei Kang
2018-10-24 8:05 ` [PATCH v13 12/12] KVM: x86: Disable Intel PT when VMXON in L1 guest Luwei Kang
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