From: Stephen Boyd <sboyd@kernel.org>
To: Nicolas Boichat <drinkcat@chromium.org>,
Weiyi Lu <weiyi.lu@mediatek.com>
Cc: Rob Herring <robh@kernel.org>,
srv_heupstream@mediatek.com, jamesjj.liao@mediatek.com,
sboyd@codeaurora.org, lkml <linux-kernel@vger.kernel.org>,
fan.chen@mediatek.com, linux-mediatek@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>,
owen.chen@mediatek.com, linux-clk@vger.kernel.org,
linux-arm Mailing List <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v1 02/11] clk: mediatek: add new member to mtk_pll_data
Date: Wed, 21 Nov 2018 00:03:24 -0800 [thread overview]
Message-ID: <154278740462.88331.17720342357503268022@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <1542685880.5132.11.camel@mtksdaap41>
Quoting Weiyi Lu (2018-11-19 19:51:20)
> On Tue, 2018-11-13 at 08:18 -0800, Nicolas Boichat wrote:
> > On Mon, Nov 5, 2018 at 10:43 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
> > > @@ -138,9 +140,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
> > > static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
> > > u32 freq, u32 fin)
> > > {
> > > - unsigned long fmin = 1000 * MHZ;
> > > + unsigned long fmin = pll->data->fmin ? pll->data->fmin : 1000 * MHZ;
> >
> > I'd put parentheses around (1000 * MHZ), to avoid the need to think
> > about precedence...
> >
>
> OK, thanks for the suggestion. will add in next version
Better style would be to not use a ternary statement for anything like
this and have an if condition instead.
next prev parent reply other threads:[~2018-11-21 8:03 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-06 6:41 [PATCH v1 00/11] Mediatek MT8183 clock and scpsys support Weiyi Lu
2018-11-06 6:41 ` Weiyi Lu
2018-11-06 6:41 ` [PATCH v1 01/11] clk: mediatek: add new clkmux register API Weiyi Lu
2018-11-13 16:00 ` Nicolas Boichat
2018-11-20 6:34 ` Weiyi Lu
2018-11-06 6:41 ` [PATCH v1 02/11] clk: mediatek: add new member to mtk_pll_data Weiyi Lu
2018-11-13 16:18 ` Nicolas Boichat
2018-11-20 3:51 ` Weiyi Lu
2018-11-21 8:03 ` Stephen Boyd [this message]
2018-11-06 6:41 ` [PATCH v1 03/11] clk: mediatek: Disable tuner_en before change PLL rate Weiyi Lu
2018-11-06 6:41 ` [PATCH v1 04/11] soc: mediatek: add new flow for mtcmos power Weiyi Lu
2018-11-13 19:31 ` Nicolas Boichat
2018-11-20 2:37 ` Weiyi Lu
2018-11-21 8:07 ` Stephen Boyd
2018-11-21 9:21 ` Weiyi Lu
2018-11-06 6:42 ` [PATCH v1 05/11] dt-bindings: ARM: Mediatek: Document bindings for MT8183 Weiyi Lu
2018-11-06 6:42 ` [PATCH v1 06/11] clk: mediatek: Add dt-bindings for MT8183 clocks Weiyi Lu
2018-11-06 6:42 ` [PATCH v1 07/11] clk: mediatek: Add flags support for mtk_gate data Weiyi Lu
2018-11-06 6:42 ` [PATCH v1 08/11] clk: mediatek: Add MT8183 clock support Weiyi Lu
2018-11-14 6:25 ` Nicolas Boichat
2018-11-19 4:14 ` Weiyi Lu
2018-11-06 6:42 ` [PATCH v1 09/11] dt-bindings: soc: fix typo of MT8173 power dt-bindings Weiyi Lu
2018-11-06 6:42 ` [PATCH v1 10/11] dt-bindings: soc: Add MT8183 " Weiyi Lu
2018-11-06 6:42 ` [PATCH v1 11/11] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
2018-11-13 19:35 ` Nicolas Boichat
2018-11-19 3:59 ` Weiyi Lu
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