[PATCH] clk: imx: Use do_div in SCCG due to 64-bit divisor

[Abel Vesa <abel.vesa@nxp.com>]

On arm32, a division with a 64-bit divisor has to be done through
do_div() function otherwise there is a link failure like:

drivers/clk/imx/clk-frac-pll.o: In function `clk_pll_round_rate':
clk-frac-pll.c:(.text+0x54): undefined reference to `__aeabi_uldivmod'
make: *** [Makefile:1040: vmlinux] Error 1

Fixes: 9fd680d0fafd ("clk: imx: add fractional PLL output clock")
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
 drivers/clk/imx/clk-frac-pll.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c
index 9872620..8b13df9 100644
--- a/drivers/clk/imx/clk-frac-pll.c
+++ b/drivers/clk/imx/clk-frac-pll.c
@@ -116,12 +116,13 @@ static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 			       unsigned long *prate)
 {
 	u64 parent_rate = *prate;
-	u32 divff, divfi;
-	u64 temp64;
+	u64 divff, divfi;
+	u64 temp64 = rate;
 
 	parent_rate *= 8;
 	rate *= 2;
-	divfi = rate / parent_rate;
+	do_div(temp64, parent_rate);
+	divfi = temp64;
 	temp64 = rate - divfi * parent_rate;
 	temp64 *= PLL_FRAC_DENOM;
 	do_div(temp64, parent_rate);
-- 
2.7.4