[PATCH v7 0/9] Port the FSL QSPI driver to the SPI framework

[PATCH v7 0/9] Port the FSL QSPI driver to the SPI framework

[Schrempf Frieder]

From: Frieder Schrempf <frieder.schrempf@kontron.de>

Now that the SPI memory interface was introduced by Boris, it is
possible to move drivers from mtd/spi-nor to the SPI framework in order
to use them for different type of SPI memory chips.

Patch 1 and 2 removes some unused properties from the devicetree and fixes the
reg properties to correctly reflect the hardware setup.

Patch 3 adds the driver for the Freescale QSPI controller to the SPI
framework. Together with m25p80.c it can be used to interface SPI
NOR flashes just as the old driver did. This patch also disables the build
of the old driver.

Patch 4 moves the bindings to the correct place and patch 5 adjusts the
bindings for the new driver.

Patch 6 removes the code of the old driver.

Patch 7 and 8 remove 'fsl,qspi-has-second-chip' from the devicetrees.
Patch 9 adjusts the MAINTAINERS file.

The new driver was tested with the following setups:
* i.MX6UL and a Micron SPI NOR @ 60MHz.
* i.MX6UL and a Toshiba TC58CVG2S0H SPI NAND flash.
* LS1088ARDB with two SPI NOR chips connected to CS0 and CS1 (Yogesh Gaur)
* Other i.MX platforms (Han Xu)

The read performance of the new driver is almost the same or even better
than the old driver, depending on the block size.
The write performance is a bit slower on average (~10-15%).

---
Changes in v7:
==============
* Remove unused variables in fsl_qspi_select_mem()
* Update cover letter

Changes in v6:
==============
* Add a quirk for LS2080A SoC to fix multi chip setup
* Use separate area in AHB memory map for each chip
* Add R-b tags for binding changes

Changes in v5:
==============
* Change SoB tags and commit author to new e-mail address
* Drop change in compatible string of bindings
* Reset the AHB domain
* Drop the defconfig changes and reuse the Kconfig option of the old driver
* Remove unused read()/write() pointers from struct fsl_qspi
* Remove unused enum fsl_qspi_devtype
* Fix break condition for fsl_qspi_readl_poll_tout()

Changes in v4:
==============
* Rebase on top of v4.20-rc1
* Drop patches that were merged separately
* Address change of company name and email address
* Use readl_poll_timeout() instead of busy waiting
* Revert change to use callback functions for register read/write
* Avoid divide by zero by checking op->dummy.nbytes
* Make big-endian setting SoC-specific and don't read it from devicetree
* Improve some register macros and masks

Changes in v3:
==============
* Move fix for typo in spi-mem.h to a separate patch
* Fix documentation of spi_mem_get_name() and get_name()
* Avoid overwriting the name of the memory device in probe of m25p80
* Add Suggested-by tags

Changes in v2:
==============
* Rebase on top of nand/next
* Add a name field to struct spi_mem and fill it while probing
* Add Yogesh Gaur and Suresh Gupta as authors
* Use GENMASK() for generating bitmasks
* Use callback functions for read/write of registers
* Attach the seq variable to the selected CS
* Avoid using conditional in read/write loop
* Avoid infinite loop and use a timeout instead
* Return error pointer when allocation in fsl_qspi_get_name() fails
* Remove redundant iounmap()
* Put suspend()/resume() in dev_pm_ops instead of platform_driver
* Split the moving and editing of the dt-bindings in two patches
---
Frieder Schrempf (9):
  ARM: dts: Reflect change of FSL QSPI driver and remove unused
    properties
  arm64: dts: Reflect change of FSL QSPI driver and remove unused
    properties
  spi: Add a driver for the Freescale/NXP QuadSPI controller
  dt-bindings: spi: Move the bindings for the FSL QSPI driver
  dt-bindings: spi: Adjust the bindings for the FSL QSPI driver
  mtd: fsl-quadspi: Remove the driver as it was replaced by
    spi-fsl-qspi.c
  ARM: dts: ls1021a: Remove fsl,qspi-has-second-chip as it is not used
  ARM64: dts: ls1046a: Remove fsl,qspi-has-second-chip as it is not used
  MAINTAINERS: Move the Freescale QSPI driver to the SPI framework

 .../fsl-quadspi.txt => spi/spi-fsl-qspi.txt}    |   18 +-
 MAINTAINERS                                     |    4 +-
 arch/arm/boot/dts/imx6sx-sdb-reva.dts           |    8 +-
 arch/arm/boot/dts/imx6sx-sdb.dts                |    8 +-
 arch/arm/boot/dts/imx6ul-14x14-evk.dtsi         |    2 +
 arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts     |    6 +-
 .../boot/dts/freescale/fsl-ls1043a-qds.dts      |    3 +-
 .../boot/dts/freescale/fsl-ls1046a-qds.dts      |    4 +-
 .../boot/dts/freescale/fsl-ls1046a-rdb.dts      |    6 +-
 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi  |    1 -
 .../boot/dts/freescale/fsl-ls208xa-qds.dtsi     |    4 +
 drivers/mtd/spi-nor/Kconfig                     |    9 -
 drivers/mtd/spi-nor/Makefile                    |    1 -
 drivers/mtd/spi-nor/fsl-quadspi.c               | 1224 ------------------
 drivers/spi/Kconfig                             |   11 +
 drivers/spi/Makefile                            |    1 +
 drivers/spi/spi-fsl-qspi.c                      |  966 ++++++++++++++
 17 files changed, 1016 insertions(+), 1260 deletions(-)
 rename Documentation/devicetree/bindings/{mtd/fsl-quadspi.txt => spi/spi-fsl-qspi.txt} (73%)
 delete mode 100644 drivers/mtd/spi-nor/fsl-quadspi.c
 create mode 100644 drivers/spi/spi-fsl-qspi.c

-- 
2.7.4

[PATCH v7 1/9] ARM: dts: Reflect change of FSL QSPI driver and remove unused properties

[Schrempf Frieder]

From: Frieder Schrempf <frieder.schrempf@kontron.de>

The FSL QSPI driver will be moved to the SPI framework and it then
acts as a SPI controller. Therefore the subnodes need to set
spi-[rx/tx]-bus-width = <4>, so quad mode is used just as before.

Also the properties 'bus-num', 'fsl,spi-num-chipselects' and
'fsl,spi-flash-chipselects' were never read by the driver and
can be removed.

The 'reg' properties are adjusted to reflect what bus and
chipselect the flash is connected to, as the new driver needs
this information.

The property 'fsl,qspi-has-second-chip' is not needed anymore
and will be removed after the old driver was disabled to avoid
breaking ls1021a-moxa-uc-8410a.dts.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
---
 arch/arm/boot/dts/imx6sx-sdb-reva.dts       | 8 ++++++--
 arch/arm/boot/dts/imx6sx-sdb.dts            | 8 ++++++--
 arch/arm/boot/dts/imx6ul-14x14-evk.dtsi     | 2 ++
 arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 5 ++---
 4 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
index 9cc6ff2..9997156 100644
--- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
@@ -132,13 +132,17 @@
 		#size-cells = <1>;
 		compatible = "spansion,s25fl128s", "jedec,spi-nor";
 		spi-max-frequency = <66000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 	};
 
-	flash1: s25fl128s@1 {
-		reg = <1>;
+	flash1: s25fl128s@2 {
+		reg = <2>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "spansion,s25fl128s", "jedec,spi-nor";
 		spi-max-frequency = <66000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 	};
 };
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 6dd9beb..9acfda8 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -117,15 +117,19 @@
 		#size-cells = <1>;
 		compatible = "micron,n25q256a", "jedec,spi-nor";
 		spi-max-frequency = <29000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 		reg = <0>;
 	};
 
-	flash1: n25q256a@1 {
+	flash1: n25q256a@2 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "micron,n25q256a", "jedec,spi-nor";
 		spi-max-frequency = <29000000>;
-		reg = <1>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
+		reg = <2>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
index 32a0723..c2c9a2a 100644
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
@@ -176,6 +176,8 @@
 		#size-cells = <1>;
 		compatible = "micron,n25q256a";
 		spi-max-frequency = <29000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 		reg = <0>;
 	};
 };
diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
index d01f64b..6a83f30 100644
--- a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
+++ b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
@@ -203,9 +203,6 @@
 };
 
 &qspi {
-	bus-num = <0>;
-	fsl,spi-num-chipselects = <2>;
-	fsl,spi-flash-chipselects = <0>;
 	fsl,qspi-has-second-chip;
 	status = "okay";
 
@@ -214,6 +211,8 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		spi-max-frequency = <20000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 		reg = <0>;
 
 		partitions@0 {
-- 
2.7.4

[PATCH v7 2/9] arm64: dts: Reflect change of FSL QSPI driver and remove unused properties

[Schrempf Frieder]

From: Frieder Schrempf <frieder.schrempf@kontron.de>

The FSL QSPI driver will be moved to the SPI framework and it then
acts as a SPI controller. Therefore the subnodes need to set
spi-[rx/tx]-bus-width = <4>, so quad mode is used just as before.

Also the properties 'num-cs' and 'bus-num' were never read by the
driver and can be removed.

The property 'fsl,qspi-has-second-chip' is not needed anymore
and will be removed after the old driver was disabled to avoid
breaking fsl-ls1046a-rdb.dts.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
---
 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts  | 3 ++-
 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts  | 4 ++--
 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts  | 6 ++++--
 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi | 4 ++++
 4 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
index dff3d64..8a50094 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
@@ -135,7 +135,6 @@
 };
 
 &qspi {
-	bus-num = <0>;
 	status = "okay";
 
 	qflash0: s25fl128s@0 {
@@ -143,6 +142,8 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		spi-max-frequency = <20000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 		reg = <0>;
 	};
 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
index e58a8ca..2f220ec 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
@@ -163,8 +163,6 @@
 };
 
 &qspi {
-	num-cs = <2>;
-	bus-num = <0>;
 	status = "okay";
 
 	qflash0: s25fl128s@0 {
@@ -172,6 +170,8 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		spi-max-frequency = <20000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 		reg = <0>;
 	};
 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index a59b482..07c665c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -99,8 +99,6 @@
 };
 
 &qspi {
-	num-cs = <2>;
-	bus-num = <0>;
 	status = "okay";
 
 	qflash0: s25fs512s@0 {
@@ -108,6 +106,8 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		spi-max-frequency = <20000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 		reg = <0>;
 	};
 
@@ -116,6 +116,8 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		spi-max-frequency = <20000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 		reg = <1>;
 	};
 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
index c11f52e..10d2fe0 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
@@ -134,6 +134,8 @@
 		#size-cells = <1>;
 		compatible = "st,m25p80";
 		spi-max-frequency = <20000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 		reg = <0>;
 	};
 	flash2: s25fl256s1@2 {
@@ -141,6 +143,8 @@
 		#size-cells = <1>;
 		compatible = "st,m25p80";
 		spi-max-frequency = <20000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 		reg = <2>;
 	};
 };
-- 
2.7.4

[PATCH v7 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Schrempf Frieder]

From: Frieder Schrempf <frieder.schrempf@kontron.de>

This driver is derived from the SPI NOR driver at
mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface
of the SPI framework to issue flash memory operations to up to
four connected flash chips (2 buses with 2 CS each).

The controller does not support generic SPI messages.

This patch also disables the build of the "old" driver and reuses
its Kconfig option CONFIG_SPI_FSL_QUADSPI to replace it.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
---
 drivers/mtd/spi-nor/Kconfig  |   9 -
 drivers/mtd/spi-nor/Makefile |   1 -
 drivers/spi/Kconfig          |  11 +
 drivers/spi/Makefile         |   1 +
 drivers/spi/spi-fsl-qspi.c   | 966 ++++++++++++++++++++++++++++++++++++++
 5 files changed, 978 insertions(+), 10 deletions(-)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 6cc9c92..d1ca307 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -59,15 +59,6 @@ config SPI_CADENCE_QUADSPI
 	  device with a Cadence QSPI controller and want to access the
 	  Flash as an MTD device.
 
-config SPI_FSL_QUADSPI
-	tristate "Freescale Quad SPI controller"
-	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
-	depends on HAS_IOMEM
-	help
-	  This enables support for the Quad SPI controller in master mode.
-	  This controller does not support generic SPI. It only supports
-	  SPI NOR.
-
 config SPI_HISI_SFC
 	tristate "Hisilicon SPI-NOR Flash Controller(SFC)"
 	depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
index f4c61d2..3f160c2e3 100644
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
@@ -3,7 +3,6 @@ obj-$(CONFIG_MTD_SPI_NOR)	+= spi-nor.o
 obj-$(CONFIG_SPI_ASPEED_SMC)	+= aspeed-smc.o
 obj-$(CONFIG_SPI_ATMEL_QUADSPI)	+= atmel-quadspi.o
 obj-$(CONFIG_SPI_CADENCE_QUADSPI)	+= cadence-quadspi.o
-obj-$(CONFIG_SPI_FSL_QUADSPI)	+= fsl-quadspi.o
 obj-$(CONFIG_SPI_HISI_SFC)	+= hisi-sfc.o
 obj-$(CONFIG_MTD_MT81xx_NOR)    += mtk-quadspi.o
 obj-$(CONFIG_SPI_NXP_SPIFI)	+= nxp-spifi.o
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 7d3a5c9..8c84186 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -259,6 +259,17 @@ config SPI_FSL_LPSPI
 	help
 	  This enables Freescale i.MX LPSPI controllers in master mode.
 
+config SPI_FSL_QUADSPI
+	tristate "Freescale QSPI controller"
+	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
+	depends on HAS_IOMEM
+	help
+	  This enables support for the Quad SPI controller in master mode.
+	  Up to four flash chips can be connected on two buses with two
+	  chipselects each.
+	  This controller does not support generic SPI messages. It only
+	  supports the high-level SPI memory interface.
+
 config SPI_GPIO
 	tristate "GPIO-based bitbanging SPI Master"
 	depends on GPIOLIB || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3575205..5377e61 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_SPI_FSL_DSPI)		+= spi-fsl-dspi.o
 obj-$(CONFIG_SPI_FSL_LIB)		+= spi-fsl-lib.o
 obj-$(CONFIG_SPI_FSL_ESPI)		+= spi-fsl-espi.o
 obj-$(CONFIG_SPI_FSL_LPSPI)		+= spi-fsl-lpspi.o
+obj-$(CONFIG_SPI_FSL_QUADSPI)		+= spi-fsl-qspi.o
 obj-$(CONFIG_SPI_FSL_SPI)		+= spi-fsl-spi.o
 obj-$(CONFIG_SPI_GPIO)			+= spi-gpio.o
 obj-$(CONFIG_SPI_IMG_SPFI)		+= spi-img-spfi.o
diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
new file mode 100644
index 0000000..f0a3400
--- /dev/null
+++ b/drivers/spi/spi-fsl-qspi.c
@@ -0,0 +1,966 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Freescale QuadSPI driver.
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2018 Bootlin
+ * Copyright (C) 2018 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ *
+ * Transition to SPI MEM interface:
+ * Authors:
+ *     Boris Brezillion <boris.brezillon@bootlin.com>
+ *     Frieder Schrempf <frieder.schrempf@kontron.de>
+ *     Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
+ *     Suresh Gupta <suresh.gupta@nxp.com>
+ *
+ * Based on the original fsl-quadspi.c spi-nor driver:
+ * Author: Freescale Semiconductor, Inc.
+ *
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/jiffies.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_qos.h>
+#include <linux/sizes.h>
+
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+
+/*
+ * The driver only uses one single LUT entry, that is updated on
+ * each call of exec_op(). Index 0 is preset at boot with a basic
+ * read operation, so let's use the last entry (15).
+ */
+#define	SEQID_LUT			15
+
+/* Registers used by the driver */
+#define QUADSPI_MCR			0x00
+#define QUADSPI_MCR_RESERVED_MASK	GENMASK(19, 16)
+#define QUADSPI_MCR_MDIS_MASK		BIT(14)
+#define QUADSPI_MCR_CLR_TXF_MASK	BIT(11)
+#define QUADSPI_MCR_CLR_RXF_MASK	BIT(10)
+#define QUADSPI_MCR_DDR_EN_MASK		BIT(7)
+#define QUADSPI_MCR_END_CFG_MASK	GENMASK(3, 2)
+#define QUADSPI_MCR_SWRSTHD_MASK	BIT(1)
+#define QUADSPI_MCR_SWRSTSD_MASK	BIT(0)
+
+#define QUADSPI_IPCR			0x08
+#define QUADSPI_IPCR_SEQID(x)		((x) << 24)
+
+#define QUADSPI_BUF3CR			0x1c
+#define QUADSPI_BUF3CR_ALLMST_MASK	BIT(31)
+#define QUADSPI_BUF3CR_ADATSZ(x)	((x) << 8)
+#define QUADSPI_BUF3CR_ADATSZ_MASK	GENMASK(15, 8)
+
+#define QUADSPI_BFGENCR			0x20
+#define QUADSPI_BFGENCR_SEQID(x)	((x) << 12)
+
+#define QUADSPI_BUF0IND			0x30
+#define QUADSPI_BUF1IND			0x34
+#define QUADSPI_BUF2IND			0x38
+#define QUADSPI_SFAR			0x100
+
+#define QUADSPI_SMPR			0x108
+#define QUADSPI_SMPR_DDRSMP_MASK	GENMASK(18, 16)
+#define QUADSPI_SMPR_FSDLY_MASK		BIT(6)
+#define QUADSPI_SMPR_FSPHS_MASK		BIT(5)
+#define QUADSPI_SMPR_HSENA_MASK		BIT(0)
+
+#define QUADSPI_RBCT			0x110
+#define QUADSPI_RBCT_WMRK_MASK		GENMASK(4, 0)
+#define QUADSPI_RBCT_RXBRD_USEIPS	BIT(8)
+
+#define QUADSPI_TBDR			0x154
+
+#define QUADSPI_SR			0x15c
+#define QUADSPI_SR_IP_ACC_MASK		BIT(1)
+#define QUADSPI_SR_AHB_ACC_MASK		BIT(2)
+
+#define QUADSPI_FR			0x160
+#define QUADSPI_FR_TFF_MASK		BIT(0)
+
+#define QUADSPI_SPTRCLR			0x16c
+#define QUADSPI_SPTRCLR_IPPTRC		BIT(8)
+#define QUADSPI_SPTRCLR_BFPTRC		BIT(0)
+
+#define QUADSPI_SFA1AD			0x180
+#define QUADSPI_SFA2AD			0x184
+#define QUADSPI_SFB1AD			0x188
+#define QUADSPI_SFB2AD			0x18c
+#define QUADSPI_RBDR(x)			(0x200 + ((x) * 4))
+
+#define QUADSPI_LUTKEY			0x300
+#define QUADSPI_LUTKEY_VALUE		0x5AF05AF0
+
+#define QUADSPI_LCKCR			0x304
+#define QUADSPI_LCKER_LOCK		BIT(0)
+#define QUADSPI_LCKER_UNLOCK		BIT(1)
+
+#define QUADSPI_RSER			0x164
+#define QUADSPI_RSER_TFIE		BIT(0)
+
+#define QUADSPI_LUT_BASE		0x310
+#define QUADSPI_LUT_OFFSET		(SEQID_LUT * 4 * 4)
+#define QUADSPI_LUT_REG(idx) \
+	(QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
+
+/* Instruction set for the LUT register */
+#define LUT_STOP		0
+#define LUT_CMD			1
+#define LUT_ADDR		2
+#define LUT_DUMMY		3
+#define LUT_MODE		4
+#define LUT_MODE2		5
+#define LUT_MODE4		6
+#define LUT_FSL_READ		7
+#define LUT_FSL_WRITE		8
+#define LUT_JMP_ON_CS		9
+#define LUT_ADDR_DDR		10
+#define LUT_MODE_DDR		11
+#define LUT_MODE2_DDR		12
+#define LUT_MODE4_DDR		13
+#define LUT_FSL_READ_DDR	14
+#define LUT_FSL_WRITE_DDR	15
+#define LUT_DATA_LEARN		16
+
+/*
+ * The PAD definitions for LUT register.
+ *
+ * The pad stands for the number of IO lines [0:3].
+ * For example, the quad read needs four IO lines,
+ * so you should use LUT_PAD(4).
+ */
+#define LUT_PAD(x) (fls(x) - 1)
+
+/*
+ * Macro for constructing the LUT entries with the following
+ * register layout:
+ *
+ *  ---------------------------------------------------
+ *  | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
+ *  ---------------------------------------------------
+ */
+#define LUT_DEF(idx, ins, pad, opr)					\
+	((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
+
+/* Controller needs driver to swap endianness */
+#define QUADSPI_QUIRK_SWAP_ENDIAN	BIT(0)
+
+/* Controller needs 4x internal clock */
+#define QUADSPI_QUIRK_4X_INT_CLK	BIT(1)
+
+/*
+ * TKT253890, the controller needs the driver to fill the txfifo with
+ * 16 bytes at least to trigger a data transfer, even though the extra
+ * data won't be transferred.
+ */
+#define QUADSPI_QUIRK_TKT253890		BIT(2)
+
+/* TKT245618, the controller cannot wake up from wait mode */
+#define QUADSPI_QUIRK_TKT245618		BIT(3)
+
+/*
+ * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
+ * internally. No need to add it when setting SFXXAD and SFAR registers
+ */
+#define QUADSPI_QUIRK_BASE_INTERNAL	BIT(4)
+
+struct fsl_qspi_devtype_data {
+	unsigned int rxfifo;
+	unsigned int txfifo;
+	unsigned int ahb_buf_size;
+	unsigned int quirks;
+	bool little_endian;
+};
+
+static const struct fsl_qspi_devtype_data vybrid_data = {
+	.rxfifo = SZ_128,
+	.txfifo = SZ_64,
+	.ahb_buf_size = SZ_1K,
+	.quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
+	.little_endian = true,
+};
+
+static const struct fsl_qspi_devtype_data imx6sx_data = {
+	.rxfifo = SZ_128,
+	.txfifo = SZ_512,
+	.ahb_buf_size = SZ_1K,
+	.quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
+	.little_endian = true,
+};
+
+static const struct fsl_qspi_devtype_data imx7d_data = {
+	.rxfifo = SZ_512,
+	.txfifo = SZ_512,
+	.ahb_buf_size = SZ_1K,
+	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
+	.little_endian = true,
+};
+
+static const struct fsl_qspi_devtype_data imx6ul_data = {
+	.rxfifo = SZ_128,
+	.txfifo = SZ_512,
+	.ahb_buf_size = SZ_1K,
+	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
+	.little_endian = true,
+};
+
+static const struct fsl_qspi_devtype_data ls1021a_data = {
+	.rxfifo = SZ_128,
+	.txfifo = SZ_64,
+	.ahb_buf_size = SZ_1K,
+	.quirks = 0,
+	.little_endian = false,
+};
+
+static const struct fsl_qspi_devtype_data ls2080a_data = {
+	.rxfifo = SZ_128,
+	.txfifo = SZ_64,
+	.ahb_buf_size = SZ_1K,
+	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
+	.little_endian = true,
+};
+
+struct fsl_qspi {
+	void __iomem *iobase;
+	void __iomem *ahb_addr;
+	u32 memmap_phy;
+	struct clk *clk, *clk_en;
+	struct device *dev;
+	struct completion c;
+	const struct fsl_qspi_devtype_data *devtype_data;
+	struct mutex lock;
+	struct pm_qos_request pm_qos_req;
+	int selected;
+};
+
+static inline int needs_swap_endian(struct fsl_qspi *q)
+{
+	return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
+}
+
+static inline int needs_4x_clock(struct fsl_qspi *q)
+{
+	return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
+}
+
+static inline int needs_fill_txfifo(struct fsl_qspi *q)
+{
+	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
+}
+
+static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
+{
+	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
+}
+
+static inline int needs_amba_base_offset(struct fsl_qspi *q)
+{
+	return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
+}
+
+/*
+ * An IC bug makes it necessary to rearrange the 32-bit data.
+ * Later chips, such as IMX6SLX, have fixed this bug.
+ */
+static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
+{
+	return needs_swap_endian(q) ? __swab32(a) : a;
+}
+
+/*
+ * R/W functions for big- or little-endian registers:
+ * The QSPI controller's endianness is independent of
+ * the CPU core's endianness. So far, although the CPU
+ * core is little-endian the QSPI controller can use
+ * big-endian or little-endian.
+ */
+static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
+{
+	if (q->devtype_data->little_endian)
+		iowrite32(val, addr);
+	else
+		iowrite32be(val, addr);
+}
+
+static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
+{
+	if (q->devtype_data->little_endian)
+		return ioread32(addr);
+
+	return ioread32be(addr);
+}
+
+static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
+{
+	struct fsl_qspi *q = dev_id;
+	u32 reg;
+
+	/* clear interrupt */
+	reg = qspi_readl(q, q->iobase + QUADSPI_FR);
+	qspi_writel(q, reg, q->iobase + QUADSPI_FR);
+
+	if (reg & QUADSPI_FR_TFF_MASK)
+		complete(&q->c);
+
+	dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg);
+	return IRQ_HANDLED;
+}
+
+static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
+{
+	switch (width) {
+	case 1:
+	case 2:
+	case 4:
+		return 0;
+	}
+
+	return -ENOTSUPP;
+}
+
+static bool fsl_qspi_supports_op(struct spi_mem *mem,
+				 const struct spi_mem_op *op)
+{
+	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+	int ret;
+
+	ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
+
+	if (op->addr.nbytes)
+		ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
+
+	if (op->dummy.nbytes)
+		ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
+
+	if (op->data.nbytes)
+		ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
+
+	if (ret)
+		return false;
+
+	/*
+	 * The number of instructions needed for the op, needs
+	 * to fit into a single LUT entry.
+	 */
+	if (op->addr.nbytes +
+	   (op->dummy.nbytes ? 1:0) +
+	   (op->data.nbytes ? 1:0) > 6)
+		return false;
+
+	/* Max 64 dummy clock cycles supported */
+	if (op->dummy.nbytes &&
+	    (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
+		return false;
+
+	/* Max data length, check controller limits and alignment */
+	if (op->data.dir == SPI_MEM_DATA_IN &&
+	    (op->data.nbytes > q->devtype_data->ahb_buf_size ||
+	     (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
+	      !IS_ALIGNED(op->data.nbytes, 8))))
+		return false;
+
+	if (op->data.dir == SPI_MEM_DATA_OUT &&
+	    op->data.nbytes > q->devtype_data->txfifo)
+		return false;
+
+	return true;
+}
+
+static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
+				 const struct spi_mem_op *op)
+{
+	void __iomem *base = q->iobase;
+	u32 lutval[4] = {};
+	int lutidx = 1, i;
+
+	lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
+			     op->cmd.opcode);
+
+	/*
+	 * For some unknown reason, using LUT_ADDR doesn't work in some
+	 * cases (at least with only one byte long addresses), so
+	 * let's use LUT_MODE to write the address bytes one by one
+	 */
+	for (i = 0; i < op->addr.nbytes; i++) {
+		u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
+
+		lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
+					      LUT_PAD(op->addr.buswidth),
+					      addrbyte);
+		lutidx++;
+	}
+
+	if (op->dummy.nbytes) {
+		lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
+					      LUT_PAD(op->dummy.buswidth),
+					      op->dummy.nbytes * 8 /
+					      op->dummy.buswidth);
+		lutidx++;
+	}
+
+	if (op->data.nbytes) {
+		lutval[lutidx / 2] |= LUT_DEF(lutidx,
+					      op->data.dir == SPI_MEM_DATA_IN ?
+					      LUT_FSL_READ : LUT_FSL_WRITE,
+					      LUT_PAD(op->data.buswidth),
+					      0);
+		lutidx++;
+	}
+
+	lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
+
+	/* unlock LUT */
+	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+	qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
+
+	/* fill LUT */
+	for (i = 0; i < ARRAY_SIZE(lutval); i++)
+		qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
+
+	/* lock LUT */
+	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+	qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
+}
+
+static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
+{
+	int ret;
+
+	ret = clk_prepare_enable(q->clk_en);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(q->clk);
+	if (ret) {
+		clk_disable_unprepare(q->clk_en);
+		return ret;
+	}
+
+	if (needs_wakeup_wait_mode(q))
+		pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
+
+	return 0;
+}
+
+static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
+{
+	if (needs_wakeup_wait_mode(q))
+		pm_qos_remove_request(&q->pm_qos_req);
+
+	clk_disable_unprepare(q->clk);
+	clk_disable_unprepare(q->clk_en);
+}
+
+/*
+ * If we have changed the content of the flash by writing or erasing, or if we
+ * read from flash with a different offset into the page buffer, we need to
+ * invalidate the AHB buffer. If we do not do so, we may read out the wrong
+ * data. The spec tells us reset the AHB domain and Serial Flash domain at
+ * the same time.
+ */
+static void fsl_qspi_invalidate(struct fsl_qspi *q)
+{
+	u32 reg;
+
+	reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
+	reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
+	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
+
+	/*
+	 * The minimum delay : 1 AHB + 2 SFCK clocks.
+	 * Delay 1 us is enough.
+	 */
+	udelay(1);
+
+	reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
+	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
+}
+
+static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi)
+{
+	unsigned long rate = spi->max_speed_hz;
+	int ret;
+
+	if (q->selected == spi->chip_select)
+		return;
+
+	if (needs_4x_clock(q))
+		rate *= 4;
+
+	fsl_qspi_clk_disable_unprep(q);
+
+	ret = clk_set_rate(q->clk, rate);
+	if (ret)
+		return;
+
+	ret = fsl_qspi_clk_prep_enable(q);
+	if (ret)
+		return;
+
+	q->selected = spi->chip_select;
+
+	fsl_qspi_invalidate(q);
+}
+
+static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
+{
+	memcpy_fromio(op->data.buf.in,
+		      q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,
+		      op->data.nbytes);
+}
+
+static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
+				 const struct spi_mem_op *op)
+{
+	void __iomem *base = q->iobase;
+	int i;
+	u32 val;
+
+	for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
+		memcpy(&val, op->data.buf.out + i, 4);
+		val = fsl_qspi_endian_xchg(q, val);
+		qspi_writel(q, val, base + QUADSPI_TBDR);
+	}
+
+	if (i < op->data.nbytes) {
+		memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
+		val = fsl_qspi_endian_xchg(q, val);
+		qspi_writel(q, val, base + QUADSPI_TBDR);
+	}
+
+	if (needs_fill_txfifo(q)) {
+		for (i = op->data.nbytes; i < 16; i += 4)
+			qspi_writel(q, 0, base + QUADSPI_TBDR);
+	}
+}
+
+static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
+			  const struct spi_mem_op *op)
+{
+	void __iomem *base = q->iobase;
+	int i;
+	u8 *buf = op->data.buf.in;
+	u32 val;
+
+	for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
+		val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
+		val = fsl_qspi_endian_xchg(q, val);
+		memcpy(buf + i, &val, 4);
+	}
+
+	if (i < op->data.nbytes) {
+		val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
+		val = fsl_qspi_endian_xchg(q, val);
+		memcpy(buf + i, &val, op->data.nbytes - i);
+	}
+}
+
+static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
+{
+	void __iomem *base = q->iobase;
+	int err = 0;
+
+	init_completion(&q->c);
+
+	/*
+	 * Always start the sequence at the same index since we update
+	 * the LUT at each exec_op() call. And also specify the DATA
+	 * length, since it's has not been specified in the LUT.
+	 */
+	qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
+		    base + QUADSPI_IPCR);
+
+	/* Wait for the interrupt. */
+	if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000)))
+		err = -ETIMEDOUT;
+
+	if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
+		fsl_qspi_read_rxfifo(q, op);
+
+	return err;
+}
+
+static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
+				    u32 mask, u32 delay_us, u32 timeout_us)
+{
+	u32 reg;
+
+	if (!q->devtype_data->little_endian)
+		mask = (u32)cpu_to_be32(mask);
+
+	return readl_poll_timeout(base, reg, !(reg & mask), delay_us,
+				  timeout_us);
+}
+
+static int fsl_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+	void __iomem *base = q->iobase;
+	u32 addr_offset = 0;
+	int err = 0;
+
+	mutex_lock(&q->lock);
+
+	/* wait for the controller being ready */
+	fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
+				 QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
+
+	fsl_qspi_select_mem(q, mem->spi);
+
+	if (needs_amba_base_offset(q))
+		addr_offset = q->memmap_phy;
+
+	qspi_writel(q,
+		    q->selected * q->devtype_data->ahb_buf_size + addr_offset,
+		    base + QUADSPI_SFAR);
+
+	qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
+		    QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
+		    base + QUADSPI_MCR);
+
+	qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
+		    base + QUADSPI_SPTRCLR);
+
+	fsl_qspi_prepare_lut(q, op);
+
+	/*
+	 * If we have large chunks of data, we read them through the AHB bus
+	 * by accessing the mapped memory. In all other cases we use
+	 * IP commands to access the flash.
+	 */
+	if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
+	    op->data.dir == SPI_MEM_DATA_IN) {
+		fsl_qspi_read_ahb(q, op);
+	} else {
+		qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
+			    QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
+
+		if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
+			fsl_qspi_fill_txfifo(q, op);
+
+		err = fsl_qspi_do_op(q, op);
+	}
+
+	/* Invalidate the data in the AHB buffer. */
+	fsl_qspi_invalidate(q);
+
+	mutex_unlock(&q->lock);
+
+	return err;
+}
+
+static int fsl_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
+{
+	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+
+	if (op->data.dir == SPI_MEM_DATA_OUT) {
+		if (op->data.nbytes > q->devtype_data->txfifo)
+			op->data.nbytes = q->devtype_data->txfifo;
+	} else {
+		if (op->data.nbytes > q->devtype_data->ahb_buf_size)
+			op->data.nbytes = q->devtype_data->ahb_buf_size;
+		else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
+			op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
+	}
+
+	return 0;
+}
+
+static int fsl_qspi_default_setup(struct fsl_qspi *q)
+{
+	void __iomem *base = q->iobase;
+	u32 reg, addr_offset = 0;
+	int ret;
+
+	/* disable and unprepare clock to avoid glitch pass to controller */
+	fsl_qspi_clk_disable_unprep(q);
+
+	/* the default frequency, we will change it later if necessary. */
+	ret = clk_set_rate(q->clk, 66000000);
+	if (ret)
+		return ret;
+
+	ret = fsl_qspi_clk_prep_enable(q);
+	if (ret)
+		return ret;
+
+	/* Reset the module */
+	qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
+		    base + QUADSPI_MCR);
+	udelay(1);
+
+	/* Disable the module */
+	qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
+		    base + QUADSPI_MCR);
+
+	reg = qspi_readl(q, base + QUADSPI_SMPR);
+	qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
+			| QUADSPI_SMPR_FSPHS_MASK
+			| QUADSPI_SMPR_HSENA_MASK
+			| QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
+
+	/* We only use the buffer3 for AHB read */
+	qspi_writel(q, 0, base + QUADSPI_BUF0IND);
+	qspi_writel(q, 0, base + QUADSPI_BUF1IND);
+	qspi_writel(q, 0, base + QUADSPI_BUF2IND);
+
+	qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
+		    q->iobase + QUADSPI_BFGENCR);
+	qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
+	qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
+		    QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
+		    base + QUADSPI_BUF3CR);
+
+	if (needs_amba_base_offset(q))
+		addr_offset = q->memmap_phy;
+
+	/*
+	 * In HW there can be a maximum of four chips on two buses with
+	 * two chip selects on each bus. We use four chip selects in SW
+	 * to differentiate between the four chips.
+	 * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
+	 * SFB2AD accordingly.
+	 */
+	qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
+		    base + QUADSPI_SFA1AD);
+	qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
+		    base + QUADSPI_SFA2AD);
+	qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
+		    base + QUADSPI_SFB1AD);
+	qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
+		    base + QUADSPI_SFB2AD);
+
+	q->selected = -1;
+
+	/* Enable the module */
+	qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
+		    base + QUADSPI_MCR);
+
+	/* clear all interrupt status */
+	qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
+
+	/* enable the interrupt */
+	qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
+
+	return 0;
+}
+
+static const char *fsl_qspi_get_name(struct spi_mem *mem)
+{
+	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
+	struct device *dev = &mem->spi->dev;
+	const char *name;
+
+	/*
+	 * In order to keep mtdparts compatible with the old MTD driver at
+	 * mtd/spi-nor/fsl-quadspi.c, we set a custom name derived from the
+	 * platform_device of the controller.
+	 */
+	if (of_get_available_child_count(q->dev->of_node) == 1)
+		return dev_name(q->dev);
+
+	name = devm_kasprintf(dev, GFP_KERNEL,
+			      "%s-%d", dev_name(q->dev),
+			      mem->spi->chip_select);
+
+	if (!name) {
+		dev_err(dev, "failed to get memory for custom flash name\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	return name;
+}
+
+static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
+	.adjust_op_size = fsl_qspi_adjust_op_size,
+	.supports_op = fsl_qspi_supports_op,
+	.exec_op = fsl_qspi_exec_op,
+	.get_name = fsl_qspi_get_name,
+};
+
+static int fsl_qspi_probe(struct platform_device *pdev)
+{
+	struct spi_controller *ctlr;
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct resource *res;
+	struct fsl_qspi *q;
+	int ret;
+
+	ctlr = spi_alloc_master(&pdev->dev, sizeof(*q));
+	if (!ctlr)
+		return -ENOMEM;
+
+	ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
+			  SPI_TX_DUAL | SPI_TX_QUAD;
+
+	q = spi_controller_get_devdata(ctlr);
+	q->dev = dev;
+	q->devtype_data = of_device_get_match_data(dev);
+	if (!q->devtype_data) {
+		ret = -ENODEV;
+		goto err_put_ctrl;
+	}
+
+	platform_set_drvdata(pdev, q);
+
+	/* find the resources */
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
+	q->iobase = devm_ioremap_resource(dev, res);
+	if (IS_ERR(q->iobase)) {
+		ret = PTR_ERR(q->iobase);
+		goto err_put_ctrl;
+	}
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+					"QuadSPI-memory");
+	q->ahb_addr = devm_ioremap_resource(dev, res);
+	if (IS_ERR(q->ahb_addr)) {
+		ret = PTR_ERR(q->ahb_addr);
+		goto err_put_ctrl;
+	}
+
+	q->memmap_phy = res->start;
+
+	/* find the clocks */
+	q->clk_en = devm_clk_get(dev, "qspi_en");
+	if (IS_ERR(q->clk_en)) {
+		ret = PTR_ERR(q->clk_en);
+		goto err_put_ctrl;
+	}
+
+	q->clk = devm_clk_get(dev, "qspi");
+	if (IS_ERR(q->clk)) {
+		ret = PTR_ERR(q->clk);
+		goto err_put_ctrl;
+	}
+
+	ret = fsl_qspi_clk_prep_enable(q);
+	if (ret) {
+		dev_err(dev, "can not enable the clock\n");
+		goto err_put_ctrl;
+	}
+
+	/* find the irq */
+	ret = platform_get_irq(pdev, 0);
+	if (ret < 0) {
+		dev_err(dev, "failed to get the irq: %d\n", ret);
+		goto err_disable_clk;
+	}
+
+	ret = devm_request_irq(dev, ret,
+			fsl_qspi_irq_handler, 0, pdev->name, q);
+	if (ret) {
+		dev_err(dev, "failed to request irq: %d\n", ret);
+		goto err_disable_clk;
+	}
+
+	mutex_init(&q->lock);
+
+	ctlr->bus_num = -1;
+	ctlr->num_chipselect = 4;
+	ctlr->mem_ops = &fsl_qspi_mem_ops;
+
+	fsl_qspi_default_setup(q);
+
+	ctlr->dev.of_node = np;
+
+	ret = spi_register_controller(ctlr);
+	if (ret)
+		goto err_destroy_mutex;
+
+	return 0;
+
+err_destroy_mutex:
+	mutex_destroy(&q->lock);
+
+err_disable_clk:
+	fsl_qspi_clk_disable_unprep(q);
+
+err_put_ctrl:
+	spi_controller_put(ctlr);
+
+	dev_err(dev, "Freescale QuadSPI probe failed\n");
+	return ret;
+}
+
+static int fsl_qspi_remove(struct platform_device *pdev)
+{
+	struct fsl_qspi *q = platform_get_drvdata(pdev);
+
+	/* disable the hardware */
+	qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
+	qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
+
+	fsl_qspi_clk_disable_unprep(q);
+
+	mutex_destroy(&q->lock);
+
+	return 0;
+}
+
+static int fsl_qspi_suspend(struct device *dev)
+{
+	return 0;
+}
+
+static int fsl_qspi_resume(struct device *dev)
+{
+	struct fsl_qspi *q = dev_get_drvdata(dev);
+
+	fsl_qspi_default_setup(q);
+
+	return 0;
+}
+
+static const struct of_device_id fsl_qspi_dt_ids[] = {
+	{ .compatible = "fsl,vf610-qspi", .data = &vybrid_data, },
+	{ .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, },
+	{ .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, },
+	{ .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
+	{ .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, },
+	{ .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
+
+static const struct dev_pm_ops fsl_qspi_pm_ops = {
+	.suspend	= fsl_qspi_suspend,
+	.resume		= fsl_qspi_resume,
+};
+
+static struct platform_driver fsl_qspi_driver = {
+	.driver = {
+		.name	= "fsl-quadspi",
+		.of_match_table = fsl_qspi_dt_ids,
+		.pm =   &fsl_qspi_pm_ops,
+	},
+	.probe          = fsl_qspi_probe,
+	.remove		= fsl_qspi_remove,
+};
+module_platform_driver(fsl_qspi_driver);
+
+MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
+MODULE_AUTHOR("Freescale Semiconductor Inc.");
+MODULE_AUTHOR("Boris Brezillion <boris.brezillon@bootlin.com>");
+MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>");
+MODULE_AUTHOR("Yogesh Gaur <yogeshnarayan.gaur@nxp.com>");
+MODULE_AUTHOR("Suresh Gupta <suresh.gupta@nxp.com>");
+MODULE_LICENSE("GPL v2");
-- 
2.7.4

RE: [PATCH v7 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

Hi,

Verified patch on LS1088ardb this board is having two connected flash slave devices on CS0 and CS1.

Verified with simple Read/Write/Erase operations along with JFFS2 mounting and booting from flash MTD partition for both slave devices.

> -----Original Message-----
> From: Schrempf Frieder [mailto:frieder.schrempf@kontron.de]
> Sent: Tuesday, December 4, 2018 7:45 PM
> To: linux-mtd@lists.infradead.org; boris.brezillon@bootlin.com; linux-
> spi@vger.kernel.org; Marek Vasut <marek.vasut@gmail.com>; Mark Brown
> <broonie@kernel.org>; Han Xu <han.xu@nxp.com>
> Cc: dwmw2@infradead.org; computersforpeace@gmail.com; richard@nod.at;
> miquel.raynal@bootlin.com; David Wolfe <david.wolfe@nxp.com>; Fabio
> Estevam <fabio.estevam@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Yogesh Narayan Gaur
> <yogeshnarayan.gaur@nxp.com>; shawnguo@kernel.org; Schrempf Frieder
> <frieder.schrempf@kontron.de>; linux-kernel@vger.kernel.org
> Subject: [PATCH v7 3/9] spi: Add a driver for the Freescale/NXP QuadSPI
> controller
> 
> From: Frieder Schrempf <frieder.schrempf@kontron.de>
> 
> This driver is derived from the SPI NOR driver at mtd/spi-nor/fsl-quadspi.c. It
> uses the new SPI memory interface of the SPI framework to issue flash memory
> operations to up to four connected flash chips (2 buses with 2 CS each).
> 
> The controller does not support generic SPI messages.
> 
> This patch also disables the build of the "old" driver and reuses its Kconfig option
> CONFIG_SPI_FSL_QUADSPI to replace it.
> 
> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Tested-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>

--
Thanks
Yogesh Gaur

> ---
>  drivers/mtd/spi-nor/Kconfig  |   9 -
>  drivers/mtd/spi-nor/Makefile |   1 -
>  drivers/spi/Kconfig          |  11 +
>  drivers/spi/Makefile         |   1 +
>  drivers/spi/spi-fsl-qspi.c   | 966 ++++++++++++++++++++++++++++++++++++++
>  5 files changed, 978 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index
> 6cc9c92..d1ca307 100644
> --- a/drivers/mtd/spi-nor/Kconfig
> +++ b/drivers/mtd/spi-nor/Kconfig
> @@ -59,15 +59,6 @@ config SPI_CADENCE_QUADSPI
>  	  device with a Cadence QSPI controller and want to access the
>  	  Flash as an MTD device.
> 
> -config SPI_FSL_QUADSPI
> -	tristate "Freescale Quad SPI controller"
> -	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE ||
> COMPILE_TEST
> -	depends on HAS_IOMEM
> -	help
> -	  This enables support for the Quad SPI controller in master mode.
> -	  This controller does not support generic SPI. It only supports
> -	  SPI NOR.
> -
>  config SPI_HISI_SFC
>  	tristate "Hisilicon SPI-NOR Flash Controller(SFC)"
>  	depends on ARCH_HISI || COMPILE_TEST
> diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index
> f4c61d2..3f160c2e3 100644
> --- a/drivers/mtd/spi-nor/Makefile
> +++ b/drivers/mtd/spi-nor/Makefile
> @@ -3,7 +3,6 @@ obj-$(CONFIG_MTD_SPI_NOR)	+= spi-nor.o
>  obj-$(CONFIG_SPI_ASPEED_SMC)	+= aspeed-smc.o
>  obj-$(CONFIG_SPI_ATMEL_QUADSPI)	+= atmel-quadspi.o
>  obj-$(CONFIG_SPI_CADENCE_QUADSPI)	+= cadence-quadspi.o
> -obj-$(CONFIG_SPI_FSL_QUADSPI)	+= fsl-quadspi.o
>  obj-$(CONFIG_SPI_HISI_SFC)	+= hisi-sfc.o
>  obj-$(CONFIG_MTD_MT81xx_NOR)    += mtk-quadspi.o
>  obj-$(CONFIG_SPI_NXP_SPIFI)	+= nxp-spifi.o
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 7d3a5c9..8c84186
> 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -259,6 +259,17 @@ config SPI_FSL_LPSPI
>  	help
>  	  This enables Freescale i.MX LPSPI controllers in master mode.
> 
> +config SPI_FSL_QUADSPI
> +	tristate "Freescale QSPI controller"
> +	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE ||
> COMPILE_TEST
> +	depends on HAS_IOMEM
> +	help
> +	  This enables support for the Quad SPI controller in master mode.
> +	  Up to four flash chips can be connected on two buses with two
> +	  chipselects each.
> +	  This controller does not support generic SPI messages. It only
> +	  supports the high-level SPI memory interface.
> +
>  config SPI_GPIO
>  	tristate "GPIO-based bitbanging SPI Master"
>  	depends on GPIOLIB || COMPILE_TEST
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 3575205..5377e61
> 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -44,6 +44,7 @@ obj-$(CONFIG_SPI_FSL_DSPI)		+= spi-fsl-
> dspi.o
>  obj-$(CONFIG_SPI_FSL_LIB)		+= spi-fsl-lib.o
>  obj-$(CONFIG_SPI_FSL_ESPI)		+= spi-fsl-espi.o
>  obj-$(CONFIG_SPI_FSL_LPSPI)		+= spi-fsl-lpspi.o
> +obj-$(CONFIG_SPI_FSL_QUADSPI)		+= spi-fsl-qspi.o
>  obj-$(CONFIG_SPI_FSL_SPI)		+= spi-fsl-spi.o
>  obj-$(CONFIG_SPI_GPIO)			+= spi-gpio.o
>  obj-$(CONFIG_SPI_IMG_SPFI)		+= spi-img-spfi.o
> diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c new file mode
> 100644 index 0000000..f0a3400
> --- /dev/null
> +++ b/drivers/spi/spi-fsl-qspi.c
> @@ -0,0 +1,966 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +/*
> + * Freescale QuadSPI driver.
> + *
> + * Copyright (C) 2013 Freescale Semiconductor, Inc.
> + * Copyright (C) 2018 Bootlin
> + * Copyright (C) 2018 exceet electronics GmbH
> + * Copyright (C) 2018 Kontron Electronics GmbH
> + *
> + * Transition to SPI MEM interface:
> + * Authors:
> + *     Boris Brezillion <boris.brezillon@bootlin.com>
> + *     Frieder Schrempf <frieder.schrempf@kontron.de>
> + *     Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> + *     Suresh Gupta <suresh.gupta@nxp.com>
> + *
> + * Based on the original fsl-quadspi.c spi-nor driver:
> + * Author: Freescale Semiconductor, Inc.
> + *
> + */
> +
> +#include <linux/bitops.h>
> +#include <linux/clk.h>
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/errno.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/jiffies.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_qos.h>
> +#include <linux/sizes.h>
> +
> +#include <linux/spi/spi.h>
> +#include <linux/spi/spi-mem.h>
> +
> +/*
> + * The driver only uses one single LUT entry, that is updated on
> + * each call of exec_op(). Index 0 is preset at boot with a basic
> + * read operation, so let's use the last entry (15).
> + */
> +#define	SEQID_LUT			15
> +
> +/* Registers used by the driver */
> +#define QUADSPI_MCR			0x00
> +#define QUADSPI_MCR_RESERVED_MASK	GENMASK(19, 16)
> +#define QUADSPI_MCR_MDIS_MASK		BIT(14)
> +#define QUADSPI_MCR_CLR_TXF_MASK	BIT(11)
> +#define QUADSPI_MCR_CLR_RXF_MASK	BIT(10)
> +#define QUADSPI_MCR_DDR_EN_MASK		BIT(7)
> +#define QUADSPI_MCR_END_CFG_MASK	GENMASK(3, 2)
> +#define QUADSPI_MCR_SWRSTHD_MASK	BIT(1)
> +#define QUADSPI_MCR_SWRSTSD_MASK	BIT(0)
> +
> +#define QUADSPI_IPCR			0x08
> +#define QUADSPI_IPCR_SEQID(x)		((x) << 24)
> +
> +#define QUADSPI_BUF3CR			0x1c
> +#define QUADSPI_BUF3CR_ALLMST_MASK	BIT(31)
> +#define QUADSPI_BUF3CR_ADATSZ(x)	((x) << 8)
> +#define QUADSPI_BUF3CR_ADATSZ_MASK	GENMASK(15, 8)
> +
> +#define QUADSPI_BFGENCR			0x20
> +#define QUADSPI_BFGENCR_SEQID(x)	((x) << 12)
> +
> +#define QUADSPI_BUF0IND			0x30
> +#define QUADSPI_BUF1IND			0x34
> +#define QUADSPI_BUF2IND			0x38
> +#define QUADSPI_SFAR			0x100
> +
> +#define QUADSPI_SMPR			0x108
> +#define QUADSPI_SMPR_DDRSMP_MASK	GENMASK(18, 16)
> +#define QUADSPI_SMPR_FSDLY_MASK		BIT(6)
> +#define QUADSPI_SMPR_FSPHS_MASK		BIT(5)
> +#define QUADSPI_SMPR_HSENA_MASK		BIT(0)
> +
> +#define QUADSPI_RBCT			0x110
> +#define QUADSPI_RBCT_WMRK_MASK		GENMASK(4, 0)
> +#define QUADSPI_RBCT_RXBRD_USEIPS	BIT(8)
> +
> +#define QUADSPI_TBDR			0x154
> +
> +#define QUADSPI_SR			0x15c
> +#define QUADSPI_SR_IP_ACC_MASK		BIT(1)
> +#define QUADSPI_SR_AHB_ACC_MASK		BIT(2)
> +
> +#define QUADSPI_FR			0x160
> +#define QUADSPI_FR_TFF_MASK		BIT(0)
> +
> +#define QUADSPI_SPTRCLR			0x16c
> +#define QUADSPI_SPTRCLR_IPPTRC		BIT(8)
> +#define QUADSPI_SPTRCLR_BFPTRC		BIT(0)
> +
> +#define QUADSPI_SFA1AD			0x180
> +#define QUADSPI_SFA2AD			0x184
> +#define QUADSPI_SFB1AD			0x188
> +#define QUADSPI_SFB2AD			0x18c
> +#define QUADSPI_RBDR(x)			(0x200 + ((x) * 4))
> +
> +#define QUADSPI_LUTKEY			0x300
> +#define QUADSPI_LUTKEY_VALUE		0x5AF05AF0
> +
> +#define QUADSPI_LCKCR			0x304
> +#define QUADSPI_LCKER_LOCK		BIT(0)
> +#define QUADSPI_LCKER_UNLOCK		BIT(1)
> +
> +#define QUADSPI_RSER			0x164
> +#define QUADSPI_RSER_TFIE		BIT(0)
> +
> +#define QUADSPI_LUT_BASE		0x310
> +#define QUADSPI_LUT_OFFSET		(SEQID_LUT * 4 * 4)
> +#define QUADSPI_LUT_REG(idx) \
> +	(QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
> +
> +/* Instruction set for the LUT register */
> +#define LUT_STOP		0
> +#define LUT_CMD			1
> +#define LUT_ADDR		2
> +#define LUT_DUMMY		3
> +#define LUT_MODE		4
> +#define LUT_MODE2		5
> +#define LUT_MODE4		6
> +#define LUT_FSL_READ		7
> +#define LUT_FSL_WRITE		8
> +#define LUT_JMP_ON_CS		9
> +#define LUT_ADDR_DDR		10
> +#define LUT_MODE_DDR		11
> +#define LUT_MODE2_DDR		12
> +#define LUT_MODE4_DDR		13
> +#define LUT_FSL_READ_DDR	14
> +#define LUT_FSL_WRITE_DDR	15
> +#define LUT_DATA_LEARN		16
> +
> +/*
> + * The PAD definitions for LUT register.
> + *
> + * The pad stands for the number of IO lines [0:3].
> + * For example, the quad read needs four IO lines,
> + * so you should use LUT_PAD(4).
> + */
> +#define LUT_PAD(x) (fls(x) - 1)
> +
> +/*
> + * Macro for constructing the LUT entries with the following
> + * register layout:
> + *
> + *  ---------------------------------------------------
> + *  | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
> + *  ---------------------------------------------------
> + */
> +#define LUT_DEF(idx, ins, pad, opr)					\
> +	((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
> +
> +/* Controller needs driver to swap endianness */
> +#define QUADSPI_QUIRK_SWAP_ENDIAN	BIT(0)
> +
> +/* Controller needs 4x internal clock */
> +#define QUADSPI_QUIRK_4X_INT_CLK	BIT(1)
> +
> +/*
> + * TKT253890, the controller needs the driver to fill the txfifo with
> + * 16 bytes at least to trigger a data transfer, even though the extra
> + * data won't be transferred.
> + */
> +#define QUADSPI_QUIRK_TKT253890		BIT(2)
> +
> +/* TKT245618, the controller cannot wake up from wait mode */
> +#define QUADSPI_QUIRK_TKT245618		BIT(3)
> +
> +/*
> + * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
> + * internally. No need to add it when setting SFXXAD and SFAR registers
> +*/
> +#define QUADSPI_QUIRK_BASE_INTERNAL	BIT(4)
> +
> +struct fsl_qspi_devtype_data {
> +	unsigned int rxfifo;
> +	unsigned int txfifo;
> +	unsigned int ahb_buf_size;
> +	unsigned int quirks;
> +	bool little_endian;
> +};
> +
> +static const struct fsl_qspi_devtype_data vybrid_data = {
> +	.rxfifo = SZ_128,
> +	.txfifo = SZ_64,
> +	.ahb_buf_size = SZ_1K,
> +	.quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
> +	.little_endian = true,
> +};
> +
> +static const struct fsl_qspi_devtype_data imx6sx_data = {
> +	.rxfifo = SZ_128,
> +	.txfifo = SZ_512,
> +	.ahb_buf_size = SZ_1K,
> +	.quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
> +	.little_endian = true,
> +};
> +
> +static const struct fsl_qspi_devtype_data imx7d_data = {
> +	.rxfifo = SZ_512,
> +	.txfifo = SZ_512,
> +	.ahb_buf_size = SZ_1K,
> +	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
> +	.little_endian = true,
> +};
> +
> +static const struct fsl_qspi_devtype_data imx6ul_data = {
> +	.rxfifo = SZ_128,
> +	.txfifo = SZ_512,
> +	.ahb_buf_size = SZ_1K,
> +	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
> +	.little_endian = true,
> +};
> +
> +static const struct fsl_qspi_devtype_data ls1021a_data = {
> +	.rxfifo = SZ_128,
> +	.txfifo = SZ_64,
> +	.ahb_buf_size = SZ_1K,
> +	.quirks = 0,
> +	.little_endian = false,
> +};
> +
> +static const struct fsl_qspi_devtype_data ls2080a_data = {
> +	.rxfifo = SZ_128,
> +	.txfifo = SZ_64,
> +	.ahb_buf_size = SZ_1K,
> +	.quirks = QUADSPI_QUIRK_TKT253890 |
> QUADSPI_QUIRK_BASE_INTERNAL,
> +	.little_endian = true,
> +};
> +
> +struct fsl_qspi {
> +	void __iomem *iobase;
> +	void __iomem *ahb_addr;
> +	u32 memmap_phy;
> +	struct clk *clk, *clk_en;
> +	struct device *dev;
> +	struct completion c;
> +	const struct fsl_qspi_devtype_data *devtype_data;
> +	struct mutex lock;
> +	struct pm_qos_request pm_qos_req;
> +	int selected;
> +};
> +
> +static inline int needs_swap_endian(struct fsl_qspi *q) {
> +	return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN; }
> +
> +static inline int needs_4x_clock(struct fsl_qspi *q) {
> +	return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK; }
> +
> +static inline int needs_fill_txfifo(struct fsl_qspi *q) {
> +	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890; }
> +
> +static inline int needs_wakeup_wait_mode(struct fsl_qspi *q) {
> +	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618; }
> +
> +static inline int needs_amba_base_offset(struct fsl_qspi *q) {
> +	return !(q->devtype_data->quirks &
> QUADSPI_QUIRK_BASE_INTERNAL); }
> +
> +/*
> + * An IC bug makes it necessary to rearrange the 32-bit data.
> + * Later chips, such as IMX6SLX, have fixed this bug.
> + */
> +static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a) {
> +	return needs_swap_endian(q) ? __swab32(a) : a; }
> +
> +/*
> + * R/W functions for big- or little-endian registers:
> + * The QSPI controller's endianness is independent of
> + * the CPU core's endianness. So far, although the CPU
> + * core is little-endian the QSPI controller can use
> + * big-endian or little-endian.
> + */
> +static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem
> +*addr) {
> +	if (q->devtype_data->little_endian)
> +		iowrite32(val, addr);
> +	else
> +		iowrite32be(val, addr);
> +}
> +
> +static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr) {
> +	if (q->devtype_data->little_endian)
> +		return ioread32(addr);
> +
> +	return ioread32be(addr);
> +}
> +
> +static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id) {
> +	struct fsl_qspi *q = dev_id;
> +	u32 reg;
> +
> +	/* clear interrupt */
> +	reg = qspi_readl(q, q->iobase + QUADSPI_FR);
> +	qspi_writel(q, reg, q->iobase + QUADSPI_FR);
> +
> +	if (reg & QUADSPI_FR_TFF_MASK)
> +		complete(&q->c);
> +
> +	dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg);
> +	return IRQ_HANDLED;
> +}
> +
> +static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width) {
> +	switch (width) {
> +	case 1:
> +	case 2:
> +	case 4:
> +		return 0;
> +	}
> +
> +	return -ENOTSUPP;
> +}
> +
> +static bool fsl_qspi_supports_op(struct spi_mem *mem,
> +				 const struct spi_mem_op *op)
> +{
> +	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
> +	int ret;
> +
> +	ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
> +
> +	if (op->addr.nbytes)
> +		ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
> +
> +	if (op->dummy.nbytes)
> +		ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
> +
> +	if (op->data.nbytes)
> +		ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
> +
> +	if (ret)
> +		return false;
> +
> +	/*
> +	 * The number of instructions needed for the op, needs
> +	 * to fit into a single LUT entry.
> +	 */
> +	if (op->addr.nbytes +
> +	   (op->dummy.nbytes ? 1:0) +
> +	   (op->data.nbytes ? 1:0) > 6)
> +		return false;
> +
> +	/* Max 64 dummy clock cycles supported */
> +	if (op->dummy.nbytes &&
> +	    (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
> +		return false;
> +
> +	/* Max data length, check controller limits and alignment */
> +	if (op->data.dir == SPI_MEM_DATA_IN &&
> +	    (op->data.nbytes > q->devtype_data->ahb_buf_size ||
> +	     (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
> +	      !IS_ALIGNED(op->data.nbytes, 8))))
> +		return false;
> +
> +	if (op->data.dir == SPI_MEM_DATA_OUT &&
> +	    op->data.nbytes > q->devtype_data->txfifo)
> +		return false;
> +
> +	return true;
> +}
> +
> +static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
> +				 const struct spi_mem_op *op)
> +{
> +	void __iomem *base = q->iobase;
> +	u32 lutval[4] = {};
> +	int lutidx = 1, i;
> +
> +	lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
> +			     op->cmd.opcode);
> +
> +	/*
> +	 * For some unknown reason, using LUT_ADDR doesn't work in some
> +	 * cases (at least with only one byte long addresses), so
> +	 * let's use LUT_MODE to write the address bytes one by one
> +	 */
> +	for (i = 0; i < op->addr.nbytes; i++) {
> +		u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
> +
> +		lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
> +					      LUT_PAD(op->addr.buswidth),
> +					      addrbyte);
> +		lutidx++;
> +	}
> +
> +	if (op->dummy.nbytes) {
> +		lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
> +					      LUT_PAD(op->dummy.buswidth),
> +					      op->dummy.nbytes * 8 /
> +					      op->dummy.buswidth);
> +		lutidx++;
> +	}
> +
> +	if (op->data.nbytes) {
> +		lutval[lutidx / 2] |= LUT_DEF(lutidx,
> +					      op->data.dir ==
> SPI_MEM_DATA_IN ?
> +					      LUT_FSL_READ : LUT_FSL_WRITE,
> +					      LUT_PAD(op->data.buswidth),
> +					      0);
> +		lutidx++;
> +	}
> +
> +	lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
> +
> +	/* unlock LUT */
> +	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
> +	qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
> +
> +	/* fill LUT */
> +	for (i = 0; i < ARRAY_SIZE(lutval); i++)
> +		qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
> +
> +	/* lock LUT */
> +	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
> +	qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); }
> +
> +static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q) {
> +	int ret;
> +
> +	ret = clk_prepare_enable(q->clk_en);
> +	if (ret)
> +		return ret;
> +
> +	ret = clk_prepare_enable(q->clk);
> +	if (ret) {
> +		clk_disable_unprepare(q->clk_en);
> +		return ret;
> +	}
> +
> +	if (needs_wakeup_wait_mode(q))
> +		pm_qos_add_request(&q->pm_qos_req,
> PM_QOS_CPU_DMA_LATENCY, 0);
> +
> +	return 0;
> +}
> +
> +static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q) {
> +	if (needs_wakeup_wait_mode(q))
> +		pm_qos_remove_request(&q->pm_qos_req);
> +
> +	clk_disable_unprepare(q->clk);
> +	clk_disable_unprepare(q->clk_en);
> +}
> +
> +/*
> + * If we have changed the content of the flash by writing or erasing,
> +or if we
> + * read from flash with a different offset into the page buffer, we
> +need to
> + * invalidate the AHB buffer. If we do not do so, we may read out the
> +wrong
> + * data. The spec tells us reset the AHB domain and Serial Flash domain
> +at
> + * the same time.
> + */
> +static void fsl_qspi_invalidate(struct fsl_qspi *q) {
> +	u32 reg;
> +
> +	reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
> +	reg |= QUADSPI_MCR_SWRSTHD_MASK |
> QUADSPI_MCR_SWRSTSD_MASK;
> +	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
> +
> +	/*
> +	 * The minimum delay : 1 AHB + 2 SFCK clocks.
> +	 * Delay 1 us is enough.
> +	 */
> +	udelay(1);
> +
> +	reg &= ~(QUADSPI_MCR_SWRSTHD_MASK |
> QUADSPI_MCR_SWRSTSD_MASK);
> +	qspi_writel(q, reg, q->iobase + QUADSPI_MCR); }
> +
> +static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device
> +*spi) {
> +	unsigned long rate = spi->max_speed_hz;
> +	int ret;
> +
> +	if (q->selected == spi->chip_select)
> +		return;
> +
> +	if (needs_4x_clock(q))
> +		rate *= 4;
> +
> +	fsl_qspi_clk_disable_unprep(q);
> +
> +	ret = clk_set_rate(q->clk, rate);
> +	if (ret)
> +		return;
> +
> +	ret = fsl_qspi_clk_prep_enable(q);
> +	if (ret)
> +		return;
> +
> +	q->selected = spi->chip_select;
> +
> +	fsl_qspi_invalidate(q);
> +}
> +
> +static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct
> +spi_mem_op *op) {
> +	memcpy_fromio(op->data.buf.in,
> +		      q->ahb_addr + q->selected * q->devtype_data-
> >ahb_buf_size,
> +		      op->data.nbytes);
> +}
> +
> +static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
> +				 const struct spi_mem_op *op)
> +{
> +	void __iomem *base = q->iobase;
> +	int i;
> +	u32 val;
> +
> +	for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
> +		memcpy(&val, op->data.buf.out + i, 4);
> +		val = fsl_qspi_endian_xchg(q, val);
> +		qspi_writel(q, val, base + QUADSPI_TBDR);
> +	}
> +
> +	if (i < op->data.nbytes) {
> +		memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
> +		val = fsl_qspi_endian_xchg(q, val);
> +		qspi_writel(q, val, base + QUADSPI_TBDR);
> +	}
> +
> +	if (needs_fill_txfifo(q)) {
> +		for (i = op->data.nbytes; i < 16; i += 4)
> +			qspi_writel(q, 0, base + QUADSPI_TBDR);
> +	}
> +}
> +
> +static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
> +			  const struct spi_mem_op *op)
> +{
> +	void __iomem *base = q->iobase;
> +	int i;
> +	u8 *buf = op->data.buf.in;
> +	u32 val;
> +
> +	for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
> +		val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
> +		val = fsl_qspi_endian_xchg(q, val);
> +		memcpy(buf + i, &val, 4);
> +	}
> +
> +	if (i < op->data.nbytes) {
> +		val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
> +		val = fsl_qspi_endian_xchg(q, val);
> +		memcpy(buf + i, &val, op->data.nbytes - i);
> +	}
> +}
> +
> +static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op
> +*op) {
> +	void __iomem *base = q->iobase;
> +	int err = 0;
> +
> +	init_completion(&q->c);
> +
> +	/*
> +	 * Always start the sequence at the same index since we update
> +	 * the LUT at each exec_op() call. And also specify the DATA
> +	 * length, since it's has not been specified in the LUT.
> +	 */
> +	qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
> +		    base + QUADSPI_IPCR);
> +
> +	/* Wait for the interrupt. */
> +	if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000)))
> +		err = -ETIMEDOUT;
> +
> +	if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
> +		fsl_qspi_read_rxfifo(q, op);
> +
> +	return err;
> +}
> +
> +static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
> +				    u32 mask, u32 delay_us, u32 timeout_us) {
> +	u32 reg;
> +
> +	if (!q->devtype_data->little_endian)
> +		mask = (u32)cpu_to_be32(mask);
> +
> +	return readl_poll_timeout(base, reg, !(reg & mask), delay_us,
> +				  timeout_us);
> +}
> +
> +static int fsl_qspi_exec_op(struct spi_mem *mem, const struct
> +spi_mem_op *op) {
> +	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
> +	void __iomem *base = q->iobase;
> +	u32 addr_offset = 0;
> +	int err = 0;
> +
> +	mutex_lock(&q->lock);
> +
> +	/* wait for the controller being ready */
> +	fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR,
> (QUADSPI_SR_IP_ACC_MASK |
> +				 QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
> +
> +	fsl_qspi_select_mem(q, mem->spi);
> +
> +	if (needs_amba_base_offset(q))
> +		addr_offset = q->memmap_phy;
> +
> +	qspi_writel(q,
> +		    q->selected * q->devtype_data->ahb_buf_size + addr_offset,
> +		    base + QUADSPI_SFAR);
> +
> +	qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
> +		    QUADSPI_MCR_CLR_RXF_MASK |
> QUADSPI_MCR_CLR_TXF_MASK,
> +		    base + QUADSPI_MCR);
> +
> +	qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
> +		    base + QUADSPI_SPTRCLR);
> +
> +	fsl_qspi_prepare_lut(q, op);
> +
> +	/*
> +	 * If we have large chunks of data, we read them through the AHB bus
> +	 * by accessing the mapped memory. In all other cases we use
> +	 * IP commands to access the flash.
> +	 */
> +	if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
> +	    op->data.dir == SPI_MEM_DATA_IN) {
> +		fsl_qspi_read_ahb(q, op);
> +	} else {
> +		qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
> +			    QUADSPI_RBCT_RXBRD_USEIPS, base +
> QUADSPI_RBCT);
> +
> +		if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
> +			fsl_qspi_fill_txfifo(q, op);
> +
> +		err = fsl_qspi_do_op(q, op);
> +	}
> +
> +	/* Invalidate the data in the AHB buffer. */
> +	fsl_qspi_invalidate(q);
> +
> +	mutex_unlock(&q->lock);
> +
> +	return err;
> +}
> +
> +static int fsl_qspi_adjust_op_size(struct spi_mem *mem, struct
> +spi_mem_op *op) {
> +	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
> +
> +	if (op->data.dir == SPI_MEM_DATA_OUT) {
> +		if (op->data.nbytes > q->devtype_data->txfifo)
> +			op->data.nbytes = q->devtype_data->txfifo;
> +	} else {
> +		if (op->data.nbytes > q->devtype_data->ahb_buf_size)
> +			op->data.nbytes = q->devtype_data->ahb_buf_size;
> +		else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
> +			op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
> +	}
> +
> +	return 0;
> +}
> +
> +static int fsl_qspi_default_setup(struct fsl_qspi *q) {
> +	void __iomem *base = q->iobase;
> +	u32 reg, addr_offset = 0;
> +	int ret;
> +
> +	/* disable and unprepare clock to avoid glitch pass to controller */
> +	fsl_qspi_clk_disable_unprep(q);
> +
> +	/* the default frequency, we will change it later if necessary. */
> +	ret = clk_set_rate(q->clk, 66000000);
> +	if (ret)
> +		return ret;
> +
> +	ret = fsl_qspi_clk_prep_enable(q);
> +	if (ret)
> +		return ret;
> +
> +	/* Reset the module */
> +	qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK |
> QUADSPI_MCR_SWRSTHD_MASK,
> +		    base + QUADSPI_MCR);
> +	udelay(1);
> +
> +	/* Disable the module */
> +	qspi_writel(q, QUADSPI_MCR_MDIS_MASK |
> QUADSPI_MCR_RESERVED_MASK,
> +		    base + QUADSPI_MCR);
> +
> +	reg = qspi_readl(q, base + QUADSPI_SMPR);
> +	qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
> +			| QUADSPI_SMPR_FSPHS_MASK
> +			| QUADSPI_SMPR_HSENA_MASK
> +			| QUADSPI_SMPR_DDRSMP_MASK), base +
> QUADSPI_SMPR);
> +
> +	/* We only use the buffer3 for AHB read */
> +	qspi_writel(q, 0, base + QUADSPI_BUF0IND);
> +	qspi_writel(q, 0, base + QUADSPI_BUF1IND);
> +	qspi_writel(q, 0, base + QUADSPI_BUF2IND);
> +
> +	qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
> +		    q->iobase + QUADSPI_BFGENCR);
> +	qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
> +	qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
> +		    QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size /
> 8),
> +		    base + QUADSPI_BUF3CR);
> +
> +	if (needs_amba_base_offset(q))
> +		addr_offset = q->memmap_phy;
> +
> +	/*
> +	 * In HW there can be a maximum of four chips on two buses with
> +	 * two chip selects on each bus. We use four chip selects in SW
> +	 * to differentiate between the four chips.
> +	 * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
> +	 * SFB2AD accordingly.
> +	 */
> +	qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
> +		    base + QUADSPI_SFA1AD);
> +	qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
> +		    base + QUADSPI_SFA2AD);
> +	qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
> +		    base + QUADSPI_SFB1AD);
> +	qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
> +		    base + QUADSPI_SFB2AD);
> +
> +	q->selected = -1;
> +
> +	/* Enable the module */
> +	qspi_writel(q, QUADSPI_MCR_RESERVED_MASK |
> QUADSPI_MCR_END_CFG_MASK,
> +		    base + QUADSPI_MCR);
> +
> +	/* clear all interrupt status */
> +	qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
> +
> +	/* enable the interrupt */
> +	qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
> +
> +	return 0;
> +}
> +
> +static const char *fsl_qspi_get_name(struct spi_mem *mem) {
> +	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
> +	struct device *dev = &mem->spi->dev;
> +	const char *name;
> +
> +	/*
> +	 * In order to keep mtdparts compatible with the old MTD driver at
> +	 * mtd/spi-nor/fsl-quadspi.c, we set a custom name derived from the
> +	 * platform_device of the controller.
> +	 */
> +	if (of_get_available_child_count(q->dev->of_node) == 1)
> +		return dev_name(q->dev);
> +
> +	name = devm_kasprintf(dev, GFP_KERNEL,
> +			      "%s-%d", dev_name(q->dev),
> +			      mem->spi->chip_select);
> +
> +	if (!name) {
> +		dev_err(dev, "failed to get memory for custom flash name\n");
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> +	return name;
> +}
> +
> +static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
> +	.adjust_op_size = fsl_qspi_adjust_op_size,
> +	.supports_op = fsl_qspi_supports_op,
> +	.exec_op = fsl_qspi_exec_op,
> +	.get_name = fsl_qspi_get_name,
> +};
> +
> +static int fsl_qspi_probe(struct platform_device *pdev) {
> +	struct spi_controller *ctlr;
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
> +	struct resource *res;
> +	struct fsl_qspi *q;
> +	int ret;
> +
> +	ctlr = spi_alloc_master(&pdev->dev, sizeof(*q));
> +	if (!ctlr)
> +		return -ENOMEM;
> +
> +	ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
> +			  SPI_TX_DUAL | SPI_TX_QUAD;
> +
> +	q = spi_controller_get_devdata(ctlr);
> +	q->dev = dev;
> +	q->devtype_data = of_device_get_match_data(dev);
> +	if (!q->devtype_data) {
> +		ret = -ENODEV;
> +		goto err_put_ctrl;
> +	}
> +
> +	platform_set_drvdata(pdev, q);
> +
> +	/* find the resources */
> +	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> "QuadSPI");
> +	q->iobase = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(q->iobase)) {
> +		ret = PTR_ERR(q->iobase);
> +		goto err_put_ctrl;
> +	}
> +
> +	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> +					"QuadSPI-memory");
> +	q->ahb_addr = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(q->ahb_addr)) {
> +		ret = PTR_ERR(q->ahb_addr);
> +		goto err_put_ctrl;
> +	}
> +
> +	q->memmap_phy = res->start;
> +
> +	/* find the clocks */
> +	q->clk_en = devm_clk_get(dev, "qspi_en");
> +	if (IS_ERR(q->clk_en)) {
> +		ret = PTR_ERR(q->clk_en);
> +		goto err_put_ctrl;
> +	}
> +
> +	q->clk = devm_clk_get(dev, "qspi");
> +	if (IS_ERR(q->clk)) {
> +		ret = PTR_ERR(q->clk);
> +		goto err_put_ctrl;
> +	}
> +
> +	ret = fsl_qspi_clk_prep_enable(q);
> +	if (ret) {
> +		dev_err(dev, "can not enable the clock\n");
> +		goto err_put_ctrl;
> +	}
> +
> +	/* find the irq */
> +	ret = platform_get_irq(pdev, 0);
> +	if (ret < 0) {
> +		dev_err(dev, "failed to get the irq: %d\n", ret);
> +		goto err_disable_clk;
> +	}
> +
> +	ret = devm_request_irq(dev, ret,
> +			fsl_qspi_irq_handler, 0, pdev->name, q);
> +	if (ret) {
> +		dev_err(dev, "failed to request irq: %d\n", ret);
> +		goto err_disable_clk;
> +	}
> +
> +	mutex_init(&q->lock);
> +
> +	ctlr->bus_num = -1;
> +	ctlr->num_chipselect = 4;
> +	ctlr->mem_ops = &fsl_qspi_mem_ops;
> +
> +	fsl_qspi_default_setup(q);
> +
> +	ctlr->dev.of_node = np;
> +
> +	ret = spi_register_controller(ctlr);
> +	if (ret)
> +		goto err_destroy_mutex;
> +
> +	return 0;
> +
> +err_destroy_mutex:
> +	mutex_destroy(&q->lock);
> +
> +err_disable_clk:
> +	fsl_qspi_clk_disable_unprep(q);
> +
> +err_put_ctrl:
> +	spi_controller_put(ctlr);
> +
> +	dev_err(dev, "Freescale QuadSPI probe failed\n");
> +	return ret;
> +}
> +
> +static int fsl_qspi_remove(struct platform_device *pdev) {
> +	struct fsl_qspi *q = platform_get_drvdata(pdev);
> +
> +	/* disable the hardware */
> +	qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
> +	qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
> +
> +	fsl_qspi_clk_disable_unprep(q);
> +
> +	mutex_destroy(&q->lock);
> +
> +	return 0;
> +}
> +
> +static int fsl_qspi_suspend(struct device *dev) {
> +	return 0;
> +}
> +
> +static int fsl_qspi_resume(struct device *dev) {
> +	struct fsl_qspi *q = dev_get_drvdata(dev);
> +
> +	fsl_qspi_default_setup(q);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id fsl_qspi_dt_ids[] = {
> +	{ .compatible = "fsl,vf610-qspi", .data = &vybrid_data, },
> +	{ .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, },
> +	{ .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, },
> +	{ .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
> +	{ .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, },
> +	{ .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
> +
> +static const struct dev_pm_ops fsl_qspi_pm_ops = {
> +	.suspend	= fsl_qspi_suspend,
> +	.resume		= fsl_qspi_resume,
> +};
> +
> +static struct platform_driver fsl_qspi_driver = {
> +	.driver = {
> +		.name	= "fsl-quadspi",
> +		.of_match_table = fsl_qspi_dt_ids,
> +		.pm =   &fsl_qspi_pm_ops,
> +	},
> +	.probe          = fsl_qspi_probe,
> +	.remove		= fsl_qspi_remove,
> +};
> +module_platform_driver(fsl_qspi_driver);
> +
> +MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
> +MODULE_AUTHOR("Freescale Semiconductor Inc."); MODULE_AUTHOR("Boris
> +Brezillion <boris.brezillon@bootlin.com>"); MODULE_AUTHOR("Frieder
> +Schrempf <frieder.schrempf@kontron.de>"); MODULE_AUTHOR("Yogesh Gaur
> +<yogeshnarayan.gaur@nxp.com>"); MODULE_AUTHOR("Suresh Gupta
> +<suresh.gupta@nxp.com>"); MODULE_LICENSE("GPL v2");
> --
> 2.7.4

RE: [PATCH v7 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

Hi Frieder,

> -----Original Message-----
> From: Schrempf Frieder [mailto:frieder.schrempf@kontron.de]
> Sent: Tuesday, December 4, 2018 7:45 PM
> To: linux-mtd@lists.infradead.org; boris.brezillon@bootlin.com; linux-
> spi@vger.kernel.org; Marek Vasut <marek.vasut@gmail.com>; Mark Brown
> <broonie@kernel.org>; Han Xu <han.xu@nxp.com>
> Cc: dwmw2@infradead.org; computersforpeace@gmail.com; richard@nod.at;
> miquel.raynal@bootlin.com; David Wolfe <david.wolfe@nxp.com>; Fabio
> Estevam <fabio.estevam@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Yogesh Narayan Gaur
> <yogeshnarayan.gaur@nxp.com>; shawnguo@kernel.org; Schrempf Frieder
> <frieder.schrempf@kontron.de>; linux-kernel@vger.kernel.org
> Subject: [PATCH v7 3/9] spi: Add a driver for the Freescale/NXP QuadSPI
> controller
> 
> From: Frieder Schrempf <frieder.schrempf@kontron.de>
> 
> This driver is derived from the SPI NOR driver at mtd/spi-nor/fsl-quadspi.c. It
> uses the new SPI memory interface of the SPI framework to issue flash memory
> operations to up to four connected flash chips (2 buses with 2 CS each).
> 
> The controller does not support generic SPI messages.
> 
> This patch also disables the build of the "old" driver and reuses its Kconfig option
> CONFIG_SPI_FSL_QUADSPI to replace it.
> 
> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
> ---
>  drivers/mtd/spi-nor/Kconfig  |   9 -
>  drivers/mtd/spi-nor/Makefile |   1 -
>  drivers/spi/Kconfig          |  11 +
>  drivers/spi/Makefile         |   1 +
>  drivers/spi/spi-fsl-qspi.c   | 966 ++++++++++++++++++++++++++++++++++++++
>  5 files changed, 978 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index
> 6cc9c92..d1ca307 100644
> --- a/drivers/mtd/spi-nor/Kconfig
> +++ b/drivers/mtd/spi-nor/Kconfig
> @@ -59,15 +59,6 @@ config SPI_CADENCE_QUADSPI
>  	  device with a Cadence QSPI controller and want to access the
>  	  Flash as an MTD device.
> 
> -config SPI_FSL_QUADSPI
> -	tristate "Freescale Quad SPI controller"
> -	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE ||
> COMPILE_TEST
> -	depends on HAS_IOMEM
> -	help
> -	  This enables support for the Quad SPI controller in master mode.
> -	  This controller does not support generic SPI. It only supports
> -	  SPI NOR.
> -
>  config SPI_HISI_SFC
>  	tristate "Hisilicon SPI-NOR Flash Controller(SFC)"
>  	depends on ARCH_HISI || COMPILE_TEST
> diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index
> f4c61d2..3f160c2e3 100644
> --- a/drivers/mtd/spi-nor/Makefile
> +++ b/drivers/mtd/spi-nor/Makefile
> @@ -3,7 +3,6 @@ obj-$(CONFIG_MTD_SPI_NOR)	+= spi-nor.o
>  obj-$(CONFIG_SPI_ASPEED_SMC)	+= aspeed-smc.o
>  obj-$(CONFIG_SPI_ATMEL_QUADSPI)	+= atmel-quadspi.o
>  obj-$(CONFIG_SPI_CADENCE_QUADSPI)	+= cadence-quadspi.o
> -obj-$(CONFIG_SPI_FSL_QUADSPI)	+= fsl-quadspi.o
>  obj-$(CONFIG_SPI_HISI_SFC)	+= hisi-sfc.o
>  obj-$(CONFIG_MTD_MT81xx_NOR)    += mtk-quadspi.o
>  obj-$(CONFIG_SPI_NXP_SPIFI)	+= nxp-spifi.o
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 7d3a5c9..8c84186
> 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -259,6 +259,17 @@ config SPI_FSL_LPSPI
>  	help
>  	  This enables Freescale i.MX LPSPI controllers in master mode.
> 
> +config SPI_FSL_QUADSPI
> +	tristate "Freescale QSPI controller"
> +	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE ||
> COMPILE_TEST
> +	depends on HAS_IOMEM
> +	help
> +	  This enables support for the Quad SPI controller in master mode.
> +	  Up to four flash chips can be connected on two buses with two
> +	  chipselects each.
> +	  This controller does not support generic SPI messages. It only
> +	  supports the high-level SPI memory interface.
> +
>  config SPI_GPIO
>  	tristate "GPIO-based bitbanging SPI Master"
>  	depends on GPIOLIB || COMPILE_TEST
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 3575205..5377e61
> 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -44,6 +44,7 @@ obj-$(CONFIG_SPI_FSL_DSPI)		+= spi-fsl-
> dspi.o
>  obj-$(CONFIG_SPI_FSL_LIB)		+= spi-fsl-lib.o
>  obj-$(CONFIG_SPI_FSL_ESPI)		+= spi-fsl-espi.o
>  obj-$(CONFIG_SPI_FSL_LPSPI)		+= spi-fsl-lpspi.o
> +obj-$(CONFIG_SPI_FSL_QUADSPI)		+= spi-fsl-qspi.o
>  obj-$(CONFIG_SPI_FSL_SPI)		+= spi-fsl-spi.o
>  obj-$(CONFIG_SPI_GPIO)			+= spi-gpio.o
>  obj-$(CONFIG_SPI_IMG_SPFI)		+= spi-img-spfi.o
> diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c new file mode
> 100644 index 0000000..f0a3400
> --- /dev/null
> +++ b/drivers/spi/spi-fsl-qspi.c
> @@ -0,0 +1,966 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +/*
> + * Freescale QuadSPI driver.
> + *
> + * Copyright (C) 2013 Freescale Semiconductor, Inc.
> + * Copyright (C) 2018 Bootlin
> + * Copyright (C) 2018 exceet electronics GmbH
> + * Copyright (C) 2018 Kontron Electronics GmbH
> + *
> + * Transition to SPI MEM interface:
> + * Authors:
> + *     Boris Brezillion <boris.brezillon@bootlin.com>
> + *     Frieder Schrempf <frieder.schrempf@kontron.de>
> + *     Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> + *     Suresh Gupta <suresh.gupta@nxp.com>
> + *
> + * Based on the original fsl-quadspi.c spi-nor driver:
> + * Author: Freescale Semiconductor, Inc.
> + *
> + */
> +
> +#include <linux/bitops.h>
> +#include <linux/clk.h>
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/errno.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/jiffies.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_qos.h>
> +#include <linux/sizes.h>
> +
> +#include <linux/spi/spi.h>
> +#include <linux/spi/spi-mem.h>
> +
> +/*
> + * The driver only uses one single LUT entry, that is updated on
> + * each call of exec_op(). Index 0 is preset at boot with a basic
> + * read operation, so let's use the last entry (15).
> + */
> +#define	SEQID_LUT			15
> +
> +/* Registers used by the driver */
> +#define QUADSPI_MCR			0x00
> +#define QUADSPI_MCR_RESERVED_MASK	GENMASK(19, 16)
> +#define QUADSPI_MCR_MDIS_MASK		BIT(14)
> +#define QUADSPI_MCR_CLR_TXF_MASK	BIT(11)
> +#define QUADSPI_MCR_CLR_RXF_MASK	BIT(10)
> +#define QUADSPI_MCR_DDR_EN_MASK		BIT(7)
> +#define QUADSPI_MCR_END_CFG_MASK	GENMASK(3, 2)
> +#define QUADSPI_MCR_SWRSTHD_MASK	BIT(1)
> +#define QUADSPI_MCR_SWRSTSD_MASK	BIT(0)
> +
> +#define QUADSPI_IPCR			0x08
> +#define QUADSPI_IPCR_SEQID(x)		((x) << 24)
> +
> +#define QUADSPI_BUF3CR			0x1c
> +#define QUADSPI_BUF3CR_ALLMST_MASK	BIT(31)
> +#define QUADSPI_BUF3CR_ADATSZ(x)	((x) << 8)
> +#define QUADSPI_BUF3CR_ADATSZ_MASK	GENMASK(15, 8)
> +
> +#define QUADSPI_BFGENCR			0x20
> +#define QUADSPI_BFGENCR_SEQID(x)	((x) << 12)
> +
> +#define QUADSPI_BUF0IND			0x30
> +#define QUADSPI_BUF1IND			0x34
> +#define QUADSPI_BUF2IND			0x38
> +#define QUADSPI_SFAR			0x100
> +
> +#define QUADSPI_SMPR			0x108
> +#define QUADSPI_SMPR_DDRSMP_MASK	GENMASK(18, 16)
> +#define QUADSPI_SMPR_FSDLY_MASK		BIT(6)
> +#define QUADSPI_SMPR_FSPHS_MASK		BIT(5)
> +#define QUADSPI_SMPR_HSENA_MASK		BIT(0)
> +
> +#define QUADSPI_RBCT			0x110
> +#define QUADSPI_RBCT_WMRK_MASK		GENMASK(4, 0)
> +#define QUADSPI_RBCT_RXBRD_USEIPS	BIT(8)
> +
> +#define QUADSPI_TBDR			0x154
> +
> +#define QUADSPI_SR			0x15c
> +#define QUADSPI_SR_IP_ACC_MASK		BIT(1)
> +#define QUADSPI_SR_AHB_ACC_MASK		BIT(2)
> +
> +#define QUADSPI_FR			0x160
> +#define QUADSPI_FR_TFF_MASK		BIT(0)
> +
> +#define QUADSPI_SPTRCLR			0x16c
> +#define QUADSPI_SPTRCLR_IPPTRC		BIT(8)
> +#define QUADSPI_SPTRCLR_BFPTRC		BIT(0)
> +
> +#define QUADSPI_SFA1AD			0x180
> +#define QUADSPI_SFA2AD			0x184
> +#define QUADSPI_SFB1AD			0x188
> +#define QUADSPI_SFB2AD			0x18c
> +#define QUADSPI_RBDR(x)			(0x200 + ((x) * 4))
> +
> +#define QUADSPI_LUTKEY			0x300
> +#define QUADSPI_LUTKEY_VALUE		0x5AF05AF0
> +
> +#define QUADSPI_LCKCR			0x304
> +#define QUADSPI_LCKER_LOCK		BIT(0)
> +#define QUADSPI_LCKER_UNLOCK		BIT(1)
> +
> +#define QUADSPI_RSER			0x164
> +#define QUADSPI_RSER_TFIE		BIT(0)
> +
> +#define QUADSPI_LUT_BASE		0x310
> +#define QUADSPI_LUT_OFFSET		(SEQID_LUT * 4 * 4)
> +#define QUADSPI_LUT_REG(idx) \
> +	(QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
> +
> +/* Instruction set for the LUT register */
> +#define LUT_STOP		0
> +#define LUT_CMD			1
> +#define LUT_ADDR		2
> +#define LUT_DUMMY		3
> +#define LUT_MODE		4
> +#define LUT_MODE2		5
> +#define LUT_MODE4		6
> +#define LUT_FSL_READ		7
> +#define LUT_FSL_WRITE		8
> +#define LUT_JMP_ON_CS		9
> +#define LUT_ADDR_DDR		10
> +#define LUT_MODE_DDR		11
> +#define LUT_MODE2_DDR		12
> +#define LUT_MODE4_DDR		13
> +#define LUT_FSL_READ_DDR	14
> +#define LUT_FSL_WRITE_DDR	15
> +#define LUT_DATA_LEARN		16
> +
> +/*
> + * The PAD definitions for LUT register.
> + *
> + * The pad stands for the number of IO lines [0:3].
> + * For example, the quad read needs four IO lines,
> + * so you should use LUT_PAD(4).
> + */
> +#define LUT_PAD(x) (fls(x) - 1)
> +
> +/*
> + * Macro for constructing the LUT entries with the following
> + * register layout:
> + *
> + *  ---------------------------------------------------
> + *  | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
> + *  ---------------------------------------------------
> + */
> +#define LUT_DEF(idx, ins, pad, opr)					\
> +	((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
> +
> +/* Controller needs driver to swap endianness */
> +#define QUADSPI_QUIRK_SWAP_ENDIAN	BIT(0)
> +
> +/* Controller needs 4x internal clock */
> +#define QUADSPI_QUIRK_4X_INT_CLK	BIT(1)
> +
> +/*
> + * TKT253890, the controller needs the driver to fill the txfifo with
> + * 16 bytes at least to trigger a data transfer, even though the extra
> + * data won't be transferred.
> + */
> +#define QUADSPI_QUIRK_TKT253890		BIT(2)
> +
> +/* TKT245618, the controller cannot wake up from wait mode */
> +#define QUADSPI_QUIRK_TKT245618		BIT(3)
> +
> +/*
> + * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
> + * internally. No need to add it when setting SFXXAD and SFAR registers
> +*/
> +#define QUADSPI_QUIRK_BASE_INTERNAL	BIT(4)
> +
> +struct fsl_qspi_devtype_data {
> +	unsigned int rxfifo;
> +	unsigned int txfifo;
> +	unsigned int ahb_buf_size;
> +	unsigned int quirks;
> +	bool little_endian;
> +};
> +
> +static const struct fsl_qspi_devtype_data vybrid_data = {
> +	.rxfifo = SZ_128,
> +	.txfifo = SZ_64,
> +	.ahb_buf_size = SZ_1K,
> +	.quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
> +	.little_endian = true,
> +};
> +
> +static const struct fsl_qspi_devtype_data imx6sx_data = {
> +	.rxfifo = SZ_128,
> +	.txfifo = SZ_512,
> +	.ahb_buf_size = SZ_1K,
> +	.quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
> +	.little_endian = true,
> +};
> +
> +static const struct fsl_qspi_devtype_data imx7d_data = {
> +	.rxfifo = SZ_512,
> +	.txfifo = SZ_512,
> +	.ahb_buf_size = SZ_1K,
> +	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
> +	.little_endian = true,
> +};
> +
> +static const struct fsl_qspi_devtype_data imx6ul_data = {
> +	.rxfifo = SZ_128,
> +	.txfifo = SZ_512,
> +	.ahb_buf_size = SZ_1K,
> +	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
> +	.little_endian = true,
> +};
> +
> +static const struct fsl_qspi_devtype_data ls1021a_data = {
> +	.rxfifo = SZ_128,
> +	.txfifo = SZ_64,
> +	.ahb_buf_size = SZ_1K,
> +	.quirks = 0,
> +	.little_endian = false,
> +};
> +
> +static const struct fsl_qspi_devtype_data ls2080a_data = {
> +	.rxfifo = SZ_128,
> +	.txfifo = SZ_64,
> +	.ahb_buf_size = SZ_1K,
> +	.quirks = QUADSPI_QUIRK_TKT253890 |
> QUADSPI_QUIRK_BASE_INTERNAL,
> +	.little_endian = true,
> +};
> +
> +struct fsl_qspi {
> +	void __iomem *iobase;
> +	void __iomem *ahb_addr;
> +	u32 memmap_phy;
> +	struct clk *clk, *clk_en;
> +	struct device *dev;
> +	struct completion c;
> +	const struct fsl_qspi_devtype_data *devtype_data;
> +	struct mutex lock;
> +	struct pm_qos_request pm_qos_req;
> +	int selected;
> +};
> +
> +static inline int needs_swap_endian(struct fsl_qspi *q) {
> +	return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN; }
> +
> +static inline int needs_4x_clock(struct fsl_qspi *q) {
> +	return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK; }
> +
> +static inline int needs_fill_txfifo(struct fsl_qspi *q) {
> +	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890; }
> +
> +static inline int needs_wakeup_wait_mode(struct fsl_qspi *q) {
> +	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618; }
> +
> +static inline int needs_amba_base_offset(struct fsl_qspi *q) {
> +	return !(q->devtype_data->quirks &
> QUADSPI_QUIRK_BASE_INTERNAL); }
> +
> +/*
> + * An IC bug makes it necessary to rearrange the 32-bit data.
> + * Later chips, such as IMX6SLX, have fixed this bug.
> + */
> +static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a) {
> +	return needs_swap_endian(q) ? __swab32(a) : a; }
> +
> +/*
> + * R/W functions for big- or little-endian registers:
> + * The QSPI controller's endianness is independent of
> + * the CPU core's endianness. So far, although the CPU
> + * core is little-endian the QSPI controller can use
> + * big-endian or little-endian.
> + */
> +static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem
> +*addr) {
> +	if (q->devtype_data->little_endian)
> +		iowrite32(val, addr);
> +	else
> +		iowrite32be(val, addr);
> +}
> +
> +static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr) {
> +	if (q->devtype_data->little_endian)
> +		return ioread32(addr);
> +
> +	return ioread32be(addr);
> +}
> +
> +static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id) {
> +	struct fsl_qspi *q = dev_id;
> +	u32 reg;
> +
> +	/* clear interrupt */
> +	reg = qspi_readl(q, q->iobase + QUADSPI_FR);
> +	qspi_writel(q, reg, q->iobase + QUADSPI_FR);
> +
> +	if (reg & QUADSPI_FR_TFF_MASK)
> +		complete(&q->c);
> +
> +	dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg);
> +	return IRQ_HANDLED;
> +}
> +
> +static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width) {
> +	switch (width) {
> +	case 1:
> +	case 2:
> +	case 4:
> +		return 0;
> +	}
> +
> +	return -ENOTSUPP;
> +}
> +
> +static bool fsl_qspi_supports_op(struct spi_mem *mem,
> +				 const struct spi_mem_op *op)
> +{
> +	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
> +	int ret;
> +
> +	ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
> +
> +	if (op->addr.nbytes)
> +		ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
> +
> +	if (op->dummy.nbytes)
> +		ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
> +
> +	if (op->data.nbytes)
> +		ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
> +
> +	if (ret)
> +		return false;
> +
> +	/*
> +	 * The number of instructions needed for the op, needs
> +	 * to fit into a single LUT entry.
> +	 */
> +	if (op->addr.nbytes +
> +	   (op->dummy.nbytes ? 1:0) +
> +	   (op->data.nbytes ? 1:0) > 6)
> +		return false;
> +
> +	/* Max 64 dummy clock cycles supported */
> +	if (op->dummy.nbytes &&
> +	    (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
> +		return false;
> +
> +	/* Max data length, check controller limits and alignment */
> +	if (op->data.dir == SPI_MEM_DATA_IN &&
> +	    (op->data.nbytes > q->devtype_data->ahb_buf_size ||
> +	     (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
> +	      !IS_ALIGNED(op->data.nbytes, 8))))
> +		return false;
> +
> +	if (op->data.dir == SPI_MEM_DATA_OUT &&
> +	    op->data.nbytes > q->devtype_data->txfifo)
> +		return false;
> +
> +	return true;
> +}
> +
> +static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
> +				 const struct spi_mem_op *op)
> +{
> +	void __iomem *base = q->iobase;
> +	u32 lutval[4] = {};
> +	int lutidx = 1, i;
> +
> +	lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
> +			     op->cmd.opcode);
> +
> +	/*
> +	 * For some unknown reason, using LUT_ADDR doesn't work in some
> +	 * cases (at least with only one byte long addresses), so
> +	 * let's use LUT_MODE to write the address bytes one by one
> +	 */
> +	for (i = 0; i < op->addr.nbytes; i++) {
> +		u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
> +
> +		lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
> +					      LUT_PAD(op->addr.buswidth),
> +					      addrbyte);
> +		lutidx++;
> +	}
> +
> +	if (op->dummy.nbytes) {
> +		lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
> +					      LUT_PAD(op->dummy.buswidth),
> +					      op->dummy.nbytes * 8 /
> +					      op->dummy.buswidth);
> +		lutidx++;
> +	}
> +
> +	if (op->data.nbytes) {
> +		lutval[lutidx / 2] |= LUT_DEF(lutidx,
> +					      op->data.dir ==
> SPI_MEM_DATA_IN ?
> +					      LUT_FSL_READ : LUT_FSL_WRITE,
> +					      LUT_PAD(op->data.buswidth),
> +					      0);
> +		lutidx++;
> +	}
> +
> +	lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
> +
> +	/* unlock LUT */
> +	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
> +	qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
> +
> +	/* fill LUT */
> +	for (i = 0; i < ARRAY_SIZE(lutval); i++)
> +		qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
> +
> +	/* lock LUT */
> +	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
> +	qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); }
> +
> +static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q) {
> +	int ret;
> +
> +	ret = clk_prepare_enable(q->clk_en);
> +	if (ret)
> +		return ret;
> +
> +	ret = clk_prepare_enable(q->clk);
> +	if (ret) {
> +		clk_disable_unprepare(q->clk_en);
> +		return ret;
> +	}
> +
> +	if (needs_wakeup_wait_mode(q))
> +		pm_qos_add_request(&q->pm_qos_req,
> PM_QOS_CPU_DMA_LATENCY, 0);
> +
> +	return 0;
> +}
> +
> +static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q) {
> +	if (needs_wakeup_wait_mode(q))
> +		pm_qos_remove_request(&q->pm_qos_req);
> +
> +	clk_disable_unprepare(q->clk);
> +	clk_disable_unprepare(q->clk_en);
> +}
> +
> +/*
> + * If we have changed the content of the flash by writing or erasing,
> +or if we
> + * read from flash with a different offset into the page buffer, we
> +need to
> + * invalidate the AHB buffer. If we do not do so, we may read out the
> +wrong
> + * data. The spec tells us reset the AHB domain and Serial Flash domain
> +at
> + * the same time.
> + */
> +static void fsl_qspi_invalidate(struct fsl_qspi *q) {
> +	u32 reg;
> +
> +	reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
> +	reg |= QUADSPI_MCR_SWRSTHD_MASK |
> QUADSPI_MCR_SWRSTSD_MASK;
> +	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
> +
> +	/*
> +	 * The minimum delay : 1 AHB + 2 SFCK clocks.
> +	 * Delay 1 us is enough.
> +	 */
> +	udelay(1);
> +
> +	reg &= ~(QUADSPI_MCR_SWRSTHD_MASK |
> QUADSPI_MCR_SWRSTSD_MASK);
> +	qspi_writel(q, reg, q->iobase + QUADSPI_MCR); }
> +
> +static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device
> +*spi) {
> +	unsigned long rate = spi->max_speed_hz;
> +	int ret;
> +
> +	if (q->selected == spi->chip_select)
> +		return;
> +
> +	if (needs_4x_clock(q))
> +		rate *= 4;
> +
> +	fsl_qspi_clk_disable_unprep(q);
> +
> +	ret = clk_set_rate(q->clk, rate);
> +	if (ret)
> +		return;
> +
> +	ret = fsl_qspi_clk_prep_enable(q);
> +	if (ret)
> +		return;
> +
> +	q->selected = spi->chip_select;
> +
> +	fsl_qspi_invalidate(q);
> +}
> +
> +static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct
> +spi_mem_op *op) {
> +	memcpy_fromio(op->data.buf.in,
> +		      q->ahb_addr + q->selected * q->devtype_data-
> >ahb_buf_size,
> +		      op->data.nbytes);
> +}
> +
> +static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
> +				 const struct spi_mem_op *op)
> +{
> +	void __iomem *base = q->iobase;
> +	int i;
> +	u32 val;
> +
> +	for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
> +		memcpy(&val, op->data.buf.out + i, 4);
> +		val = fsl_qspi_endian_xchg(q, val);
> +		qspi_writel(q, val, base + QUADSPI_TBDR);
> +	}
> +
> +	if (i < op->data.nbytes) {
> +		memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
> +		val = fsl_qspi_endian_xchg(q, val);
> +		qspi_writel(q, val, base + QUADSPI_TBDR);
> +	}
> +
> +	if (needs_fill_txfifo(q)) {
> +		for (i = op->data.nbytes; i < 16; i += 4)
> +			qspi_writel(q, 0, base + QUADSPI_TBDR);
> +	}
> +}
> +
> +static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
> +			  const struct spi_mem_op *op)
> +{
> +	void __iomem *base = q->iobase;
> +	int i;
> +	u8 *buf = op->data.buf.in;
> +	u32 val;
> +
> +	for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
> +		val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
> +		val = fsl_qspi_endian_xchg(q, val);
> +		memcpy(buf + i, &val, 4);
> +	}
> +
> +	if (i < op->data.nbytes) {
> +		val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
> +		val = fsl_qspi_endian_xchg(q, val);
> +		memcpy(buf + i, &val, op->data.nbytes - i);
> +	}
> +}
> +
> +static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op
> +*op) {
> +	void __iomem *base = q->iobase;
> +	int err = 0;
> +
> +	init_completion(&q->c);
> +
> +	/*
> +	 * Always start the sequence at the same index since we update
> +	 * the LUT at each exec_op() call. And also specify the DATA
> +	 * length, since it's has not been specified in the LUT.
> +	 */
> +	qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
> +		    base + QUADSPI_IPCR);
> +
> +	/* Wait for the interrupt. */
> +	if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000)))
> +		err = -ETIMEDOUT;
> +
> +	if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
> +		fsl_qspi_read_rxfifo(q, op);
> +
> +	return err;
> +}
> +
> +static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
> +				    u32 mask, u32 delay_us, u32 timeout_us) {
> +	u32 reg;
> +
> +	if (!q->devtype_data->little_endian)
> +		mask = (u32)cpu_to_be32(mask);
> +

reg is being used as an un-initialized variable, didn't it needs to be initialized with some proper value?

> +	return readl_poll_timeout(base, reg, !(reg & mask), delay_us,
> +				  timeout_us);
> +}
> +

--
Regards
Yogesh Gaur.

[...]

Re: [PATCH v7 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Schrempf Frieder]

On 07.12.18 06:46, Yogesh Narayan Gaur wrote:
> Hi Frieder,
> 
>> -----Original Message-----
>> From: Schrempf Frieder [mailto:frieder.schrempf@kontron.de]
>> Sent: Tuesday, December 4, 2018 7:45 PM
>> To: linux-mtd@lists.infradead.org; boris.brezillon@bootlin.com; linux-
>> spi@vger.kernel.org; Marek Vasut <marek.vasut@gmail.com>; Mark Brown
>> <broonie@kernel.org>; Han Xu <han.xu@nxp.com>
>> Cc: dwmw2@infradead.org; computersforpeace@gmail.com; richard@nod.at;
>> miquel.raynal@bootlin.com; David Wolfe <david.wolfe@nxp.com>; Fabio
>> Estevam <fabio.estevam@nxp.com>; Prabhakar Kushwaha
>> <prabhakar.kushwaha@nxp.com>; Yogesh Narayan Gaur
>> <yogeshnarayan.gaur@nxp.com>; shawnguo@kernel.org; Schrempf Frieder
>> <frieder.schrempf@kontron.de>; linux-kernel@vger.kernel.org
>> Subject: [PATCH v7 3/9] spi: Add a driver for the Freescale/NXP QuadSPI
>> controller
>>
>> From: Frieder Schrempf <frieder.schrempf@kontron.de>
>>
>> This driver is derived from the SPI NOR driver at mtd/spi-nor/fsl-quadspi.c. It
>> uses the new SPI memory interface of the SPI framework to issue flash memory
>> operations to up to four connected flash chips (2 buses with 2 CS each).
>>
>> The controller does not support generic SPI messages.
>>
>> This patch also disables the build of the "old" driver and reuses its Kconfig option
>> CONFIG_SPI_FSL_QUADSPI to replace it.
>>
>> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
>> ---
>>   drivers/mtd/spi-nor/Kconfig  |   9 -
>>   drivers/mtd/spi-nor/Makefile |   1 -
>>   drivers/spi/Kconfig          |  11 +
>>   drivers/spi/Makefile         |   1 +
>>   drivers/spi/spi-fsl-qspi.c   | 966 ++++++++++++++++++++++++++++++++++++++
>>   5 files changed, 978 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index
>> 6cc9c92..d1ca307 100644
>> --- a/drivers/mtd/spi-nor/Kconfig
>> +++ b/drivers/mtd/spi-nor/Kconfig
>> @@ -59,15 +59,6 @@ config SPI_CADENCE_QUADSPI
>>   	  device with a Cadence QSPI controller and want to access the
>>   	  Flash as an MTD device.
>>
>> -config SPI_FSL_QUADSPI
>> -	tristate "Freescale Quad SPI controller"
>> -	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE ||
>> COMPILE_TEST
>> -	depends on HAS_IOMEM
>> -	help
>> -	  This enables support for the Quad SPI controller in master mode.
>> -	  This controller does not support generic SPI. It only supports
>> -	  SPI NOR.
>> -
>>   config SPI_HISI_SFC
>>   	tristate "Hisilicon SPI-NOR Flash Controller(SFC)"
>>   	depends on ARCH_HISI || COMPILE_TEST
>> diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index
>> f4c61d2..3f160c2e3 100644
>> --- a/drivers/mtd/spi-nor/Makefile
>> +++ b/drivers/mtd/spi-nor/Makefile
>> @@ -3,7 +3,6 @@ obj-$(CONFIG_MTD_SPI_NOR)	+= spi-nor.o
>>   obj-$(CONFIG_SPI_ASPEED_SMC)	+= aspeed-smc.o
>>   obj-$(CONFIG_SPI_ATMEL_QUADSPI)	+= atmel-quadspi.o
>>   obj-$(CONFIG_SPI_CADENCE_QUADSPI)	+= cadence-quadspi.o
>> -obj-$(CONFIG_SPI_FSL_QUADSPI)	+= fsl-quadspi.o
>>   obj-$(CONFIG_SPI_HISI_SFC)	+= hisi-sfc.o
>>   obj-$(CONFIG_MTD_MT81xx_NOR)    += mtk-quadspi.o
>>   obj-$(CONFIG_SPI_NXP_SPIFI)	+= nxp-spifi.o
>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 7d3a5c9..8c84186
>> 100644
>> --- a/drivers/spi/Kconfig
>> +++ b/drivers/spi/Kconfig
>> @@ -259,6 +259,17 @@ config SPI_FSL_LPSPI
>>   	help
>>   	  This enables Freescale i.MX LPSPI controllers in master mode.
>>
>> +config SPI_FSL_QUADSPI
>> +	tristate "Freescale QSPI controller"
>> +	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE ||
>> COMPILE_TEST
>> +	depends on HAS_IOMEM
>> +	help
>> +	  This enables support for the Quad SPI controller in master mode.
>> +	  Up to four flash chips can be connected on two buses with two
>> +	  chipselects each.
>> +	  This controller does not support generic SPI messages. It only
>> +	  supports the high-level SPI memory interface.
>> +
>>   config SPI_GPIO
>>   	tristate "GPIO-based bitbanging SPI Master"
>>   	depends on GPIOLIB || COMPILE_TEST
>> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 3575205..5377e61
>> 100644
>> --- a/drivers/spi/Makefile
>> +++ b/drivers/spi/Makefile
>> @@ -44,6 +44,7 @@ obj-$(CONFIG_SPI_FSL_DSPI)		+= spi-fsl-
>> dspi.o
>>   obj-$(CONFIG_SPI_FSL_LIB)		+= spi-fsl-lib.o
>>   obj-$(CONFIG_SPI_FSL_ESPI)		+= spi-fsl-espi.o
>>   obj-$(CONFIG_SPI_FSL_LPSPI)		+= spi-fsl-lpspi.o
>> +obj-$(CONFIG_SPI_FSL_QUADSPI)		+= spi-fsl-qspi.o
>>   obj-$(CONFIG_SPI_FSL_SPI)		+= spi-fsl-spi.o
>>   obj-$(CONFIG_SPI_GPIO)			+= spi-gpio.o
>>   obj-$(CONFIG_SPI_IMG_SPFI)		+= spi-img-spfi.o
>> diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c new file mode
>> 100644 index 0000000..f0a3400
>> --- /dev/null
>> +++ b/drivers/spi/spi-fsl-qspi.c
>> @@ -0,0 +1,966 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +
>> +/*
>> + * Freescale QuadSPI driver.
>> + *
>> + * Copyright (C) 2013 Freescale Semiconductor, Inc.
>> + * Copyright (C) 2018 Bootlin
>> + * Copyright (C) 2018 exceet electronics GmbH
>> + * Copyright (C) 2018 Kontron Electronics GmbH
>> + *
>> + * Transition to SPI MEM interface:
>> + * Authors:
>> + *     Boris Brezillion <boris.brezillon@bootlin.com>
>> + *     Frieder Schrempf <frieder.schrempf@kontron.de>
>> + *     Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
>> + *     Suresh Gupta <suresh.gupta@nxp.com>
>> + *
>> + * Based on the original fsl-quadspi.c spi-nor driver:
>> + * Author: Freescale Semiconductor, Inc.
>> + *
>> + */
>> +
>> +#include <linux/bitops.h>
>> +#include <linux/clk.h>
>> +#include <linux/completion.h>
>> +#include <linux/delay.h>
>> +#include <linux/err.h>
>> +#include <linux/errno.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/io.h>
>> +#include <linux/iopoll.h>
>> +#include <linux/jiffies.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/mutex.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/pm_qos.h>
>> +#include <linux/sizes.h>
>> +
>> +#include <linux/spi/spi.h>
>> +#include <linux/spi/spi-mem.h>
>> +
>> +/*
>> + * The driver only uses one single LUT entry, that is updated on
>> + * each call of exec_op(). Index 0 is preset at boot with a basic
>> + * read operation, so let's use the last entry (15).
>> + */
>> +#define	SEQID_LUT			15
>> +
>> +/* Registers used by the driver */
>> +#define QUADSPI_MCR			0x00
>> +#define QUADSPI_MCR_RESERVED_MASK	GENMASK(19, 16)
>> +#define QUADSPI_MCR_MDIS_MASK		BIT(14)
>> +#define QUADSPI_MCR_CLR_TXF_MASK	BIT(11)
>> +#define QUADSPI_MCR_CLR_RXF_MASK	BIT(10)
>> +#define QUADSPI_MCR_DDR_EN_MASK		BIT(7)
>> +#define QUADSPI_MCR_END_CFG_MASK	GENMASK(3, 2)
>> +#define QUADSPI_MCR_SWRSTHD_MASK	BIT(1)
>> +#define QUADSPI_MCR_SWRSTSD_MASK	BIT(0)
>> +
>> +#define QUADSPI_IPCR			0x08
>> +#define QUADSPI_IPCR_SEQID(x)		((x) << 24)
>> +
>> +#define QUADSPI_BUF3CR			0x1c
>> +#define QUADSPI_BUF3CR_ALLMST_MASK	BIT(31)
>> +#define QUADSPI_BUF3CR_ADATSZ(x)	((x) << 8)
>> +#define QUADSPI_BUF3CR_ADATSZ_MASK	GENMASK(15, 8)
>> +
>> +#define QUADSPI_BFGENCR			0x20
>> +#define QUADSPI_BFGENCR_SEQID(x)	((x) << 12)
>> +
>> +#define QUADSPI_BUF0IND			0x30
>> +#define QUADSPI_BUF1IND			0x34
>> +#define QUADSPI_BUF2IND			0x38
>> +#define QUADSPI_SFAR			0x100
>> +
>> +#define QUADSPI_SMPR			0x108
>> +#define QUADSPI_SMPR_DDRSMP_MASK	GENMASK(18, 16)
>> +#define QUADSPI_SMPR_FSDLY_MASK		BIT(6)
>> +#define QUADSPI_SMPR_FSPHS_MASK		BIT(5)
>> +#define QUADSPI_SMPR_HSENA_MASK		BIT(0)
>> +
>> +#define QUADSPI_RBCT			0x110
>> +#define QUADSPI_RBCT_WMRK_MASK		GENMASK(4, 0)
>> +#define QUADSPI_RBCT_RXBRD_USEIPS	BIT(8)
>> +
>> +#define QUADSPI_TBDR			0x154
>> +
>> +#define QUADSPI_SR			0x15c
>> +#define QUADSPI_SR_IP_ACC_MASK		BIT(1)
>> +#define QUADSPI_SR_AHB_ACC_MASK		BIT(2)
>> +
>> +#define QUADSPI_FR			0x160
>> +#define QUADSPI_FR_TFF_MASK		BIT(0)
>> +
>> +#define QUADSPI_SPTRCLR			0x16c
>> +#define QUADSPI_SPTRCLR_IPPTRC		BIT(8)
>> +#define QUADSPI_SPTRCLR_BFPTRC		BIT(0)
>> +
>> +#define QUADSPI_SFA1AD			0x180
>> +#define QUADSPI_SFA2AD			0x184
>> +#define QUADSPI_SFB1AD			0x188
>> +#define QUADSPI_SFB2AD			0x18c
>> +#define QUADSPI_RBDR(x)			(0x200 + ((x) * 4))
>> +
>> +#define QUADSPI_LUTKEY			0x300
>> +#define QUADSPI_LUTKEY_VALUE		0x5AF05AF0
>> +
>> +#define QUADSPI_LCKCR			0x304
>> +#define QUADSPI_LCKER_LOCK		BIT(0)
>> +#define QUADSPI_LCKER_UNLOCK		BIT(1)
>> +
>> +#define QUADSPI_RSER			0x164
>> +#define QUADSPI_RSER_TFIE		BIT(0)
>> +
>> +#define QUADSPI_LUT_BASE		0x310
>> +#define QUADSPI_LUT_OFFSET		(SEQID_LUT * 4 * 4)
>> +#define QUADSPI_LUT_REG(idx) \
>> +	(QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
>> +
>> +/* Instruction set for the LUT register */
>> +#define LUT_STOP		0
>> +#define LUT_CMD			1
>> +#define LUT_ADDR		2
>> +#define LUT_DUMMY		3
>> +#define LUT_MODE		4
>> +#define LUT_MODE2		5
>> +#define LUT_MODE4		6
>> +#define LUT_FSL_READ		7
>> +#define LUT_FSL_WRITE		8
>> +#define LUT_JMP_ON_CS		9
>> +#define LUT_ADDR_DDR		10
>> +#define LUT_MODE_DDR		11
>> +#define LUT_MODE2_DDR		12
>> +#define LUT_MODE4_DDR		13
>> +#define LUT_FSL_READ_DDR	14
>> +#define LUT_FSL_WRITE_DDR	15
>> +#define LUT_DATA_LEARN		16
>> +
>> +/*
>> + * The PAD definitions for LUT register.
>> + *
>> + * The pad stands for the number of IO lines [0:3].
>> + * For example, the quad read needs four IO lines,
>> + * so you should use LUT_PAD(4).
>> + */
>> +#define LUT_PAD(x) (fls(x) - 1)
>> +
>> +/*
>> + * Macro for constructing the LUT entries with the following
>> + * register layout:
>> + *
>> + *  ---------------------------------------------------
>> + *  | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
>> + *  ---------------------------------------------------
>> + */
>> +#define LUT_DEF(idx, ins, pad, opr)					\
>> +	((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
>> +
>> +/* Controller needs driver to swap endianness */
>> +#define QUADSPI_QUIRK_SWAP_ENDIAN	BIT(0)
>> +
>> +/* Controller needs 4x internal clock */
>> +#define QUADSPI_QUIRK_4X_INT_CLK	BIT(1)
>> +
>> +/*
>> + * TKT253890, the controller needs the driver to fill the txfifo with
>> + * 16 bytes at least to trigger a data transfer, even though the extra
>> + * data won't be transferred.
>> + */
>> +#define QUADSPI_QUIRK_TKT253890		BIT(2)
>> +
>> +/* TKT245618, the controller cannot wake up from wait mode */
>> +#define QUADSPI_QUIRK_TKT245618		BIT(3)
>> +
>> +/*
>> + * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
>> + * internally. No need to add it when setting SFXXAD and SFAR registers
>> +*/
>> +#define QUADSPI_QUIRK_BASE_INTERNAL	BIT(4)
>> +
>> +struct fsl_qspi_devtype_data {
>> +	unsigned int rxfifo;
>> +	unsigned int txfifo;
>> +	unsigned int ahb_buf_size;
>> +	unsigned int quirks;
>> +	bool little_endian;
>> +};
>> +
>> +static const struct fsl_qspi_devtype_data vybrid_data = {
>> +	.rxfifo = SZ_128,
>> +	.txfifo = SZ_64,
>> +	.ahb_buf_size = SZ_1K,
>> +	.quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
>> +	.little_endian = true,
>> +};
>> +
>> +static const struct fsl_qspi_devtype_data imx6sx_data = {
>> +	.rxfifo = SZ_128,
>> +	.txfifo = SZ_512,
>> +	.ahb_buf_size = SZ_1K,
>> +	.quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
>> +	.little_endian = true,
>> +};
>> +
>> +static const struct fsl_qspi_devtype_data imx7d_data = {
>> +	.rxfifo = SZ_512,
>> +	.txfifo = SZ_512,
>> +	.ahb_buf_size = SZ_1K,
>> +	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
>> +	.little_endian = true,
>> +};
>> +
>> +static const struct fsl_qspi_devtype_data imx6ul_data = {
>> +	.rxfifo = SZ_128,
>> +	.txfifo = SZ_512,
>> +	.ahb_buf_size = SZ_1K,
>> +	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
>> +	.little_endian = true,
>> +};
>> +
>> +static const struct fsl_qspi_devtype_data ls1021a_data = {
>> +	.rxfifo = SZ_128,
>> +	.txfifo = SZ_64,
>> +	.ahb_buf_size = SZ_1K,
>> +	.quirks = 0,
>> +	.little_endian = false,
>> +};
>> +
>> +static const struct fsl_qspi_devtype_data ls2080a_data = {
>> +	.rxfifo = SZ_128,
>> +	.txfifo = SZ_64,
>> +	.ahb_buf_size = SZ_1K,
>> +	.quirks = QUADSPI_QUIRK_TKT253890 |
>> QUADSPI_QUIRK_BASE_INTERNAL,
>> +	.little_endian = true,
>> +};
>> +
>> +struct fsl_qspi {
>> +	void __iomem *iobase;
>> +	void __iomem *ahb_addr;
>> +	u32 memmap_phy;
>> +	struct clk *clk, *clk_en;
>> +	struct device *dev;
>> +	struct completion c;
>> +	const struct fsl_qspi_devtype_data *devtype_data;
>> +	struct mutex lock;
>> +	struct pm_qos_request pm_qos_req;
>> +	int selected;
>> +};
>> +
>> +static inline int needs_swap_endian(struct fsl_qspi *q) {
>> +	return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN; }
>> +
>> +static inline int needs_4x_clock(struct fsl_qspi *q) {
>> +	return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK; }
>> +
>> +static inline int needs_fill_txfifo(struct fsl_qspi *q) {
>> +	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890; }
>> +
>> +static inline int needs_wakeup_wait_mode(struct fsl_qspi *q) {
>> +	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618; }
>> +
>> +static inline int needs_amba_base_offset(struct fsl_qspi *q) {
>> +	return !(q->devtype_data->quirks &
>> QUADSPI_QUIRK_BASE_INTERNAL); }
>> +
>> +/*
>> + * An IC bug makes it necessary to rearrange the 32-bit data.
>> + * Later chips, such as IMX6SLX, have fixed this bug.
>> + */
>> +static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a) {
>> +	return needs_swap_endian(q) ? __swab32(a) : a; }
>> +
>> +/*
>> + * R/W functions for big- or little-endian registers:
>> + * The QSPI controller's endianness is independent of
>> + * the CPU core's endianness. So far, although the CPU
>> + * core is little-endian the QSPI controller can use
>> + * big-endian or little-endian.
>> + */
>> +static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem
>> +*addr) {
>> +	if (q->devtype_data->little_endian)
>> +		iowrite32(val, addr);
>> +	else
>> +		iowrite32be(val, addr);
>> +}
>> +
>> +static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr) {
>> +	if (q->devtype_data->little_endian)
>> +		return ioread32(addr);
>> +
>> +	return ioread32be(addr);
>> +}
>> +
>> +static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id) {
>> +	struct fsl_qspi *q = dev_id;
>> +	u32 reg;
>> +
>> +	/* clear interrupt */
>> +	reg = qspi_readl(q, q->iobase + QUADSPI_FR);
>> +	qspi_writel(q, reg, q->iobase + QUADSPI_FR);
>> +
>> +	if (reg & QUADSPI_FR_TFF_MASK)
>> +		complete(&q->c);
>> +
>> +	dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg);
>> +	return IRQ_HANDLED;
>> +}
>> +
>> +static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width) {
>> +	switch (width) {
>> +	case 1:
>> +	case 2:
>> +	case 4:
>> +		return 0;
>> +	}
>> +
>> +	return -ENOTSUPP;
>> +}
>> +
>> +static bool fsl_qspi_supports_op(struct spi_mem *mem,
>> +				 const struct spi_mem_op *op)
>> +{
>> +	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
>> +	int ret;
>> +
>> +	ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
>> +
>> +	if (op->addr.nbytes)
>> +		ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
>> +
>> +	if (op->dummy.nbytes)
>> +		ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
>> +
>> +	if (op->data.nbytes)
>> +		ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
>> +
>> +	if (ret)
>> +		return false;
>> +
>> +	/*
>> +	 * The number of instructions needed for the op, needs
>> +	 * to fit into a single LUT entry.
>> +	 */
>> +	if (op->addr.nbytes +
>> +	   (op->dummy.nbytes ? 1:0) +
>> +	   (op->data.nbytes ? 1:0) > 6)
>> +		return false;
>> +
>> +	/* Max 64 dummy clock cycles supported */
>> +	if (op->dummy.nbytes &&
>> +	    (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
>> +		return false;
>> +
>> +	/* Max data length, check controller limits and alignment */
>> +	if (op->data.dir == SPI_MEM_DATA_IN &&
>> +	    (op->data.nbytes > q->devtype_data->ahb_buf_size ||
>> +	     (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
>> +	      !IS_ALIGNED(op->data.nbytes, 8))))
>> +		return false;
>> +
>> +	if (op->data.dir == SPI_MEM_DATA_OUT &&
>> +	    op->data.nbytes > q->devtype_data->txfifo)
>> +		return false;
>> +
>> +	return true;
>> +}
>> +
>> +static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
>> +				 const struct spi_mem_op *op)
>> +{
>> +	void __iomem *base = q->iobase;
>> +	u32 lutval[4] = {};
>> +	int lutidx = 1, i;
>> +
>> +	lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
>> +			     op->cmd.opcode);
>> +
>> +	/*
>> +	 * For some unknown reason, using LUT_ADDR doesn't work in some
>> +	 * cases (at least with only one byte long addresses), so
>> +	 * let's use LUT_MODE to write the address bytes one by one
>> +	 */
>> +	for (i = 0; i < op->addr.nbytes; i++) {
>> +		u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
>> +
>> +		lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
>> +					      LUT_PAD(op->addr.buswidth),
>> +					      addrbyte);
>> +		lutidx++;
>> +	}
>> +
>> +	if (op->dummy.nbytes) {
>> +		lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
>> +					      LUT_PAD(op->dummy.buswidth),
>> +					      op->dummy.nbytes * 8 /
>> +					      op->dummy.buswidth);
>> +		lutidx++;
>> +	}
>> +
>> +	if (op->data.nbytes) {
>> +		lutval[lutidx / 2] |= LUT_DEF(lutidx,
>> +					      op->data.dir ==
>> SPI_MEM_DATA_IN ?
>> +					      LUT_FSL_READ : LUT_FSL_WRITE,
>> +					      LUT_PAD(op->data.buswidth),
>> +					      0);
>> +		lutidx++;
>> +	}
>> +
>> +	lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
>> +
>> +	/* unlock LUT */
>> +	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
>> +	qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
>> +
>> +	/* fill LUT */
>> +	for (i = 0; i < ARRAY_SIZE(lutval); i++)
>> +		qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
>> +
>> +	/* lock LUT */
>> +	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
>> +	qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); }
>> +
>> +static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q) {
>> +	int ret;
>> +
>> +	ret = clk_prepare_enable(q->clk_en);
>> +	if (ret)
>> +		return ret;
>> +
>> +	ret = clk_prepare_enable(q->clk);
>> +	if (ret) {
>> +		clk_disable_unprepare(q->clk_en);
>> +		return ret;
>> +	}
>> +
>> +	if (needs_wakeup_wait_mode(q))
>> +		pm_qos_add_request(&q->pm_qos_req,
>> PM_QOS_CPU_DMA_LATENCY, 0);
>> +
>> +	return 0;
>> +}
>> +
>> +static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q) {
>> +	if (needs_wakeup_wait_mode(q))
>> +		pm_qos_remove_request(&q->pm_qos_req);
>> +
>> +	clk_disable_unprepare(q->clk);
>> +	clk_disable_unprepare(q->clk_en);
>> +}
>> +
>> +/*
>> + * If we have changed the content of the flash by writing or erasing,
>> +or if we
>> + * read from flash with a different offset into the page buffer, we
>> +need to
>> + * invalidate the AHB buffer. If we do not do so, we may read out the
>> +wrong
>> + * data. The spec tells us reset the AHB domain and Serial Flash domain
>> +at
>> + * the same time.
>> + */
>> +static void fsl_qspi_invalidate(struct fsl_qspi *q) {
>> +	u32 reg;
>> +
>> +	reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
>> +	reg |= QUADSPI_MCR_SWRSTHD_MASK |
>> QUADSPI_MCR_SWRSTSD_MASK;
>> +	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
>> +
>> +	/*
>> +	 * The minimum delay : 1 AHB + 2 SFCK clocks.
>> +	 * Delay 1 us is enough.
>> +	 */
>> +	udelay(1);
>> +
>> +	reg &= ~(QUADSPI_MCR_SWRSTHD_MASK |
>> QUADSPI_MCR_SWRSTSD_MASK);
>> +	qspi_writel(q, reg, q->iobase + QUADSPI_MCR); }
>> +
>> +static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device
>> +*spi) {
>> +	unsigned long rate = spi->max_speed_hz;
>> +	int ret;
>> +
>> +	if (q->selected == spi->chip_select)
>> +		return;
>> +
>> +	if (needs_4x_clock(q))
>> +		rate *= 4;
>> +
>> +	fsl_qspi_clk_disable_unprep(q);
>> +
>> +	ret = clk_set_rate(q->clk, rate);
>> +	if (ret)
>> +		return;
>> +
>> +	ret = fsl_qspi_clk_prep_enable(q);
>> +	if (ret)
>> +		return;
>> +
>> +	q->selected = spi->chip_select;
>> +
>> +	fsl_qspi_invalidate(q);
>> +}
>> +
>> +static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct
>> +spi_mem_op *op) {
>> +	memcpy_fromio(op->data.buf.in,
>> +		      q->ahb_addr + q->selected * q->devtype_data-
>>> ahb_buf_size,
>> +		      op->data.nbytes);
>> +}
>> +
>> +static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
>> +				 const struct spi_mem_op *op)
>> +{
>> +	void __iomem *base = q->iobase;
>> +	int i;
>> +	u32 val;
>> +
>> +	for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
>> +		memcpy(&val, op->data.buf.out + i, 4);
>> +		val = fsl_qspi_endian_xchg(q, val);
>> +		qspi_writel(q, val, base + QUADSPI_TBDR);
>> +	}
>> +
>> +	if (i < op->data.nbytes) {
>> +		memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
>> +		val = fsl_qspi_endian_xchg(q, val);
>> +		qspi_writel(q, val, base + QUADSPI_TBDR);
>> +	}
>> +
>> +	if (needs_fill_txfifo(q)) {
>> +		for (i = op->data.nbytes; i < 16; i += 4)
>> +			qspi_writel(q, 0, base + QUADSPI_TBDR);
>> +	}
>> +}
>> +
>> +static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
>> +			  const struct spi_mem_op *op)
>> +{
>> +	void __iomem *base = q->iobase;
>> +	int i;
>> +	u8 *buf = op->data.buf.in;
>> +	u32 val;
>> +
>> +	for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
>> +		val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
>> +		val = fsl_qspi_endian_xchg(q, val);
>> +		memcpy(buf + i, &val, 4);
>> +	}
>> +
>> +	if (i < op->data.nbytes) {
>> +		val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
>> +		val = fsl_qspi_endian_xchg(q, val);
>> +		memcpy(buf + i, &val, op->data.nbytes - i);
>> +	}
>> +}
>> +
>> +static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op
>> +*op) {
>> +	void __iomem *base = q->iobase;
>> +	int err = 0;
>> +
>> +	init_completion(&q->c);
>> +
>> +	/*
>> +	 * Always start the sequence at the same index since we update
>> +	 * the LUT at each exec_op() call. And also specify the DATA
>> +	 * length, since it's has not been specified in the LUT.
>> +	 */
>> +	qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
>> +		    base + QUADSPI_IPCR);
>> +
>> +	/* Wait for the interrupt. */
>> +	if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000)))
>> +		err = -ETIMEDOUT;
>> +
>> +	if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
>> +		fsl_qspi_read_rxfifo(q, op);
>> +
>> +	return err;
>> +}
>> +
>> +static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
>> +				    u32 mask, u32 delay_us, u32 timeout_us) {
>> +	u32 reg;
>> +
>> +	if (!q->devtype_data->little_endian)
>> +		mask = (u32)cpu_to_be32(mask);
>> +
> 
> reg is being used as an un-initialized variable, didn't it needs to be initialized with some proper value?

No, it does not need to be initialized. This is only to assign some 
memory for the readx_poll_timeout() macro: [1].

[1] 
https://elixir.bootlin.com/linux/latest/source/include/linux/iopoll.h#L50

> 
>> +	return readl_poll_timeout(base, reg, !(reg & mask), delay_us,
>> +				  timeout_us);
>> +}
>> +
> 
> --
> Regards
> Yogesh Gaur.
> 
> [...]
> 

RE: [PATCH v7 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Han Xu]

> -----Original Message-----
> From: Schrempf Frieder <frieder.schrempf@kontron.de>
> Sent: Tuesday, December 4, 2018 8:15 AM
> To: linux-mtd@lists.infradead.org; boris.brezillon@bootlin.com; linux-
> spi@vger.kernel.org; Marek Vasut <marek.vasut@gmail.com>; Mark Brown
> <broonie@kernel.org>; Han Xu <han.xu@nxp.com>
> Cc: dwmw2@infradead.org; computersforpeace@gmail.com;
> richard@nod.at; miquel.raynal@bootlin.com; David Wolfe
> <david.wolfe@nxp.com>; Fabio Estevam <fabio.estevam@nxp.com>;
> Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; Yogesh Narayan
> Gaur <yogeshnarayan.gaur@nxp.com>; shawnguo@kernel.org; Schrempf
> Frieder <frieder.schrempf@kontron.de>; linux-kernel@vger.kernel.org
> Subject: [PATCH v7 3/9] spi: Add a driver for the Freescale/NXP QuadSPI
> controller
> 
> From: Frieder Schrempf <frieder.schrempf@kontron.de>
> 
> This driver is derived from the SPI NOR driver at mtd/spi-nor/fsl-quadspi.c. It
> uses the new SPI memory interface of the SPI framework to issue flash
> memory operations to up to four connected flash chips (2 buses with 2 CS
> each).
> 
> The controller does not support generic SPI messages.
> 
> This patch also disables the build of the "old" driver and reuses its Kconfig
> option CONFIG_SPI_FSL_QUADSPI to replace it.
> 
> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
> ---
>  drivers/mtd/spi-nor/Kconfig  |   9 -
>  drivers/mtd/spi-nor/Makefile |   1 -
>  drivers/spi/Kconfig          |  11 +
>  drivers/spi/Makefile         |   1 +
>  drivers/spi/spi-fsl-qspi.c   | 966
> ++++++++++++++++++++++++++++++++++++++
>  5 files changed, 978 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index
> 6cc9c92..d1ca307 100644
> --- a/drivers/mtd/spi-nor/Kconfig
> +++ b/drivers/mtd/spi-nor/Kconfig
> @@ -59,15 +59,6 @@ config SPI_CADENCE_QUADSPI
>  	  device with a Cadence QSPI controller and want to access the
>  	  Flash as an MTD device.
> 
> -config SPI_FSL_QUADSPI
> -	tristate "Freescale Quad SPI controller"
> -	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE ||
> COMPILE_TEST
> -	depends on HAS_IOMEM
> -	help
> -	  This enables support for the Quad SPI controller in master mode.
> -	  This controller does not support generic SPI. It only supports
> -	  SPI NOR.
> -
>  config SPI_HISI_SFC
>  	tristate "Hisilicon SPI-NOR Flash Controller(SFC)"
>  	depends on ARCH_HISI || COMPILE_TEST
> diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
> index f4c61d2..3f160c2e3 100644
> --- a/drivers/mtd/spi-nor/Makefile
> +++ b/drivers/mtd/spi-nor/Makefile
> @@ -3,7 +3,6 @@ obj-$(CONFIG_MTD_SPI_NOR)	+= spi-nor.o
>  obj-$(CONFIG_SPI_ASPEED_SMC)	+= aspeed-smc.o
>  obj-$(CONFIG_SPI_ATMEL_QUADSPI)	+= atmel-quadspi.o
>  obj-$(CONFIG_SPI_CADENCE_QUADSPI)	+= cadence-quadspi.o
> -obj-$(CONFIG_SPI_FSL_QUADSPI)	+= fsl-quadspi.o
>  obj-$(CONFIG_SPI_HISI_SFC)	+= hisi-sfc.o
>  obj-$(CONFIG_MTD_MT81xx_NOR)    += mtk-quadspi.o
>  obj-$(CONFIG_SPI_NXP_SPIFI)	+= nxp-spifi.o
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 7d3a5c9..8c84186
> 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -259,6 +259,17 @@ config SPI_FSL_LPSPI
>  	help
>  	  This enables Freescale i.MX LPSPI controllers in master mode.
> 
> +config SPI_FSL_QUADSPI
> +	tristate "Freescale QSPI controller"
> +	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE ||
> COMPILE_TEST
> +	depends on HAS_IOMEM
> +	help
> +	  This enables support for the Quad SPI controller in master mode.
> +	  Up to four flash chips can be connected on two buses with two
> +	  chipselects each.
> +	  This controller does not support generic SPI messages. It only
> +	  supports the high-level SPI memory interface.
> +
>  config SPI_GPIO
>  	tristate "GPIO-based bitbanging SPI Master"
>  	depends on GPIOLIB || COMPILE_TEST
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index
> 3575205..5377e61 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -44,6 +44,7 @@ obj-$(CONFIG_SPI_FSL_DSPI)		+= spi-fsl-
> dspi.o
>  obj-$(CONFIG_SPI_FSL_LIB)		+= spi-fsl-lib.o
>  obj-$(CONFIG_SPI_FSL_ESPI)		+= spi-fsl-espi.o
>  obj-$(CONFIG_SPI_FSL_LPSPI)		+= spi-fsl-lpspi.o
> +obj-$(CONFIG_SPI_FSL_QUADSPI)		+= spi-fsl-qspi.o
>  obj-$(CONFIG_SPI_FSL_SPI)		+= spi-fsl-spi.o
>  obj-$(CONFIG_SPI_GPIO)			+= spi-gpio.o
>  obj-$(CONFIG_SPI_IMG_SPFI)		+= spi-img-spfi.o
> diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c new file mode
> 100644 index 0000000..f0a3400
> --- /dev/null
> +++ b/drivers/spi/spi-fsl-qspi.c
> @@ -0,0 +1,966 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +/*
> + * Freescale QuadSPI driver.
> + *
> + * Copyright (C) 2013 Freescale Semiconductor, Inc.
> + * Copyright (C) 2018 Bootlin
> + * Copyright (C) 2018 exceet electronics GmbH
> + * Copyright (C) 2018 Kontron Electronics GmbH
> + *
> + * Transition to SPI MEM interface:
> + * Authors:
> + *     Boris Brezillion <boris.brezillon@bootlin.com>
> + *     Frieder Schrempf <frieder.schrempf@kontron.de>
> + *     Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> + *     Suresh Gupta <suresh.gupta@nxp.com>
> + *
> + * Based on the original fsl-quadspi.c spi-nor driver:
> + * Author: Freescale Semiconductor, Inc.
> + *
> + */
> +
> +#include <linux/bitops.h>
> +#include <linux/clk.h>
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/errno.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/jiffies.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_qos.h>
> +#include <linux/sizes.h>
> +
> +#include <linux/spi/spi.h>
> +#include <linux/spi/spi-mem.h>
> +
> +/*
> + * The driver only uses one single LUT entry, that is updated on
> + * each call of exec_op(). Index 0 is preset at boot with a basic
> + * read operation, so let's use the last entry (15).
> + */
> +#define	SEQID_LUT			15
> +
> +/* Registers used by the driver */
> +#define QUADSPI_MCR			0x00
> +#define QUADSPI_MCR_RESERVED_MASK	GENMASK(19, 16)
> +#define QUADSPI_MCR_MDIS_MASK		BIT(14)
> +#define QUADSPI_MCR_CLR_TXF_MASK	BIT(11)
> +#define QUADSPI_MCR_CLR_RXF_MASK	BIT(10)
> +#define QUADSPI_MCR_DDR_EN_MASK		BIT(7)
> +#define QUADSPI_MCR_END_CFG_MASK	GENMASK(3, 2)
> +#define QUADSPI_MCR_SWRSTHD_MASK	BIT(1)
> +#define QUADSPI_MCR_SWRSTSD_MASK	BIT(0)
> +
> +#define QUADSPI_IPCR			0x08
> +#define QUADSPI_IPCR_SEQID(x)		((x) << 24)
> +
> +#define QUADSPI_BUF3CR			0x1c
> +#define QUADSPI_BUF3CR_ALLMST_MASK	BIT(31)
> +#define QUADSPI_BUF3CR_ADATSZ(x)	((x) << 8)
> +#define QUADSPI_BUF3CR_ADATSZ_MASK	GENMASK(15, 8)
> +
> +#define QUADSPI_BFGENCR			0x20
> +#define QUADSPI_BFGENCR_SEQID(x)	((x) << 12)
> +
> +#define QUADSPI_BUF0IND			0x30
> +#define QUADSPI_BUF1IND			0x34
> +#define QUADSPI_BUF2IND			0x38
> +#define QUADSPI_SFAR			0x100
> +
> +#define QUADSPI_SMPR			0x108
> +#define QUADSPI_SMPR_DDRSMP_MASK	GENMASK(18, 16)
> +#define QUADSPI_SMPR_FSDLY_MASK		BIT(6)
> +#define QUADSPI_SMPR_FSPHS_MASK		BIT(5)
> +#define QUADSPI_SMPR_HSENA_MASK		BIT(0)
> +
> +#define QUADSPI_RBCT			0x110
> +#define QUADSPI_RBCT_WMRK_MASK		GENMASK(4, 0)
> +#define QUADSPI_RBCT_RXBRD_USEIPS	BIT(8)
> +
> +#define QUADSPI_TBDR			0x154
> +
> +#define QUADSPI_SR			0x15c
> +#define QUADSPI_SR_IP_ACC_MASK		BIT(1)
> +#define QUADSPI_SR_AHB_ACC_MASK		BIT(2)
> +
> +#define QUADSPI_FR			0x160
> +#define QUADSPI_FR_TFF_MASK		BIT(0)
> +
> +#define QUADSPI_SPTRCLR			0x16c
> +#define QUADSPI_SPTRCLR_IPPTRC		BIT(8)
> +#define QUADSPI_SPTRCLR_BFPTRC		BIT(0)
> +
> +#define QUADSPI_SFA1AD			0x180
> +#define QUADSPI_SFA2AD			0x184
> +#define QUADSPI_SFB1AD			0x188
> +#define QUADSPI_SFB2AD			0x18c
> +#define QUADSPI_RBDR(x)			(0x200 + ((x) * 4))
> +
> +#define QUADSPI_LUTKEY			0x300
> +#define QUADSPI_LUTKEY_VALUE		0x5AF05AF0
> +
> +#define QUADSPI_LCKCR			0x304
> +#define QUADSPI_LCKER_LOCK		BIT(0)
> +#define QUADSPI_LCKER_UNLOCK		BIT(1)
> +
> +#define QUADSPI_RSER			0x164
> +#define QUADSPI_RSER_TFIE		BIT(0)
> +
> +#define QUADSPI_LUT_BASE		0x310
> +#define QUADSPI_LUT_OFFSET		(SEQID_LUT * 4 * 4)
> +#define QUADSPI_LUT_REG(idx) \
> +	(QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
> +
> +/* Instruction set for the LUT register */
> +#define LUT_STOP		0
> +#define LUT_CMD			1
> +#define LUT_ADDR		2
> +#define LUT_DUMMY		3
> +#define LUT_MODE		4
> +#define LUT_MODE2		5
> +#define LUT_MODE4		6
> +#define LUT_FSL_READ		7
> +#define LUT_FSL_WRITE		8
> +#define LUT_JMP_ON_CS		9
> +#define LUT_ADDR_DDR		10
> +#define LUT_MODE_DDR		11
> +#define LUT_MODE2_DDR		12
> +#define LUT_MODE4_DDR		13
> +#define LUT_FSL_READ_DDR	14
> +#define LUT_FSL_WRITE_DDR	15
> +#define LUT_DATA_LEARN		16
> +
> +/*
> + * The PAD definitions for LUT register.
> + *
> + * The pad stands for the number of IO lines [0:3].
> + * For example, the quad read needs four IO lines,
> + * so you should use LUT_PAD(4).
> + */
> +#define LUT_PAD(x) (fls(x) - 1)
> +
> +/*
> + * Macro for constructing the LUT entries with the following
> + * register layout:
> + *
> + *  ---------------------------------------------------
> + *  | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
> + *  ---------------------------------------------------
> + */
> +#define LUT_DEF(idx, ins, pad, opr)					\
> +	((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
> +
> +/* Controller needs driver to swap endianness */
> +#define QUADSPI_QUIRK_SWAP_ENDIAN	BIT(0)
> +
> +/* Controller needs 4x internal clock */
> +#define QUADSPI_QUIRK_4X_INT_CLK	BIT(1)
> +
> +/*
> + * TKT253890, the controller needs the driver to fill the txfifo with
> + * 16 bytes at least to trigger a data transfer, even though the extra
> + * data won't be transferred.
> + */
> +#define QUADSPI_QUIRK_TKT253890		BIT(2)
> +
> +/* TKT245618, the controller cannot wake up from wait mode */
> +#define QUADSPI_QUIRK_TKT245618		BIT(3)
> +
> +/*
> + * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
> + * internally. No need to add it when setting SFXXAD and SFAR registers
> +*/
> +#define QUADSPI_QUIRK_BASE_INTERNAL	BIT(4)
> +
> +struct fsl_qspi_devtype_data {
> +	unsigned int rxfifo;
> +	unsigned int txfifo;
> +	unsigned int ahb_buf_size;
> +	unsigned int quirks;
> +	bool little_endian;
> +};
> +
> +static const struct fsl_qspi_devtype_data vybrid_data = {
> +	.rxfifo = SZ_128,
> +	.txfifo = SZ_64,
> +	.ahb_buf_size = SZ_1K,
> +	.quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
> +	.little_endian = true,
> +};
> +
> +static const struct fsl_qspi_devtype_data imx6sx_data = {
> +	.rxfifo = SZ_128,
> +	.txfifo = SZ_512,
> +	.ahb_buf_size = SZ_1K,
> +	.quirks = QUADSPI_QUIRK_4X_INT_CLK |
> QUADSPI_QUIRK_TKT245618,
> +	.little_endian = true,
> +};
> +
> +static const struct fsl_qspi_devtype_data imx7d_data = {
> +	.rxfifo = SZ_512,
> +	.txfifo = SZ_512,
> +	.ahb_buf_size = SZ_1K,
> +	.quirks = QUADSPI_QUIRK_TKT253890 |
> QUADSPI_QUIRK_4X_INT_CLK,
> +	.little_endian = true,
> +};
> +
> +static const struct fsl_qspi_devtype_data imx6ul_data = {
> +	.rxfifo = SZ_128,
> +	.txfifo = SZ_512,
> +	.ahb_buf_size = SZ_1K,
> +	.quirks = QUADSPI_QUIRK_TKT253890 |
> QUADSPI_QUIRK_4X_INT_CLK,
> +	.little_endian = true,
> +};
> +
> +static const struct fsl_qspi_devtype_data ls1021a_data = {
> +	.rxfifo = SZ_128,
> +	.txfifo = SZ_64,
> +	.ahb_buf_size = SZ_1K,
> +	.quirks = 0,
> +	.little_endian = false,
> +};
> +
> +static const struct fsl_qspi_devtype_data ls2080a_data = {
> +	.rxfifo = SZ_128,
> +	.txfifo = SZ_64,
> +	.ahb_buf_size = SZ_1K,
> +	.quirks = QUADSPI_QUIRK_TKT253890 |
> QUADSPI_QUIRK_BASE_INTERNAL,
> +	.little_endian = true,
> +};
> +
> +struct fsl_qspi {
> +	void __iomem *iobase;
> +	void __iomem *ahb_addr;
> +	u32 memmap_phy;
> +	struct clk *clk, *clk_en;
> +	struct device *dev;
> +	struct completion c;
> +	const struct fsl_qspi_devtype_data *devtype_data;
> +	struct mutex lock;
> +	struct pm_qos_request pm_qos_req;
> +	int selected;
> +};
> +
> +static inline int needs_swap_endian(struct fsl_qspi *q) {
> +	return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN; }
> +
> +static inline int needs_4x_clock(struct fsl_qspi *q) {
> +	return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK; }
> +
> +static inline int needs_fill_txfifo(struct fsl_qspi *q) {
> +	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890; }
> +
> +static inline int needs_wakeup_wait_mode(struct fsl_qspi *q) {
> +	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618; }
> +
> +static inline int needs_amba_base_offset(struct fsl_qspi *q) {
> +	return !(q->devtype_data->quirks &
> QUADSPI_QUIRK_BASE_INTERNAL); }
> +
> +/*
> + * An IC bug makes it necessary to rearrange the 32-bit data.
> + * Later chips, such as IMX6SLX, have fixed this bug.
> + */
> +static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a) {
> +	return needs_swap_endian(q) ? __swab32(a) : a; }
> +
> +/*
> + * R/W functions for big- or little-endian registers:
> + * The QSPI controller's endianness is independent of
> + * the CPU core's endianness. So far, although the CPU
> + * core is little-endian the QSPI controller can use
> + * big-endian or little-endian.
> + */
> +static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem
> +*addr) {
> +	if (q->devtype_data->little_endian)
> +		iowrite32(val, addr);
> +	else
> +		iowrite32be(val, addr);
> +}
> +
> +static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr) {
> +	if (q->devtype_data->little_endian)
> +		return ioread32(addr);
> +
> +	return ioread32be(addr);
> +}
> +
> +static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id) {
> +	struct fsl_qspi *q = dev_id;
> +	u32 reg;
> +
> +	/* clear interrupt */
> +	reg = qspi_readl(q, q->iobase + QUADSPI_FR);
> +	qspi_writel(q, reg, q->iobase + QUADSPI_FR);
> +
> +	if (reg & QUADSPI_FR_TFF_MASK)
> +		complete(&q->c);
> +
> +	dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg);
> +	return IRQ_HANDLED;
> +}
> +
> +static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width) {
> +	switch (width) {
> +	case 1:
> +	case 2:
> +	case 4:
> +		return 0;
> +	}
> +
> +	return -ENOTSUPP;
> +}
> +
> +static bool fsl_qspi_supports_op(struct spi_mem *mem,
> +				 const struct spi_mem_op *op)
> +{
> +	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
> +	int ret;
> +
> +	ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
> +
> +	if (op->addr.nbytes)
> +		ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
> +
> +	if (op->dummy.nbytes)
> +		ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
> +
> +	if (op->data.nbytes)
> +		ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
> +
> +	if (ret)
> +		return false;
> +
> +	/*
> +	 * The number of instructions needed for the op, needs
> +	 * to fit into a single LUT entry.
> +	 */
> +	if (op->addr.nbytes +
> +	   (op->dummy.nbytes ? 1:0) +
> +	   (op->data.nbytes ? 1:0) > 6)
> +		return false;
> +
> +	/* Max 64 dummy clock cycles supported */
> +	if (op->dummy.nbytes &&
> +	    (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
> +		return false;
> +
> +	/* Max data length, check controller limits and alignment */
> +	if (op->data.dir == SPI_MEM_DATA_IN &&
> +	    (op->data.nbytes > q->devtype_data->ahb_buf_size ||
> +	     (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
> +	      !IS_ALIGNED(op->data.nbytes, 8))))
> +		return false;
> +
> +	if (op->data.dir == SPI_MEM_DATA_OUT &&
> +	    op->data.nbytes > q->devtype_data->txfifo)
> +		return false;
> +
> +	return true;
> +}
> +
> +static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
> +				 const struct spi_mem_op *op)
> +{
> +	void __iomem *base = q->iobase;
> +	u32 lutval[4] = {};
> +	int lutidx = 1, i;
> +
> +	lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
> +			     op->cmd.opcode);
> +
> +	/*
> +	 * For some unknown reason, using LUT_ADDR doesn't work in some
> +	 * cases (at least with only one byte long addresses), so
> +	 * let's use LUT_MODE to write the address bytes one by one
> +	 */
> +	for (i = 0; i < op->addr.nbytes; i++) {
> +		u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
> +
> +		lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
> +					      LUT_PAD(op->addr.buswidth),
> +					      addrbyte);
> +		lutidx++;
> +	}
> +
> +	if (op->dummy.nbytes) {
> +		lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
> +					      LUT_PAD(op->dummy.buswidth),
> +					      op->dummy.nbytes * 8 /
> +					      op->dummy.buswidth);
> +		lutidx++;
> +	}
> +
> +	if (op->data.nbytes) {
> +		lutval[lutidx / 2] |= LUT_DEF(lutidx,
> +					      op->data.dir ==
> SPI_MEM_DATA_IN ?
> +					      LUT_FSL_READ : LUT_FSL_WRITE,
> +					      LUT_PAD(op->data.buswidth),
> +					      0);
> +		lutidx++;
> +	}
> +
> +	lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
> +
> +	/* unlock LUT */
> +	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase +
> QUADSPI_LUTKEY);
> +	qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase +
> QUADSPI_LCKCR);
> +
> +	/* fill LUT */
> +	for (i = 0; i < ARRAY_SIZE(lutval); i++)
> +		qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
> +
> +	/* lock LUT */
> +	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase +
> QUADSPI_LUTKEY);
> +	qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); }
> +
> +static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q) {
> +	int ret;
> +
> +	ret = clk_prepare_enable(q->clk_en);
> +	if (ret)
> +		return ret;
> +
> +	ret = clk_prepare_enable(q->clk);
> +	if (ret) {
> +		clk_disable_unprepare(q->clk_en);
> +		return ret;
> +	}
> +
> +	if (needs_wakeup_wait_mode(q))
> +		pm_qos_add_request(&q->pm_qos_req,
> PM_QOS_CPU_DMA_LATENCY, 0);
> +
> +	return 0;
> +}
> +
> +static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q) {
> +	if (needs_wakeup_wait_mode(q))
> +		pm_qos_remove_request(&q->pm_qos_req);
> +
> +	clk_disable_unprepare(q->clk);
> +	clk_disable_unprepare(q->clk_en);
> +}
> +
> +/*
> + * If we have changed the content of the flash by writing or erasing,
> +or if we
> + * read from flash with a different offset into the page buffer, we
> +need to
> + * invalidate the AHB buffer. If we do not do so, we may read out the
> +wrong
> + * data. The spec tells us reset the AHB domain and Serial Flash domain
> +at
> + * the same time.
> + */
> +static void fsl_qspi_invalidate(struct fsl_qspi *q) {
> +	u32 reg;
> +
> +	reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
> +	reg |= QUADSPI_MCR_SWRSTHD_MASK |
> QUADSPI_MCR_SWRSTSD_MASK;
> +	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
> +
> +	/*
> +	 * The minimum delay : 1 AHB + 2 SFCK clocks.
> +	 * Delay 1 us is enough.
> +	 */
> +	udelay(1);
> +
> +	reg &= ~(QUADSPI_MCR_SWRSTHD_MASK |
> QUADSPI_MCR_SWRSTSD_MASK);
> +	qspi_writel(q, reg, q->iobase + QUADSPI_MCR); }
> +
> +static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device
> +*spi) {
> +	unsigned long rate = spi->max_speed_hz;
> +	int ret;
> +
> +	if (q->selected == spi->chip_select)
> +		return;
> +
> +	if (needs_4x_clock(q))
> +		rate *= 4;
> +
> +	fsl_qspi_clk_disable_unprep(q);
> +
> +	ret = clk_set_rate(q->clk, rate);
> +	if (ret)
> +		return;
> +
> +	ret = fsl_qspi_clk_prep_enable(q);
> +	if (ret)
> +		return;
> +
> +	q->selected = spi->chip_select;
> +
> +	fsl_qspi_invalidate(q);
> +}
> +
> +static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct
> +spi_mem_op *op) {
> +	memcpy_fromio(op->data.buf.in,
> +		      q->ahb_addr + q->selected * q->devtype_data-
> >ahb_buf_size,
> +		      op->data.nbytes);
> +}
> +
> +static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
> +				 const struct spi_mem_op *op)
> +{
> +	void __iomem *base = q->iobase;
> +	int i;
> +	u32 val;
> +
> +	for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
> +		memcpy(&val, op->data.buf.out + i, 4);
> +		val = fsl_qspi_endian_xchg(q, val);
> +		qspi_writel(q, val, base + QUADSPI_TBDR);
> +	}
> +
> +	if (i < op->data.nbytes) {
> +		memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
> +		val = fsl_qspi_endian_xchg(q, val);
> +		qspi_writel(q, val, base + QUADSPI_TBDR);
> +	}
> +
> +	if (needs_fill_txfifo(q)) {
> +		for (i = op->data.nbytes; i < 16; i += 4)
> +			qspi_writel(q, 0, base + QUADSPI_TBDR);
> +	}
> +}
> +
> +static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
> +			  const struct spi_mem_op *op)
> +{
> +	void __iomem *base = q->iobase;
> +	int i;
> +	u8 *buf = op->data.buf.in;
> +	u32 val;
> +
> +	for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
> +		val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
> +		val = fsl_qspi_endian_xchg(q, val);
> +		memcpy(buf + i, &val, 4);
> +	}
> +
> +	if (i < op->data.nbytes) {
> +		val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
> +		val = fsl_qspi_endian_xchg(q, val);
> +		memcpy(buf + i, &val, op->data.nbytes - i);
> +	}
> +}
> +
> +static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op
> +*op) {
> +	void __iomem *base = q->iobase;
> +	int err = 0;
> +
> +	init_completion(&q->c);
> +
> +	/*
> +	 * Always start the sequence at the same index since we update
> +	 * the LUT at each exec_op() call. And also specify the DATA
> +	 * length, since it's has not been specified in the LUT.
> +	 */
> +	qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
> +		    base + QUADSPI_IPCR);
> +
> +	/* Wait for the interrupt. */
> +	if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000)))
> +		err = -ETIMEDOUT;
> +
> +	if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
> +		fsl_qspi_read_rxfifo(q, op);
> +
> +	return err;
> +}
> +
> +static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
> +				    u32 mask, u32 delay_us, u32 timeout_us) {
> +	u32 reg;
> +
> +	if (!q->devtype_data->little_endian)
> +		mask = (u32)cpu_to_be32(mask);
> +
> +	return readl_poll_timeout(base, reg, !(reg & mask), delay_us,
> +				  timeout_us);
> +}
> +
> +static int fsl_qspi_exec_op(struct spi_mem *mem, const struct
> +spi_mem_op *op) {
> +	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
> +	void __iomem *base = q->iobase;
> +	u32 addr_offset = 0;
> +	int err = 0;
> +
> +	mutex_lock(&q->lock);
> +
> +	/* wait for the controller being ready */
> +	fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR,
> (QUADSPI_SR_IP_ACC_MASK |
> +				 QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
> +
> +	fsl_qspi_select_mem(q, mem->spi);
> +
> +	if (needs_amba_base_offset(q))
> +		addr_offset = q->memmap_phy;
> +
> +	qspi_writel(q,
> +		    q->selected * q->devtype_data->ahb_buf_size +
> addr_offset,
> +		    base + QUADSPI_SFAR);
> +
> +	qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
> +		    QUADSPI_MCR_CLR_RXF_MASK |
> QUADSPI_MCR_CLR_TXF_MASK,
> +		    base + QUADSPI_MCR);
> +
> +	qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC |
> QUADSPI_SPTRCLR_IPPTRC,
> +		    base + QUADSPI_SPTRCLR);
> +
> +	fsl_qspi_prepare_lut(q, op);
> +
> +	/*
> +	 * If we have large chunks of data, we read them through the AHB
> bus
> +	 * by accessing the mapped memory. In all other cases we use
> +	 * IP commands to access the flash.
> +	 */
> +	if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
> +	    op->data.dir == SPI_MEM_DATA_IN) {
> +		fsl_qspi_read_ahb(q, op);
> +	} else {
> +		qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
> +			    QUADSPI_RBCT_RXBRD_USEIPS, base +
> QUADSPI_RBCT);
> +
> +		if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
> +			fsl_qspi_fill_txfifo(q, op);
> +
> +		err = fsl_qspi_do_op(q, op);
> +	}
> +
> +	/* Invalidate the data in the AHB buffer. */
> +	fsl_qspi_invalidate(q);
> +
> +	mutex_unlock(&q->lock);
> +
> +	return err;
> +}
> +
> +static int fsl_qspi_adjust_op_size(struct spi_mem *mem, struct
> +spi_mem_op *op) {
> +	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
> +
> +	if (op->data.dir == SPI_MEM_DATA_OUT) {
> +		if (op->data.nbytes > q->devtype_data->txfifo)
> +			op->data.nbytes = q->devtype_data->txfifo;
> +	} else {
> +		if (op->data.nbytes > q->devtype_data->ahb_buf_size)
> +			op->data.nbytes = q->devtype_data->ahb_buf_size;
> +		else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
> +			op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
> +	}
> +
> +	return 0;
> +}
> +
> +static int fsl_qspi_default_setup(struct fsl_qspi *q) {
> +	void __iomem *base = q->iobase;
> +	u32 reg, addr_offset = 0;
> +	int ret;
> +
> +	/* disable and unprepare clock to avoid glitch pass to controller */
> +	fsl_qspi_clk_disable_unprep(q);
> +
> +	/* the default frequency, we will change it later if necessary. */
> +	ret = clk_set_rate(q->clk, 66000000);
> +	if (ret)
> +		return ret;
> +
> +	ret = fsl_qspi_clk_prep_enable(q);
> +	if (ret)
> +		return ret;
> +
> +	/* Reset the module */
> +	qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK |
> QUADSPI_MCR_SWRSTHD_MASK,
> +		    base + QUADSPI_MCR);
> +	udelay(1);
> +
> +	/* Disable the module */
> +	qspi_writel(q, QUADSPI_MCR_MDIS_MASK |
> QUADSPI_MCR_RESERVED_MASK,
> +		    base + QUADSPI_MCR);
> +
> +	reg = qspi_readl(q, base + QUADSPI_SMPR);
> +	qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
> +			| QUADSPI_SMPR_FSPHS_MASK
> +			| QUADSPI_SMPR_HSENA_MASK
> +			| QUADSPI_SMPR_DDRSMP_MASK), base +
> QUADSPI_SMPR);
> +
> +	/* We only use the buffer3 for AHB read */
> +	qspi_writel(q, 0, base + QUADSPI_BUF0IND);
> +	qspi_writel(q, 0, base + QUADSPI_BUF1IND);
> +	qspi_writel(q, 0, base + QUADSPI_BUF2IND);
> +
> +	qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
> +		    q->iobase + QUADSPI_BFGENCR);
> +	qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
> +	qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
> +		    QUADSPI_BUF3CR_ADATSZ(q->devtype_data-
> >ahb_buf_size / 8),
> +		    base + QUADSPI_BUF3CR);
> +
> +	if (needs_amba_base_offset(q))
> +		addr_offset = q->memmap_phy;
> +
> +	/*
> +	 * In HW there can be a maximum of four chips on two buses with
> +	 * two chip selects on each bus. We use four chip selects in SW
> +	 * to differentiate between the four chips.
> +	 * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD,
> SFB1AD,
> +	 * SFB2AD accordingly.
> +	 */
> +	qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
> +		    base + QUADSPI_SFA1AD);
> +	qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
> +		    base + QUADSPI_SFA2AD);
> +	qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
> +		    base + QUADSPI_SFB1AD);
> +	qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
> +		    base + QUADSPI_SFB2AD);
> +
> +	q->selected = -1;
> +
> +	/* Enable the module */
> +	qspi_writel(q, QUADSPI_MCR_RESERVED_MASK |
> QUADSPI_MCR_END_CFG_MASK,
> +		    base + QUADSPI_MCR);
> +
> +	/* clear all interrupt status */
> +	qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
> +
> +	/* enable the interrupt */
> +	qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
> +
> +	return 0;
> +}
> +
> +static const char *fsl_qspi_get_name(struct spi_mem *mem) {
> +	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
> +	struct device *dev = &mem->spi->dev;
> +	const char *name;
> +
> +	/*
> +	 * In order to keep mtdparts compatible with the old MTD driver at
> +	 * mtd/spi-nor/fsl-quadspi.c, we set a custom name derived from the
> +	 * platform_device of the controller.
> +	 */
> +	if (of_get_available_child_count(q->dev->of_node) == 1)
> +		return dev_name(q->dev);
> +
> +	name = devm_kasprintf(dev, GFP_KERNEL,
> +			      "%s-%d", dev_name(q->dev),
> +			      mem->spi->chip_select);
> +
> +	if (!name) {
> +		dev_err(dev, "failed to get memory for custom flash
> name\n");
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> +	return name;
> +}
> +
> +static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
> +	.adjust_op_size = fsl_qspi_adjust_op_size,
> +	.supports_op = fsl_qspi_supports_op,
> +	.exec_op = fsl_qspi_exec_op,
> +	.get_name = fsl_qspi_get_name,
> +};
> +
> +static int fsl_qspi_probe(struct platform_device *pdev) {
> +	struct spi_controller *ctlr;
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
> +	struct resource *res;
> +	struct fsl_qspi *q;
> +	int ret;
> +
> +	ctlr = spi_alloc_master(&pdev->dev, sizeof(*q));
> +	if (!ctlr)
> +		return -ENOMEM;
> +
> +	ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
> +			  SPI_TX_DUAL | SPI_TX_QUAD;
> +
> +	q = spi_controller_get_devdata(ctlr);
> +	q->dev = dev;
> +	q->devtype_data = of_device_get_match_data(dev);
> +	if (!q->devtype_data) {
> +		ret = -ENODEV;
> +		goto err_put_ctrl;
> +	}
> +
> +	platform_set_drvdata(pdev, q);
> +
> +	/* find the resources */
> +	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> "QuadSPI");
> +	q->iobase = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(q->iobase)) {
> +		ret = PTR_ERR(q->iobase);
> +		goto err_put_ctrl;
> +	}
> +
> +	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> +					"QuadSPI-memory");
> +	q->ahb_addr = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(q->ahb_addr)) {
> +		ret = PTR_ERR(q->ahb_addr);
> +		goto err_put_ctrl;
> +	}
> +
> +	q->memmap_phy = res->start;
> +
> +	/* find the clocks */
> +	q->clk_en = devm_clk_get(dev, "qspi_en");
> +	if (IS_ERR(q->clk_en)) {
> +		ret = PTR_ERR(q->clk_en);
> +		goto err_put_ctrl;
> +	}
> +
> +	q->clk = devm_clk_get(dev, "qspi");
> +	if (IS_ERR(q->clk)) {
> +		ret = PTR_ERR(q->clk);
> +		goto err_put_ctrl;
> +	}
> +
> +	ret = fsl_qspi_clk_prep_enable(q);
> +	if (ret) {
> +		dev_err(dev, "can not enable the clock\n");
> +		goto err_put_ctrl;
> +	}
> +
> +	/* find the irq */
> +	ret = platform_get_irq(pdev, 0);
> +	if (ret < 0) {
> +		dev_err(dev, "failed to get the irq: %d\n", ret);
> +		goto err_disable_clk;
> +	}
> +
> +	ret = devm_request_irq(dev, ret,
> +			fsl_qspi_irq_handler, 0, pdev->name, q);
> +	if (ret) {
> +		dev_err(dev, "failed to request irq: %d\n", ret);
> +		goto err_disable_clk;
> +	}
> +
> +	mutex_init(&q->lock);
> +
> +	ctlr->bus_num = -1;
> +	ctlr->num_chipselect = 4;
> +	ctlr->mem_ops = &fsl_qspi_mem_ops;
> +
> +	fsl_qspi_default_setup(q);
> +
> +	ctlr->dev.of_node = np;
> +
> +	ret = spi_register_controller(ctlr);
> +	if (ret)
> +		goto err_destroy_mutex;
> +
> +	return 0;
> +
> +err_destroy_mutex:
> +	mutex_destroy(&q->lock);
> +
> +err_disable_clk:
> +	fsl_qspi_clk_disable_unprep(q);
> +
> +err_put_ctrl:
> +	spi_controller_put(ctlr);
> +
> +	dev_err(dev, "Freescale QuadSPI probe failed\n");
> +	return ret;
> +}
> +
> +static int fsl_qspi_remove(struct platform_device *pdev) {
> +	struct fsl_qspi *q = platform_get_drvdata(pdev);
> +
> +	/* disable the hardware */
> +	qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase +
> QUADSPI_MCR);
> +	qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
> +
> +	fsl_qspi_clk_disable_unprep(q);
> +
> +	mutex_destroy(&q->lock);
> +
> +	return 0;
> +}
> +
> +static int fsl_qspi_suspend(struct device *dev) {
> +	return 0;
> +}
> +
> +static int fsl_qspi_resume(struct device *dev) {
> +	struct fsl_qspi *q = dev_get_drvdata(dev);
> +
> +	fsl_qspi_default_setup(q);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id fsl_qspi_dt_ids[] = {
> +	{ .compatible = "fsl,vf610-qspi", .data = &vybrid_data, },
> +	{ .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, },
> +	{ .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, },
> +	{ .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
> +	{ .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, },
> +	{ .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
> +
> +static const struct dev_pm_ops fsl_qspi_pm_ops = {
> +	.suspend	= fsl_qspi_suspend,
> +	.resume		= fsl_qspi_resume,
> +};
> +
> +static struct platform_driver fsl_qspi_driver = {
> +	.driver = {
> +		.name	= "fsl-quadspi",
> +		.of_match_table = fsl_qspi_dt_ids,
> +		.pm =   &fsl_qspi_pm_ops,
> +	},
> +	.probe          = fsl_qspi_probe,
> +	.remove		= fsl_qspi_remove,
> +};
> +module_platform_driver(fsl_qspi_driver);
> +
> +MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
> +MODULE_AUTHOR("Freescale Semiconductor Inc.");
> MODULE_AUTHOR("Boris
> +Brezillion <boris.brezillon@bootlin.com>"); MODULE_AUTHOR("Frieder
> +Schrempf <frieder.schrempf@kontron.de>"); MODULE_AUTHOR("Yogesh
> Gaur
> +<yogeshnarayan.gaur@nxp.com>"); MODULE_AUTHOR("Suresh Gupta
> +<suresh.gupta@nxp.com>"); MODULE_LICENSE("GPL v2");
> --
> 2.7.4

Acked-by: Han Xu <han.xu@nxp.com>
Tested-by: Han Xu <han.xu@nxp.com>

[PATCH v7 4/9] dt-bindings: spi: Move the bindings for the FSL QSPI driver

[Schrempf Frieder]

From: Frieder Schrempf <frieder.schrempf@kontron.de>

Move the documentation of the old SPI NOR driver to the place of the new
SPI memory interface based driver.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../bindings/{mtd/fsl-quadspi.txt => spi/spi-fsl-qspi.txt}           | 0
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt
similarity index 100%
rename from Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
rename to Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt
-- 
2.7.4

[PATCH v7 5/9] dt-bindings: spi: Adjust the bindings for the FSL QSPI driver

[Schrempf Frieder]

From: Frieder Schrempf <frieder.schrempf@kontron.de>

Adjust the documentation of the new SPI memory interface based
driver to reflect the new drivers settings.

The "old" driver was using the "fsl,qspi-has-second-chip" property to
select one of two dual chip setups (two chips on one bus or two chips
on separate buses). And it used the order in which the subnodes are
defined in the dt to select the CS, the chip is connected to.

Both methods are wrong and in fact the "reg" property should be used to
determine which bus and CS a chip is connected to. This also enables us
to use different setups than just single chip, or symmetric dual chip.

So the porting of the driver from the MTD to the SPI framework actually
enforces the use of the "reg" properties and makes
"fsl,qspi-has-second-chip" superfluous.

As all boards that have "fsl,qspi-has-second-chip" set, also have
correct "reg" properties, the removal of this property shouldn't lead to
any incompatibilities.

The only compatibility issues I can see are with imx6sx-sdb.dts and
imx6sx-sdb-reva.dts, which have their reg properties set incorrectly
(see explanation here: [2]), all other boards should stay compatible.

Also the "big-endian" flag was removed, as this setting is now selected
by the driver, depending on which SoC is in use.

[2] https://patchwork.ozlabs.org/patch/922817/#1925445

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/spi/spi-fsl-qspi.txt      | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt
index 483e9cf..e8f1d62 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt
@@ -14,15 +14,13 @@ Required properties:
   - clocks : The clocks needed by the QuadSPI controller
   - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi".
 
-Optional properties:
-  - fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B.
-                              Each bus can be connected with two NOR flashes.
-			      Most of the time, each bus only has one NOR flash
-			      connected, this is the default case.
-			      But if there are two NOR flashes connected to the
-			      bus, you should enable this property.
-			      (Please check the board's schematic.)
-  - big-endian : That means the IP register is big endian
+Required SPI slave node properties:
+  - reg: There are two buses (A and B) with two chip selects each.
+	 This encodes to which bus and CS the flash is connected:
+		<0>: Bus A, CS 0
+		<1>: Bus A, CS 1
+		<2>: Bus B, CS 0
+		<3>: Bus B, CS 1
 
 Example:
 
@@ -40,7 +38,7 @@ qspi0: quadspi@40044000 {
 	};
 };
 
-Example showing the usage of two SPI NOR devices:
+Example showing the usage of two SPI NOR devices on bus A:
 
 &qspi2 {
 	pinctrl-names = "default";
-- 
2.7.4

[PATCH v7 6/9] mtd: fsl-quadspi: Remove the driver as it was replaced by spi-fsl-qspi.c

[Schrempf Frieder]

From: Frieder Schrempf <frieder.schrempf@kontron.de>

There's a new driver using the SPI memory interface of the SPI framework
at spi/spi-fsl-qspi.c, which can be used together with m25p80.c to
replace the functionality of this SPI NOR driver.

The new driver is already in use and this code is not compiled anymore,
so let's remove it.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 1224 --------------------------------
 1 file changed, 1224 deletions(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
deleted file mode 100644
index 1ff3430..0000000
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ /dev/null
@@ -1,1224 +0,0 @@
-/*
- * Freescale QuadSPI driver.
- *
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/errno.h>
-#include <linux/platform_device.h>
-#include <linux/sched.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/timer.h>
-#include <linux/jiffies.h>
-#include <linux/completion.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/spi-nor.h>
-#include <linux/mutex.h>
-#include <linux/pm_qos.h>
-#include <linux/sizes.h>
-
-/* Controller needs driver to swap endian */
-#define QUADSPI_QUIRK_SWAP_ENDIAN	(1 << 0)
-/* Controller needs 4x internal clock */
-#define QUADSPI_QUIRK_4X_INT_CLK	(1 << 1)
-/*
- * TKT253890, Controller needs driver to fill txfifo till 16 byte to
- * trigger data transfer even though extern data will not transferred.
- */
-#define QUADSPI_QUIRK_TKT253890		(1 << 2)
-/* Controller cannot wake up from wait mode, TKT245618 */
-#define QUADSPI_QUIRK_TKT245618         (1 << 3)
-
-/* The registers */
-#define QUADSPI_MCR			0x00
-#define QUADSPI_MCR_RESERVED_SHIFT	16
-#define QUADSPI_MCR_RESERVED_MASK	(0xF << QUADSPI_MCR_RESERVED_SHIFT)
-#define QUADSPI_MCR_MDIS_SHIFT		14
-#define QUADSPI_MCR_MDIS_MASK		(1 << QUADSPI_MCR_MDIS_SHIFT)
-#define QUADSPI_MCR_CLR_TXF_SHIFT	11
-#define QUADSPI_MCR_CLR_TXF_MASK	(1 << QUADSPI_MCR_CLR_TXF_SHIFT)
-#define QUADSPI_MCR_CLR_RXF_SHIFT	10
-#define QUADSPI_MCR_CLR_RXF_MASK	(1 << QUADSPI_MCR_CLR_RXF_SHIFT)
-#define QUADSPI_MCR_DDR_EN_SHIFT	7
-#define QUADSPI_MCR_DDR_EN_MASK		(1 << QUADSPI_MCR_DDR_EN_SHIFT)
-#define QUADSPI_MCR_END_CFG_SHIFT	2
-#define QUADSPI_MCR_END_CFG_MASK	(3 << QUADSPI_MCR_END_CFG_SHIFT)
-#define QUADSPI_MCR_SWRSTHD_SHIFT	1
-#define QUADSPI_MCR_SWRSTHD_MASK	(1 << QUADSPI_MCR_SWRSTHD_SHIFT)
-#define QUADSPI_MCR_SWRSTSD_SHIFT	0
-#define QUADSPI_MCR_SWRSTSD_MASK	(1 << QUADSPI_MCR_SWRSTSD_SHIFT)
-
-#define QUADSPI_IPCR			0x08
-#define QUADSPI_IPCR_SEQID_SHIFT	24
-#define QUADSPI_IPCR_SEQID_MASK		(0xF << QUADSPI_IPCR_SEQID_SHIFT)
-
-#define QUADSPI_BUF0CR			0x10
-#define QUADSPI_BUF1CR			0x14
-#define QUADSPI_BUF2CR			0x18
-#define QUADSPI_BUFXCR_INVALID_MSTRID	0xe
-
-#define QUADSPI_BUF3CR			0x1c
-#define QUADSPI_BUF3CR_ALLMST_SHIFT	31
-#define QUADSPI_BUF3CR_ALLMST_MASK	(1 << QUADSPI_BUF3CR_ALLMST_SHIFT)
-#define QUADSPI_BUF3CR_ADATSZ_SHIFT		8
-#define QUADSPI_BUF3CR_ADATSZ_MASK	(0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
-
-#define QUADSPI_BFGENCR			0x20
-#define QUADSPI_BFGENCR_PAR_EN_SHIFT	16
-#define QUADSPI_BFGENCR_PAR_EN_MASK	(1 << (QUADSPI_BFGENCR_PAR_EN_SHIFT))
-#define QUADSPI_BFGENCR_SEQID_SHIFT	12
-#define QUADSPI_BFGENCR_SEQID_MASK	(0xF << QUADSPI_BFGENCR_SEQID_SHIFT)
-
-#define QUADSPI_BUF0IND			0x30
-#define QUADSPI_BUF1IND			0x34
-#define QUADSPI_BUF2IND			0x38
-#define QUADSPI_SFAR			0x100
-
-#define QUADSPI_SMPR			0x108
-#define QUADSPI_SMPR_DDRSMP_SHIFT	16
-#define QUADSPI_SMPR_DDRSMP_MASK	(7 << QUADSPI_SMPR_DDRSMP_SHIFT)
-#define QUADSPI_SMPR_FSDLY_SHIFT	6
-#define QUADSPI_SMPR_FSDLY_MASK		(1 << QUADSPI_SMPR_FSDLY_SHIFT)
-#define QUADSPI_SMPR_FSPHS_SHIFT	5
-#define QUADSPI_SMPR_FSPHS_MASK		(1 << QUADSPI_SMPR_FSPHS_SHIFT)
-#define QUADSPI_SMPR_HSENA_SHIFT	0
-#define QUADSPI_SMPR_HSENA_MASK		(1 << QUADSPI_SMPR_HSENA_SHIFT)
-
-#define QUADSPI_RBSR			0x10c
-#define QUADSPI_RBSR_RDBFL_SHIFT	8
-#define QUADSPI_RBSR_RDBFL_MASK		(0x3F << QUADSPI_RBSR_RDBFL_SHIFT)
-
-#define QUADSPI_RBCT			0x110
-#define QUADSPI_RBCT_WMRK_MASK		0x1F
-#define QUADSPI_RBCT_RXBRD_SHIFT	8
-#define QUADSPI_RBCT_RXBRD_USEIPS	(0x1 << QUADSPI_RBCT_RXBRD_SHIFT)
-
-#define QUADSPI_TBSR			0x150
-#define QUADSPI_TBDR			0x154
-#define QUADSPI_SR			0x15c
-#define QUADSPI_SR_IP_ACC_SHIFT		1
-#define QUADSPI_SR_IP_ACC_MASK		(0x1 << QUADSPI_SR_IP_ACC_SHIFT)
-#define QUADSPI_SR_AHB_ACC_SHIFT	2
-#define QUADSPI_SR_AHB_ACC_MASK		(0x1 << QUADSPI_SR_AHB_ACC_SHIFT)
-
-#define QUADSPI_FR			0x160
-#define QUADSPI_FR_TFF_MASK		0x1
-
-#define QUADSPI_SFA1AD			0x180
-#define QUADSPI_SFA2AD			0x184
-#define QUADSPI_SFB1AD			0x188
-#define QUADSPI_SFB2AD			0x18c
-#define QUADSPI_RBDR			0x200
-
-#define QUADSPI_LUTKEY			0x300
-#define QUADSPI_LUTKEY_VALUE		0x5AF05AF0
-
-#define QUADSPI_LCKCR			0x304
-#define QUADSPI_LCKER_LOCK		0x1
-#define QUADSPI_LCKER_UNLOCK		0x2
-
-#define QUADSPI_RSER			0x164
-#define QUADSPI_RSER_TFIE		(0x1 << 0)
-
-#define QUADSPI_LUT_BASE		0x310
-
-/*
- * The definition of the LUT register shows below:
- *
- *  ---------------------------------------------------
- *  | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
- *  ---------------------------------------------------
- */
-#define OPRND0_SHIFT		0
-#define PAD0_SHIFT		8
-#define INSTR0_SHIFT		10
-#define OPRND1_SHIFT		16
-
-/* Instruction set for the LUT register. */
-#define LUT_STOP		0
-#define LUT_CMD			1
-#define LUT_ADDR		2
-#define LUT_DUMMY		3
-#define LUT_MODE		4
-#define LUT_MODE2		5
-#define LUT_MODE4		6
-#define LUT_FSL_READ		7
-#define LUT_FSL_WRITE		8
-#define LUT_JMP_ON_CS		9
-#define LUT_ADDR_DDR		10
-#define LUT_MODE_DDR		11
-#define LUT_MODE2_DDR		12
-#define LUT_MODE4_DDR		13
-#define LUT_FSL_READ_DDR		14
-#define LUT_FSL_WRITE_DDR		15
-#define LUT_DATA_LEARN		16
-
-/*
- * The PAD definitions for LUT register.
- *
- * The pad stands for the lines number of IO[0:3].
- * For example, the Quad read need four IO lines, so you should
- * set LUT_PAD4 which means we use four IO lines.
- */
-#define LUT_PAD1		0
-#define LUT_PAD2		1
-#define LUT_PAD4		2
-
-/* Oprands for the LUT register. */
-#define ADDR24BIT		0x18
-#define ADDR32BIT		0x20
-
-/* Macros for constructing the LUT register. */
-#define LUT0(ins, pad, opr)						\
-		(((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
-		((LUT_##ins) << INSTR0_SHIFT))
-
-#define LUT1(ins, pad, opr)	(LUT0(ins, pad, opr) << OPRND1_SHIFT)
-
-/* other macros for LUT register. */
-#define QUADSPI_LUT(x)          (QUADSPI_LUT_BASE + (x) * 4)
-#define QUADSPI_LUT_NUM		64
-
-/* SEQID -- we can have 16 seqids at most. */
-#define SEQID_READ		0
-#define SEQID_WREN		1
-#define SEQID_WRDI		2
-#define SEQID_RDSR		3
-#define SEQID_SE		4
-#define SEQID_CHIP_ERASE	5
-#define SEQID_PP		6
-#define SEQID_RDID		7
-#define SEQID_WRSR		8
-#define SEQID_RDCR		9
-#define SEQID_EN4B		10
-#define SEQID_BRWR		11
-
-#define QUADSPI_MIN_IOMAP SZ_4M
-
-enum fsl_qspi_devtype {
-	FSL_QUADSPI_VYBRID,
-	FSL_QUADSPI_IMX6SX,
-	FSL_QUADSPI_IMX7D,
-	FSL_QUADSPI_IMX6UL,
-	FSL_QUADSPI_LS1021A,
-	FSL_QUADSPI_LS2080A,
-};
-
-struct fsl_qspi_devtype_data {
-	enum fsl_qspi_devtype devtype;
-	int rxfifo;
-	int txfifo;
-	int ahb_buf_size;
-	int driver_data;
-};
-
-static const struct fsl_qspi_devtype_data vybrid_data = {
-	.devtype = FSL_QUADSPI_VYBRID,
-	.rxfifo = 128,
-	.txfifo = 64,
-	.ahb_buf_size = 1024,
-	.driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
-};
-
-static const struct fsl_qspi_devtype_data imx6sx_data = {
-	.devtype = FSL_QUADSPI_IMX6SX,
-	.rxfifo = 128,
-	.txfifo = 512,
-	.ahb_buf_size = 1024,
-	.driver_data = QUADSPI_QUIRK_4X_INT_CLK
-		       | QUADSPI_QUIRK_TKT245618,
-};
-
-static const struct fsl_qspi_devtype_data imx7d_data = {
-	.devtype = FSL_QUADSPI_IMX7D,
-	.rxfifo = 512,
-	.txfifo = 512,
-	.ahb_buf_size = 1024,
-	.driver_data = QUADSPI_QUIRK_TKT253890
-		       | QUADSPI_QUIRK_4X_INT_CLK,
-};
-
-static const struct fsl_qspi_devtype_data imx6ul_data = {
-	.devtype = FSL_QUADSPI_IMX6UL,
-	.rxfifo = 128,
-	.txfifo = 512,
-	.ahb_buf_size = 1024,
-	.driver_data = QUADSPI_QUIRK_TKT253890
-		       | QUADSPI_QUIRK_4X_INT_CLK,
-};
-
-static struct fsl_qspi_devtype_data ls1021a_data = {
-	.devtype = FSL_QUADSPI_LS1021A,
-	.rxfifo = 128,
-	.txfifo = 64,
-	.ahb_buf_size = 1024,
-	.driver_data = 0,
-};
-
-static const struct fsl_qspi_devtype_data ls2080a_data = {
-	.devtype = FSL_QUADSPI_LS2080A,
-	.rxfifo = 128,
-	.txfifo = 64,
-	.ahb_buf_size = 1024,
-	.driver_data = QUADSPI_QUIRK_TKT253890,
-};
-
-
-#define FSL_QSPI_MAX_CHIP	4
-struct fsl_qspi {
-	struct spi_nor nor[FSL_QSPI_MAX_CHIP];
-	void __iomem *iobase;
-	void __iomem *ahb_addr;
-	u32 memmap_phy;
-	u32 memmap_offs;
-	u32 memmap_len;
-	struct clk *clk, *clk_en;
-	struct device *dev;
-	struct completion c;
-	const struct fsl_qspi_devtype_data *devtype_data;
-	u32 nor_size;
-	u32 nor_num;
-	u32 clk_rate;
-	unsigned int chip_base_addr; /* We may support two chips. */
-	bool has_second_chip;
-	bool big_endian;
-	struct mutex lock;
-	struct pm_qos_request pm_qos_req;
-};
-
-static inline int needs_swap_endian(struct fsl_qspi *q)
-{
-	return q->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN;
-}
-
-static inline int needs_4x_clock(struct fsl_qspi *q)
-{
-	return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK;
-}
-
-static inline int needs_fill_txfifo(struct fsl_qspi *q)
-{
-	return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890;
-}
-
-static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
-{
-	return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
-}
-
-/*
- * R/W functions for big- or little-endian registers:
- * The qSPI controller's endian is independent of the CPU core's endian.
- * So far, although the CPU core is little-endian but the qSPI have two
- * versions for big-endian and little-endian.
- */
-static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
-{
-	if (q->big_endian)
-		iowrite32be(val, addr);
-	else
-		iowrite32(val, addr);
-}
-
-static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
-{
-	if (q->big_endian)
-		return ioread32be(addr);
-	else
-		return ioread32(addr);
-}
-
-/*
- * An IC bug makes us to re-arrange the 32-bit data.
- * The following chips, such as IMX6SLX, have fixed this bug.
- */
-static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
-{
-	return needs_swap_endian(q) ? __swab32(a) : a;
-}
-
-static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
-{
-	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-	qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
-}
-
-static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
-{
-	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-	qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
-}
-
-static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
-{
-	struct fsl_qspi *q = dev_id;
-	u32 reg;
-
-	/* clear interrupt */
-	reg = qspi_readl(q, q->iobase + QUADSPI_FR);
-	qspi_writel(q, reg, q->iobase + QUADSPI_FR);
-
-	if (reg & QUADSPI_FR_TFF_MASK)
-		complete(&q->c);
-
-	dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q->chip_base_addr, reg);
-	return IRQ_HANDLED;
-}
-
-static void fsl_qspi_init_lut(struct fsl_qspi *q)
-{
-	void __iomem *base = q->iobase;
-	int rxfifo = q->devtype_data->rxfifo;
-	u32 lut_base;
-	int i;
-
-	struct spi_nor *nor = &q->nor[0];
-	u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
-	u8 read_op = nor->read_opcode;
-	u8 read_dm = nor->read_dummy;
-
-	fsl_qspi_unlock_lut(q);
-
-	/* Clear all the LUT table */
-	for (i = 0; i < QUADSPI_LUT_NUM; i++)
-		qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
-
-	/* Read */
-	lut_base = SEQID_READ * 4;
-
-	qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
-			base + QUADSPI_LUT(lut_base));
-	qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
-		    LUT1(FSL_READ, PAD4, rxfifo),
-			base + QUADSPI_LUT(lut_base + 1));
-
-	/* Write enable */
-	lut_base = SEQID_WREN * 4;
-	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
-			base + QUADSPI_LUT(lut_base));
-
-	/* Page Program */
-	lut_base = SEQID_PP * 4;
-
-	qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
-		    LUT1(ADDR, PAD1, addrlen),
-			base + QUADSPI_LUT(lut_base));
-	qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
-			base + QUADSPI_LUT(lut_base + 1));
-
-	/* Read Status */
-	lut_base = SEQID_RDSR * 4;
-	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
-			LUT1(FSL_READ, PAD1, 0x1),
-			base + QUADSPI_LUT(lut_base));
-
-	/* Erase a sector */
-	lut_base = SEQID_SE * 4;
-
-	qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
-		    LUT1(ADDR, PAD1, addrlen),
-			base + QUADSPI_LUT(lut_base));
-
-	/* Erase the whole chip */
-	lut_base = SEQID_CHIP_ERASE * 4;
-	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
-			base + QUADSPI_LUT(lut_base));
-
-	/* READ ID */
-	lut_base = SEQID_RDID * 4;
-	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDID) |
-			LUT1(FSL_READ, PAD1, 0x8),
-			base + QUADSPI_LUT(lut_base));
-
-	/* Write Register */
-	lut_base = SEQID_WRSR * 4;
-	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRSR) |
-			LUT1(FSL_WRITE, PAD1, 0x2),
-			base + QUADSPI_LUT(lut_base));
-
-	/* Read Configuration Register */
-	lut_base = SEQID_RDCR * 4;
-	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDCR) |
-			LUT1(FSL_READ, PAD1, 0x1),
-			base + QUADSPI_LUT(lut_base));
-
-	/* Write disable */
-	lut_base = SEQID_WRDI * 4;
-	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRDI),
-			base + QUADSPI_LUT(lut_base));
-
-	/* Enter 4 Byte Mode (Micron) */
-	lut_base = SEQID_EN4B * 4;
-	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_EN4B),
-			base + QUADSPI_LUT(lut_base));
-
-	/* Enter 4 Byte Mode (Spansion) */
-	lut_base = SEQID_BRWR * 4;
-	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
-			base + QUADSPI_LUT(lut_base));
-
-	fsl_qspi_lock_lut(q);
-}
-
-/* Get the SEQID for the command */
-static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
-{
-	switch (cmd) {
-	case SPINOR_OP_READ_1_1_4:
-	case SPINOR_OP_READ_1_1_4_4B:
-		return SEQID_READ;
-	case SPINOR_OP_WREN:
-		return SEQID_WREN;
-	case SPINOR_OP_WRDI:
-		return SEQID_WRDI;
-	case SPINOR_OP_RDSR:
-		return SEQID_RDSR;
-	case SPINOR_OP_SE:
-		return SEQID_SE;
-	case SPINOR_OP_CHIP_ERASE:
-		return SEQID_CHIP_ERASE;
-	case SPINOR_OP_PP:
-		return SEQID_PP;
-	case SPINOR_OP_RDID:
-		return SEQID_RDID;
-	case SPINOR_OP_WRSR:
-		return SEQID_WRSR;
-	case SPINOR_OP_RDCR:
-		return SEQID_RDCR;
-	case SPINOR_OP_EN4B:
-		return SEQID_EN4B;
-	case SPINOR_OP_BRWR:
-		return SEQID_BRWR;
-	default:
-		if (cmd == q->nor[0].erase_opcode)
-			return SEQID_SE;
-		dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
-		break;
-	}
-	return -EINVAL;
-}
-
-static int
-fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
-{
-	void __iomem *base = q->iobase;
-	int seqid;
-	u32 reg, reg2;
-	int err;
-
-	init_completion(&q->c);
-	dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
-			q->chip_base_addr, addr, len, cmd);
-
-	/* save the reg */
-	reg = qspi_readl(q, base + QUADSPI_MCR);
-
-	qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
-			base + QUADSPI_SFAR);
-	qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
-			base + QUADSPI_RBCT);
-	qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
-
-	do {
-		reg2 = qspi_readl(q, base + QUADSPI_SR);
-		if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
-			udelay(1);
-			dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
-			continue;
-		}
-		break;
-	} while (1);
-
-	/* trigger the LUT now */
-	seqid = fsl_qspi_get_seqid(q, cmd);
-	if (seqid < 0)
-		return seqid;
-
-	qspi_writel(q, (seqid << QUADSPI_IPCR_SEQID_SHIFT) | len,
-			base + QUADSPI_IPCR);
-
-	/* Wait for the interrupt. */
-	if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) {
-		dev_err(q->dev,
-			"cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
-			cmd, addr, qspi_readl(q, base + QUADSPI_FR),
-			qspi_readl(q, base + QUADSPI_SR));
-		err = -ETIMEDOUT;
-	} else {
-		err = 0;
-	}
-
-	/* restore the MCR */
-	qspi_writel(q, reg, base + QUADSPI_MCR);
-
-	return err;
-}
-
-/* Read out the data from the QUADSPI_RBDR buffer registers. */
-static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
-{
-	u32 tmp;
-	int i = 0;
-
-	while (len > 0) {
-		tmp = qspi_readl(q, q->iobase + QUADSPI_RBDR + i * 4);
-		tmp = fsl_qspi_endian_xchg(q, tmp);
-		dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
-				q->chip_base_addr, tmp);
-
-		if (len >= 4) {
-			*((u32 *)rxbuf) = tmp;
-			rxbuf += 4;
-		} else {
-			memcpy(rxbuf, &tmp, len);
-			break;
-		}
-
-		len -= 4;
-		i++;
-	}
-}
-
-/*
- * If we have changed the content of the flash by writing or erasing,
- * we need to invalidate the AHB buffer. If we do not do so, we may read out
- * the wrong data. The spec tells us reset the AHB domain and Serial Flash
- * domain at the same time.
- */
-static inline void fsl_qspi_invalid(struct fsl_qspi *q)
-{
-	u32 reg;
-
-	reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
-	reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
-	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
-
-	/*
-	 * The minimum delay : 1 AHB + 2 SFCK clocks.
-	 * Delay 1 us is enough.
-	 */
-	udelay(1);
-
-	reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
-	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
-}
-
-static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
-				u8 opcode, unsigned int to, u32 *txbuf,
-				unsigned count)
-{
-	int ret, i, j;
-	u32 tmp;
-
-	dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
-		q->chip_base_addr, to, count);
-
-	/* clear the TX FIFO. */
-	tmp = qspi_readl(q, q->iobase + QUADSPI_MCR);
-	qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
-
-	/* fill the TX data to the FIFO */
-	for (j = 0, i = ((count + 3) / 4); j < i; j++) {
-		tmp = fsl_qspi_endian_xchg(q, *txbuf);
-		qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
-		txbuf++;
-	}
-
-	/* fill the TXFIFO upto 16 bytes for i.MX7d */
-	if (needs_fill_txfifo(q))
-		for (; i < 4; i++)
-			qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
-
-	/* Trigger it */
-	ret = fsl_qspi_runcmd(q, opcode, to, count);
-
-	if (ret == 0)
-		return count;
-
-	return ret;
-}
-
-static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
-{
-	int nor_size = q->nor_size;
-	void __iomem *base = q->iobase;
-
-	qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
-	qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
-	qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
-	qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
-}
-
-/*
- * There are two different ways to read out the data from the flash:
- *  the "IP Command Read" and the "AHB Command Read".
- *
- * The IC guy suggests we use the "AHB Command Read" which is faster
- * then the "IP Command Read". (What's more is that there is a bug in
- * the "IP Command Read" in the Vybrid.)
- *
- * After we set up the registers for the "AHB Command Read", we can use
- * the memcpy to read the data directly. A "missed" access to the buffer
- * causes the controller to clear the buffer, and use the sequence pointed
- * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
- */
-static int fsl_qspi_init_ahb_read(struct fsl_qspi *q)
-{
-	void __iomem *base = q->iobase;
-	int seqid;
-
-	/* AHB configuration for access buffer 0/1/2 .*/
-	qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
-	qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
-	qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
-	/*
-	 * Set ADATSZ with the maximum AHB buffer size to improve the
-	 * read performance.
-	 */
-	qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
-			((q->devtype_data->ahb_buf_size / 8)
-			<< QUADSPI_BUF3CR_ADATSZ_SHIFT),
-			base + QUADSPI_BUF3CR);
-
-	/* We only use the buffer3 */
-	qspi_writel(q, 0, base + QUADSPI_BUF0IND);
-	qspi_writel(q, 0, base + QUADSPI_BUF1IND);
-	qspi_writel(q, 0, base + QUADSPI_BUF2IND);
-
-	/* Set the default lut sequence for AHB Read. */
-	seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
-	if (seqid < 0)
-		return seqid;
-
-	qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
-		q->iobase + QUADSPI_BFGENCR);
-
-	return 0;
-}
-
-/* This function was used to prepare and enable QSPI clock */
-static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
-{
-	int ret;
-
-	ret = clk_prepare_enable(q->clk_en);
-	if (ret)
-		return ret;
-
-	ret = clk_prepare_enable(q->clk);
-	if (ret) {
-		clk_disable_unprepare(q->clk_en);
-		return ret;
-	}
-
-	if (needs_wakeup_wait_mode(q))
-		pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
-
-	return 0;
-}
-
-/* This function was used to disable and unprepare QSPI clock */
-static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
-{
-	if (needs_wakeup_wait_mode(q))
-		pm_qos_remove_request(&q->pm_qos_req);
-
-	clk_disable_unprepare(q->clk);
-	clk_disable_unprepare(q->clk_en);
-
-}
-
-/* We use this function to do some basic init for spi_nor_scan(). */
-static int fsl_qspi_nor_setup(struct fsl_qspi *q)
-{
-	void __iomem *base = q->iobase;
-	u32 reg;
-	int ret;
-
-	/* disable and unprepare clock to avoid glitch pass to controller */
-	fsl_qspi_clk_disable_unprep(q);
-
-	/* the default frequency, we will change it in the future. */
-	ret = clk_set_rate(q->clk, 66000000);
-	if (ret)
-		return ret;
-
-	ret = fsl_qspi_clk_prep_enable(q);
-	if (ret)
-		return ret;
-
-	/* Reset the module */
-	qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
-		base + QUADSPI_MCR);
-	udelay(1);
-
-	/* Init the LUT table. */
-	fsl_qspi_init_lut(q);
-
-	/* Disable the module */
-	qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
-			base + QUADSPI_MCR);
-
-	reg = qspi_readl(q, base + QUADSPI_SMPR);
-	qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
-			| QUADSPI_SMPR_FSPHS_MASK
-			| QUADSPI_SMPR_HSENA_MASK
-			| QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
-
-	/* Enable the module */
-	qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
-			base + QUADSPI_MCR);
-
-	/* clear all interrupt status */
-	qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
-
-	/* enable the interrupt */
-	qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
-
-	return 0;
-}
-
-static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
-{
-	unsigned long rate = q->clk_rate;
-	int ret;
-
-	if (needs_4x_clock(q))
-		rate *= 4;
-
-	/* disable and unprepare clock to avoid glitch pass to controller */
-	fsl_qspi_clk_disable_unprep(q);
-
-	ret = clk_set_rate(q->clk, rate);
-	if (ret)
-		return ret;
-
-	ret = fsl_qspi_clk_prep_enable(q);
-	if (ret)
-		return ret;
-
-	/* Init the LUT table again. */
-	fsl_qspi_init_lut(q);
-
-	/* Init for AHB read */
-	return fsl_qspi_init_ahb_read(q);
-}
-
-static const struct of_device_id fsl_qspi_dt_ids[] = {
-	{ .compatible = "fsl,vf610-qspi", .data = &vybrid_data, },
-	{ .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, },
-	{ .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, },
-	{ .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
-	{ .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
-	{ .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
-	{ /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
-
-static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor)
-{
-	q->chip_base_addr = q->nor_size * (nor - q->nor);
-}
-
-static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
-{
-	int ret;
-	struct fsl_qspi *q = nor->priv;
-
-	ret = fsl_qspi_runcmd(q, opcode, 0, len);
-	if (ret)
-		return ret;
-
-	fsl_qspi_read_data(q, len, buf);
-	return 0;
-}
-
-static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
-{
-	struct fsl_qspi *q = nor->priv;
-	int ret;
-
-	if (!buf) {
-		ret = fsl_qspi_runcmd(q, opcode, 0, 1);
-		if (ret)
-			return ret;
-
-		if (opcode == SPINOR_OP_CHIP_ERASE)
-			fsl_qspi_invalid(q);
-
-	} else if (len > 0) {
-		ret = fsl_qspi_nor_write(q, nor, opcode, 0,
-					(u32 *)buf, len);
-		if (ret > 0)
-			return 0;
-	} else {
-		dev_err(q->dev, "invalid cmd %d\n", opcode);
-		ret = -EINVAL;
-	}
-
-	return ret;
-}
-
-static ssize_t fsl_qspi_write(struct spi_nor *nor, loff_t to,
-			      size_t len, const u_char *buf)
-{
-	struct fsl_qspi *q = nor->priv;
-	ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
-					 (u32 *)buf, len);
-
-	/* invalid the data in the AHB buffer. */
-	fsl_qspi_invalid(q);
-	return ret;
-}
-
-static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from,
-			     size_t len, u_char *buf)
-{
-	struct fsl_qspi *q = nor->priv;
-	u8 cmd = nor->read_opcode;
-
-	/* if necessary,ioremap buffer before AHB read, */
-	if (!q->ahb_addr) {
-		q->memmap_offs = q->chip_base_addr + from;
-		q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
-
-		q->ahb_addr = ioremap_nocache(
-				q->memmap_phy + q->memmap_offs,
-				q->memmap_len);
-		if (!q->ahb_addr) {
-			dev_err(q->dev, "ioremap failed\n");
-			return -ENOMEM;
-		}
-	/* ioremap if the data requested is out of range */
-	} else if (q->chip_base_addr + from < q->memmap_offs
-			|| q->chip_base_addr + from + len >
-			q->memmap_offs + q->memmap_len) {
-		iounmap(q->ahb_addr);
-
-		q->memmap_offs = q->chip_base_addr + from;
-		q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
-		q->ahb_addr = ioremap_nocache(
-				q->memmap_phy + q->memmap_offs,
-				q->memmap_len);
-		if (!q->ahb_addr) {
-			dev_err(q->dev, "ioremap failed\n");
-			return -ENOMEM;
-		}
-	}
-
-	dev_dbg(q->dev, "cmd [%x],read from %p, len:%zd\n",
-		cmd, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
-		len);
-
-	/* Read out the data directly from the AHB buffer.*/
-	memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
-		len);
-
-	return len;
-}
-
-static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs)
-{
-	struct fsl_qspi *q = nor->priv;
-	int ret;
-
-	dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
-		nor->mtd.erasesize / 1024, q->chip_base_addr, (u32)offs);
-
-	ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
-	if (ret)
-		return ret;
-
-	fsl_qspi_invalid(q);
-	return 0;
-}
-
-static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
-{
-	struct fsl_qspi *q = nor->priv;
-	int ret;
-
-	mutex_lock(&q->lock);
-
-	ret = fsl_qspi_clk_prep_enable(q);
-	if (ret)
-		goto err_mutex;
-
-	fsl_qspi_set_base_addr(q, nor);
-	return 0;
-
-err_mutex:
-	mutex_unlock(&q->lock);
-	return ret;
-}
-
-static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
-{
-	struct fsl_qspi *q = nor->priv;
-
-	fsl_qspi_clk_disable_unprep(q);
-	mutex_unlock(&q->lock);
-}
-
-static int fsl_qspi_probe(struct platform_device *pdev)
-{
-	const struct spi_nor_hwcaps hwcaps = {
-		.mask = SNOR_HWCAPS_READ_1_1_4 |
-			SNOR_HWCAPS_PP,
-	};
-	struct device_node *np = pdev->dev.of_node;
-	struct device *dev = &pdev->dev;
-	struct fsl_qspi *q;
-	struct resource *res;
-	struct spi_nor *nor;
-	struct mtd_info *mtd;
-	int ret, i = 0;
-
-	q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
-	if (!q)
-		return -ENOMEM;
-
-	q->nor_num = of_get_child_count(dev->of_node);
-	if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
-		return -ENODEV;
-
-	q->dev = dev;
-	q->devtype_data = of_device_get_match_data(dev);
-	if (!q->devtype_data)
-		return -ENODEV;
-	platform_set_drvdata(pdev, q);
-
-	/* find the resources */
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
-	q->iobase = devm_ioremap_resource(dev, res);
-	if (IS_ERR(q->iobase))
-		return PTR_ERR(q->iobase);
-
-	q->big_endian = of_property_read_bool(np, "big-endian");
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-					"QuadSPI-memory");
-	if (!devm_request_mem_region(dev, res->start, resource_size(res),
-				     res->name)) {
-		dev_err(dev, "can't request region for resource %pR\n", res);
-		return -EBUSY;
-	}
-
-	q->memmap_phy = res->start;
-
-	/* find the clocks */
-	q->clk_en = devm_clk_get(dev, "qspi_en");
-	if (IS_ERR(q->clk_en))
-		return PTR_ERR(q->clk_en);
-
-	q->clk = devm_clk_get(dev, "qspi");
-	if (IS_ERR(q->clk))
-		return PTR_ERR(q->clk);
-
-	ret = fsl_qspi_clk_prep_enable(q);
-	if (ret) {
-		dev_err(dev, "can not enable the clock\n");
-		goto clk_failed;
-	}
-
-	/* find the irq */
-	ret = platform_get_irq(pdev, 0);
-	if (ret < 0) {
-		dev_err(dev, "failed to get the irq: %d\n", ret);
-		goto irq_failed;
-	}
-
-	ret = devm_request_irq(dev, ret,
-			fsl_qspi_irq_handler, 0, pdev->name, q);
-	if (ret) {
-		dev_err(dev, "failed to request irq: %d\n", ret);
-		goto irq_failed;
-	}
-
-	ret = fsl_qspi_nor_setup(q);
-	if (ret)
-		goto irq_failed;
-
-	if (of_get_property(np, "fsl,qspi-has-second-chip", NULL))
-		q->has_second_chip = true;
-
-	mutex_init(&q->lock);
-
-	/* iterate the subnodes. */
-	for_each_available_child_of_node(dev->of_node, np) {
-		/* skip the holes */
-		if (!q->has_second_chip)
-			i *= 2;
-
-		nor = &q->nor[i];
-		mtd = &nor->mtd;
-
-		nor->dev = dev;
-		spi_nor_set_flash_node(nor, np);
-		nor->priv = q;
-
-		if (q->nor_num > 1 && !mtd->name) {
-			int spiflash_idx;
-
-			ret = of_property_read_u32(np, "reg", &spiflash_idx);
-			if (!ret) {
-				mtd->name = devm_kasprintf(dev, GFP_KERNEL,
-							   "%s-%d",
-							   dev_name(dev),
-							   spiflash_idx);
-				if (!mtd->name) {
-					ret = -ENOMEM;
-					goto mutex_failed;
-				}
-			} else {
-				dev_warn(dev, "reg property is missing\n");
-			}
-		}
-
-		/* fill the hooks */
-		nor->read_reg = fsl_qspi_read_reg;
-		nor->write_reg = fsl_qspi_write_reg;
-		nor->read = fsl_qspi_read;
-		nor->write = fsl_qspi_write;
-		nor->erase = fsl_qspi_erase;
-
-		nor->prepare = fsl_qspi_prep;
-		nor->unprepare = fsl_qspi_unprep;
-
-		ret = of_property_read_u32(np, "spi-max-frequency",
-				&q->clk_rate);
-		if (ret < 0)
-			goto mutex_failed;
-
-		/* set the chip address for READID */
-		fsl_qspi_set_base_addr(q, nor);
-
-		ret = spi_nor_scan(nor, NULL, &hwcaps);
-		if (ret)
-			goto mutex_failed;
-
-		ret = mtd_device_register(mtd, NULL, 0);
-		if (ret)
-			goto mutex_failed;
-
-		/* Set the correct NOR size now. */
-		if (q->nor_size == 0) {
-			q->nor_size = mtd->size;
-
-			/* Map the SPI NOR to accessiable address */
-			fsl_qspi_set_map_addr(q);
-		}
-
-		/*
-		 * The TX FIFO is 64 bytes in the Vybrid, but the Page Program
-		 * may writes 265 bytes per time. The write is working in the
-		 * unit of the TX FIFO, not in the unit of the SPI NOR's page
-		 * size.
-		 *
-		 * So shrink the spi_nor->page_size if it is larger then the
-		 * TX FIFO.
-		 */
-		if (nor->page_size > q->devtype_data->txfifo)
-			nor->page_size = q->devtype_data->txfifo;
-
-		i++;
-	}
-
-	/* finish the rest init. */
-	ret = fsl_qspi_nor_setup_last(q);
-	if (ret)
-		goto last_init_failed;
-
-	fsl_qspi_clk_disable_unprep(q);
-	return 0;
-
-last_init_failed:
-	for (i = 0; i < q->nor_num; i++) {
-		/* skip the holes */
-		if (!q->has_second_chip)
-			i *= 2;
-		mtd_device_unregister(&q->nor[i].mtd);
-	}
-mutex_failed:
-	mutex_destroy(&q->lock);
-irq_failed:
-	fsl_qspi_clk_disable_unprep(q);
-clk_failed:
-	dev_err(dev, "Freescale QuadSPI probe failed\n");
-	return ret;
-}
-
-static int fsl_qspi_remove(struct platform_device *pdev)
-{
-	struct fsl_qspi *q = platform_get_drvdata(pdev);
-	int i;
-
-	for (i = 0; i < q->nor_num; i++) {
-		/* skip the holes */
-		if (!q->has_second_chip)
-			i *= 2;
-		mtd_device_unregister(&q->nor[i].mtd);
-	}
-
-	/* disable the hardware */
-	qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
-	qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
-
-	mutex_destroy(&q->lock);
-
-	if (q->ahb_addr)
-		iounmap(q->ahb_addr);
-
-	return 0;
-}
-
-static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t state)
-{
-	return 0;
-}
-
-static int fsl_qspi_resume(struct platform_device *pdev)
-{
-	int ret;
-	struct fsl_qspi *q = platform_get_drvdata(pdev);
-
-	ret = fsl_qspi_clk_prep_enable(q);
-	if (ret)
-		return ret;
-
-	fsl_qspi_nor_setup(q);
-	fsl_qspi_set_map_addr(q);
-	fsl_qspi_nor_setup_last(q);
-
-	fsl_qspi_clk_disable_unprep(q);
-
-	return 0;
-}
-
-static struct platform_driver fsl_qspi_driver = {
-	.driver = {
-		.name	= "fsl-quadspi",
-		.of_match_table = fsl_qspi_dt_ids,
-	},
-	.probe          = fsl_qspi_probe,
-	.remove		= fsl_qspi_remove,
-	.suspend	= fsl_qspi_suspend,
-	.resume		= fsl_qspi_resume,
-};
-module_platform_driver(fsl_qspi_driver);
-
-MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
-MODULE_AUTHOR("Freescale Semiconductor Inc.");
-MODULE_LICENSE("GPL v2");
-- 
2.7.4

RE: [PATCH v7 6/9] mtd: fsl-quadspi: Remove the driver as it was replaced by spi-fsl-qspi.c

[Han Xu]

> -----Original Message-----
> From: Schrempf Frieder <frieder.schrempf@kontron.de>
> Sent: Tuesday, December 4, 2018 8:15 AM
> To: linux-mtd@lists.infradead.org; boris.brezillon@bootlin.com; linux-
> spi@vger.kernel.org; Marek Vasut <marek.vasut@gmail.com>
> Cc: dwmw2@infradead.org; computersforpeace@gmail.com;
> richard@nod.at; miquel.raynal@bootlin.com; broonie@kernel.org; David
> Wolfe <david.wolfe@nxp.com>; Fabio Estevam <fabio.estevam@nxp.com>;
> Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; Yogesh Narayan
> Gaur <yogeshnarayan.gaur@nxp.com>; Han Xu <han.xu@nxp.com>;
> shawnguo@kernel.org; Schrempf Frieder <frieder.schrempf@kontron.de>;
> linux-kernel@vger.kernel.org
> Subject: [PATCH v7 6/9] mtd: fsl-quadspi: Remove the driver as it was
> replaced by spi-fsl-qspi.c
> 
> From: Frieder Schrempf <frieder.schrempf@kontron.de>
> 
> There's a new driver using the SPI memory interface of the SPI framework at
> spi/spi-fsl-qspi.c, which can be used together with m25p80.c to replace the
> functionality of this SPI NOR driver.
> 
> The new driver is already in use and this code is not compiled anymore, so
> let's remove it.
> 
> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
> ---
>  drivers/mtd/spi-nor/fsl-quadspi.c | 1224 --------------------------------
>  1 file changed, 1224 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-
> quadspi.c
> deleted file mode 100644
> index 1ff3430..0000000
> --- a/drivers/mtd/spi-nor/fsl-quadspi.c
> +++ /dev/null
> @@ -1,1224 +0,0 @@
> -/*
> - * Freescale QuadSPI driver.
> - *
> - * Copyright (C) 2013 Freescale Semiconductor, Inc.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - */
> -#include <linux/kernel.h>
> -#include <linux/module.h>
> -#include <linux/interrupt.h>
> -#include <linux/errno.h>
> -#include <linux/platform_device.h>
> -#include <linux/sched.h>
> -#include <linux/delay.h>
> -#include <linux/io.h>
> -#include <linux/clk.h>
> -#include <linux/err.h>
> -#include <linux/of.h>
> -#include <linux/of_device.h>
> -#include <linux/timer.h>
> -#include <linux/jiffies.h>
> -#include <linux/completion.h>
> -#include <linux/mtd/mtd.h>
> -#include <linux/mtd/partitions.h>
> -#include <linux/mtd/spi-nor.h>
> -#include <linux/mutex.h>
> -#include <linux/pm_qos.h>
> -#include <linux/sizes.h>
> -
> -/* Controller needs driver to swap endian */
> -#define QUADSPI_QUIRK_SWAP_ENDIAN	(1 << 0)
> -/* Controller needs 4x internal clock */
> -#define QUADSPI_QUIRK_4X_INT_CLK	(1 << 1)
> -/*
> - * TKT253890, Controller needs driver to fill txfifo till 16 byte to
> - * trigger data transfer even though extern data will not transferred.
> - */
> -#define QUADSPI_QUIRK_TKT253890		(1 << 2)
> -/* Controller cannot wake up from wait mode, TKT245618 */
> -#define QUADSPI_QUIRK_TKT245618         (1 << 3)
> -
> -/* The registers */
> -#define QUADSPI_MCR			0x00
> -#define QUADSPI_MCR_RESERVED_SHIFT	16
> -#define QUADSPI_MCR_RESERVED_MASK	(0xF <<
> QUADSPI_MCR_RESERVED_SHIFT)
> -#define QUADSPI_MCR_MDIS_SHIFT		14
> -#define QUADSPI_MCR_MDIS_MASK		(1 <<
> QUADSPI_MCR_MDIS_SHIFT)
> -#define QUADSPI_MCR_CLR_TXF_SHIFT	11
> -#define QUADSPI_MCR_CLR_TXF_MASK	(1 <<
> QUADSPI_MCR_CLR_TXF_SHIFT)
> -#define QUADSPI_MCR_CLR_RXF_SHIFT	10
> -#define QUADSPI_MCR_CLR_RXF_MASK	(1 <<
> QUADSPI_MCR_CLR_RXF_SHIFT)
> -#define QUADSPI_MCR_DDR_EN_SHIFT	7
> -#define QUADSPI_MCR_DDR_EN_MASK		(1 <<
> QUADSPI_MCR_DDR_EN_SHIFT)
> -#define QUADSPI_MCR_END_CFG_SHIFT	2
> -#define QUADSPI_MCR_END_CFG_MASK	(3 <<
> QUADSPI_MCR_END_CFG_SHIFT)
> -#define QUADSPI_MCR_SWRSTHD_SHIFT	1
> -#define QUADSPI_MCR_SWRSTHD_MASK	(1 <<
> QUADSPI_MCR_SWRSTHD_SHIFT)
> -#define QUADSPI_MCR_SWRSTSD_SHIFT	0
> -#define QUADSPI_MCR_SWRSTSD_MASK	(1 <<
> QUADSPI_MCR_SWRSTSD_SHIFT)
> -
> -#define QUADSPI_IPCR			0x08
> -#define QUADSPI_IPCR_SEQID_SHIFT	24
> -#define QUADSPI_IPCR_SEQID_MASK		(0xF <<
> QUADSPI_IPCR_SEQID_SHIFT)
> -
> -#define QUADSPI_BUF0CR			0x10
> -#define QUADSPI_BUF1CR			0x14
> -#define QUADSPI_BUF2CR			0x18
> -#define QUADSPI_BUFXCR_INVALID_MSTRID	0xe
> -
> -#define QUADSPI_BUF3CR			0x1c
> -#define QUADSPI_BUF3CR_ALLMST_SHIFT	31
> -#define QUADSPI_BUF3CR_ALLMST_MASK	(1 <<
> QUADSPI_BUF3CR_ALLMST_SHIFT)
> -#define QUADSPI_BUF3CR_ADATSZ_SHIFT		8
> -#define QUADSPI_BUF3CR_ADATSZ_MASK	(0xFF <<
> QUADSPI_BUF3CR_ADATSZ_SHIFT)
> -
> -#define QUADSPI_BFGENCR			0x20
> -#define QUADSPI_BFGENCR_PAR_EN_SHIFT	16
> -#define QUADSPI_BFGENCR_PAR_EN_MASK	(1 <<
> (QUADSPI_BFGENCR_PAR_EN_SHIFT))
> -#define QUADSPI_BFGENCR_SEQID_SHIFT	12
> -#define QUADSPI_BFGENCR_SEQID_MASK	(0xF <<
> QUADSPI_BFGENCR_SEQID_SHIFT)
> -
> -#define QUADSPI_BUF0IND			0x30
> -#define QUADSPI_BUF1IND			0x34
> -#define QUADSPI_BUF2IND			0x38
> -#define QUADSPI_SFAR			0x100
> -
> -#define QUADSPI_SMPR			0x108
> -#define QUADSPI_SMPR_DDRSMP_SHIFT	16
> -#define QUADSPI_SMPR_DDRSMP_MASK	(7 <<
> QUADSPI_SMPR_DDRSMP_SHIFT)
> -#define QUADSPI_SMPR_FSDLY_SHIFT	6
> -#define QUADSPI_SMPR_FSDLY_MASK		(1 <<
> QUADSPI_SMPR_FSDLY_SHIFT)
> -#define QUADSPI_SMPR_FSPHS_SHIFT	5
> -#define QUADSPI_SMPR_FSPHS_MASK		(1 <<
> QUADSPI_SMPR_FSPHS_SHIFT)
> -#define QUADSPI_SMPR_HSENA_SHIFT	0
> -#define QUADSPI_SMPR_HSENA_MASK		(1 <<
> QUADSPI_SMPR_HSENA_SHIFT)
> -
> -#define QUADSPI_RBSR			0x10c
> -#define QUADSPI_RBSR_RDBFL_SHIFT	8
> -#define QUADSPI_RBSR_RDBFL_MASK		(0x3F <<
> QUADSPI_RBSR_RDBFL_SHIFT)
> -
> -#define QUADSPI_RBCT			0x110
> -#define QUADSPI_RBCT_WMRK_MASK		0x1F
> -#define QUADSPI_RBCT_RXBRD_SHIFT	8
> -#define QUADSPI_RBCT_RXBRD_USEIPS	(0x1 <<
> QUADSPI_RBCT_RXBRD_SHIFT)
> -
> -#define QUADSPI_TBSR			0x150
> -#define QUADSPI_TBDR			0x154
> -#define QUADSPI_SR			0x15c
> -#define QUADSPI_SR_IP_ACC_SHIFT		1
> -#define QUADSPI_SR_IP_ACC_MASK		(0x1 <<
> QUADSPI_SR_IP_ACC_SHIFT)
> -#define QUADSPI_SR_AHB_ACC_SHIFT	2
> -#define QUADSPI_SR_AHB_ACC_MASK		(0x1 <<
> QUADSPI_SR_AHB_ACC_SHIFT)
> -
> -#define QUADSPI_FR			0x160
> -#define QUADSPI_FR_TFF_MASK		0x1
> -
> -#define QUADSPI_SFA1AD			0x180
> -#define QUADSPI_SFA2AD			0x184
> -#define QUADSPI_SFB1AD			0x188
> -#define QUADSPI_SFB2AD			0x18c
> -#define QUADSPI_RBDR			0x200
> -
> -#define QUADSPI_LUTKEY			0x300
> -#define QUADSPI_LUTKEY_VALUE		0x5AF05AF0
> -
> -#define QUADSPI_LCKCR			0x304
> -#define QUADSPI_LCKER_LOCK		0x1
> -#define QUADSPI_LCKER_UNLOCK		0x2
> -
> -#define QUADSPI_RSER			0x164
> -#define QUADSPI_RSER_TFIE		(0x1 << 0)
> -
> -#define QUADSPI_LUT_BASE		0x310
> -
> -/*
> - * The definition of the LUT register shows below:
> - *
> - *  ---------------------------------------------------
> - *  | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
> - *  ---------------------------------------------------
> - */
> -#define OPRND0_SHIFT		0
> -#define PAD0_SHIFT		8
> -#define INSTR0_SHIFT		10
> -#define OPRND1_SHIFT		16
> -
> -/* Instruction set for the LUT register. */
> -#define LUT_STOP		0
> -#define LUT_CMD			1
> -#define LUT_ADDR		2
> -#define LUT_DUMMY		3
> -#define LUT_MODE		4
> -#define LUT_MODE2		5
> -#define LUT_MODE4		6
> -#define LUT_FSL_READ		7
> -#define LUT_FSL_WRITE		8
> -#define LUT_JMP_ON_CS		9
> -#define LUT_ADDR_DDR		10
> -#define LUT_MODE_DDR		11
> -#define LUT_MODE2_DDR		12
> -#define LUT_MODE4_DDR		13
> -#define LUT_FSL_READ_DDR		14
> -#define LUT_FSL_WRITE_DDR		15
> -#define LUT_DATA_LEARN		16
> -
> -/*
> - * The PAD definitions for LUT register.
> - *
> - * The pad stands for the lines number of IO[0:3].
> - * For example, the Quad read need four IO lines, so you should
> - * set LUT_PAD4 which means we use four IO lines.
> - */
> -#define LUT_PAD1		0
> -#define LUT_PAD2		1
> -#define LUT_PAD4		2
> -
> -/* Oprands for the LUT register. */
> -#define ADDR24BIT		0x18
> -#define ADDR32BIT		0x20
> -
> -/* Macros for constructing the LUT register. */
> -#define LUT0(ins, pad, opr)						\
> -		(((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
> -		((LUT_##ins) << INSTR0_SHIFT))
> -
> -#define LUT1(ins, pad, opr)	(LUT0(ins, pad, opr) << OPRND1_SHIFT)
> -
> -/* other macros for LUT register. */
> -#define QUADSPI_LUT(x)          (QUADSPI_LUT_BASE + (x) * 4)
> -#define QUADSPI_LUT_NUM		64
> -
> -/* SEQID -- we can have 16 seqids at most. */
> -#define SEQID_READ		0
> -#define SEQID_WREN		1
> -#define SEQID_WRDI		2
> -#define SEQID_RDSR		3
> -#define SEQID_SE		4
> -#define SEQID_CHIP_ERASE	5
> -#define SEQID_PP		6
> -#define SEQID_RDID		7
> -#define SEQID_WRSR		8
> -#define SEQID_RDCR		9
> -#define SEQID_EN4B		10
> -#define SEQID_BRWR		11
> -
> -#define QUADSPI_MIN_IOMAP SZ_4M
> -
> -enum fsl_qspi_devtype {
> -	FSL_QUADSPI_VYBRID,
> -	FSL_QUADSPI_IMX6SX,
> -	FSL_QUADSPI_IMX7D,
> -	FSL_QUADSPI_IMX6UL,
> -	FSL_QUADSPI_LS1021A,
> -	FSL_QUADSPI_LS2080A,
> -};
> -
> -struct fsl_qspi_devtype_data {
> -	enum fsl_qspi_devtype devtype;
> -	int rxfifo;
> -	int txfifo;
> -	int ahb_buf_size;
> -	int driver_data;
> -};
> -
> -static const struct fsl_qspi_devtype_data vybrid_data = {
> -	.devtype = FSL_QUADSPI_VYBRID,
> -	.rxfifo = 128,
> -	.txfifo = 64,
> -	.ahb_buf_size = 1024,
> -	.driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
> -};
> -
> -static const struct fsl_qspi_devtype_data imx6sx_data = {
> -	.devtype = FSL_QUADSPI_IMX6SX,
> -	.rxfifo = 128,
> -	.txfifo = 512,
> -	.ahb_buf_size = 1024,
> -	.driver_data = QUADSPI_QUIRK_4X_INT_CLK
> -		       | QUADSPI_QUIRK_TKT245618,
> -};
> -
> -static const struct fsl_qspi_devtype_data imx7d_data = {
> -	.devtype = FSL_QUADSPI_IMX7D,
> -	.rxfifo = 512,
> -	.txfifo = 512,
> -	.ahb_buf_size = 1024,
> -	.driver_data = QUADSPI_QUIRK_TKT253890
> -		       | QUADSPI_QUIRK_4X_INT_CLK,
> -};
> -
> -static const struct fsl_qspi_devtype_data imx6ul_data = {
> -	.devtype = FSL_QUADSPI_IMX6UL,
> -	.rxfifo = 128,
> -	.txfifo = 512,
> -	.ahb_buf_size = 1024,
> -	.driver_data = QUADSPI_QUIRK_TKT253890
> -		       | QUADSPI_QUIRK_4X_INT_CLK,
> -};
> -
> -static struct fsl_qspi_devtype_data ls1021a_data = {
> -	.devtype = FSL_QUADSPI_LS1021A,
> -	.rxfifo = 128,
> -	.txfifo = 64,
> -	.ahb_buf_size = 1024,
> -	.driver_data = 0,
> -};
> -
> -static const struct fsl_qspi_devtype_data ls2080a_data = {
> -	.devtype = FSL_QUADSPI_LS2080A,
> -	.rxfifo = 128,
> -	.txfifo = 64,
> -	.ahb_buf_size = 1024,
> -	.driver_data = QUADSPI_QUIRK_TKT253890,
> -};
> -
> -
> -#define FSL_QSPI_MAX_CHIP	4
> -struct fsl_qspi {
> -	struct spi_nor nor[FSL_QSPI_MAX_CHIP];
> -	void __iomem *iobase;
> -	void __iomem *ahb_addr;
> -	u32 memmap_phy;
> -	u32 memmap_offs;
> -	u32 memmap_len;
> -	struct clk *clk, *clk_en;
> -	struct device *dev;
> -	struct completion c;
> -	const struct fsl_qspi_devtype_data *devtype_data;
> -	u32 nor_size;
> -	u32 nor_num;
> -	u32 clk_rate;
> -	unsigned int chip_base_addr; /* We may support two chips. */
> -	bool has_second_chip;
> -	bool big_endian;
> -	struct mutex lock;
> -	struct pm_qos_request pm_qos_req;
> -};
> -
> -static inline int needs_swap_endian(struct fsl_qspi *q) -{
> -	return q->devtype_data->driver_data &
> QUADSPI_QUIRK_SWAP_ENDIAN;
> -}
> -
> -static inline int needs_4x_clock(struct fsl_qspi *q) -{
> -	return q->devtype_data->driver_data &
> QUADSPI_QUIRK_4X_INT_CLK;
> -}
> -
> -static inline int needs_fill_txfifo(struct fsl_qspi *q) -{
> -	return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890;
> -}
> -
> -static inline int needs_wakeup_wait_mode(struct fsl_qspi *q) -{
> -	return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
> -}
> -
> -/*
> - * R/W functions for big- or little-endian registers:
> - * The qSPI controller's endian is independent of the CPU core's endian.
> - * So far, although the CPU core is little-endian but the qSPI have two
> - * versions for big-endian and little-endian.
> - */
> -static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr) -{
> -	if (q->big_endian)
> -		iowrite32be(val, addr);
> -	else
> -		iowrite32(val, addr);
> -}
> -
> -static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr) -{
> -	if (q->big_endian)
> -		return ioread32be(addr);
> -	else
> -		return ioread32(addr);
> -}
> -
> -/*
> - * An IC bug makes us to re-arrange the 32-bit data.
> - * The following chips, such as IMX6SLX, have fixed this bug.
> - */
> -static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a) -{
> -	return needs_swap_endian(q) ? __swab32(a) : a;
> -}
> -
> -static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q) -{
> -	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase +
> QUADSPI_LUTKEY);
> -	qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase +
> QUADSPI_LCKCR);
> -}
> -
> -static inline void fsl_qspi_lock_lut(struct fsl_qspi *q) -{
> -	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase +
> QUADSPI_LUTKEY);
> -	qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
> -}
> -
> -static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id) -{
> -	struct fsl_qspi *q = dev_id;
> -	u32 reg;
> -
> -	/* clear interrupt */
> -	reg = qspi_readl(q, q->iobase + QUADSPI_FR);
> -	qspi_writel(q, reg, q->iobase + QUADSPI_FR);
> -
> -	if (reg & QUADSPI_FR_TFF_MASK)
> -		complete(&q->c);
> -
> -	dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q-
> >chip_base_addr, reg);
> -	return IRQ_HANDLED;
> -}
> -
> -static void fsl_qspi_init_lut(struct fsl_qspi *q) -{
> -	void __iomem *base = q->iobase;
> -	int rxfifo = q->devtype_data->rxfifo;
> -	u32 lut_base;
> -	int i;
> -
> -	struct spi_nor *nor = &q->nor[0];
> -	u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
> -	u8 read_op = nor->read_opcode;
> -	u8 read_dm = nor->read_dummy;
> -
> -	fsl_qspi_unlock_lut(q);
> -
> -	/* Clear all the LUT table */
> -	for (i = 0; i < QUADSPI_LUT_NUM; i++)
> -		qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
> -
> -	/* Read */
> -	lut_base = SEQID_READ * 4;
> -
> -	qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1,
> addrlen),
> -			base + QUADSPI_LUT(lut_base));
> -	qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
> -		    LUT1(FSL_READ, PAD4, rxfifo),
> -			base + QUADSPI_LUT(lut_base + 1));
> -
> -	/* Write enable */
> -	lut_base = SEQID_WREN * 4;
> -	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
> -			base + QUADSPI_LUT(lut_base));
> -
> -	/* Page Program */
> -	lut_base = SEQID_PP * 4;
> -
> -	qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
> -		    LUT1(ADDR, PAD1, addrlen),
> -			base + QUADSPI_LUT(lut_base));
> -	qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
> -			base + QUADSPI_LUT(lut_base + 1));
> -
> -	/* Read Status */
> -	lut_base = SEQID_RDSR * 4;
> -	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
> -			LUT1(FSL_READ, PAD1, 0x1),
> -			base + QUADSPI_LUT(lut_base));
> -
> -	/* Erase a sector */
> -	lut_base = SEQID_SE * 4;
> -
> -	qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
> -		    LUT1(ADDR, PAD1, addrlen),
> -			base + QUADSPI_LUT(lut_base));
> -
> -	/* Erase the whole chip */
> -	lut_base = SEQID_CHIP_ERASE * 4;
> -	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
> -			base + QUADSPI_LUT(lut_base));
> -
> -	/* READ ID */
> -	lut_base = SEQID_RDID * 4;
> -	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDID) |
> -			LUT1(FSL_READ, PAD1, 0x8),
> -			base + QUADSPI_LUT(lut_base));
> -
> -	/* Write Register */
> -	lut_base = SEQID_WRSR * 4;
> -	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRSR) |
> -			LUT1(FSL_WRITE, PAD1, 0x2),
> -			base + QUADSPI_LUT(lut_base));
> -
> -	/* Read Configuration Register */
> -	lut_base = SEQID_RDCR * 4;
> -	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDCR) |
> -			LUT1(FSL_READ, PAD1, 0x1),
> -			base + QUADSPI_LUT(lut_base));
> -
> -	/* Write disable */
> -	lut_base = SEQID_WRDI * 4;
> -	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRDI),
> -			base + QUADSPI_LUT(lut_base));
> -
> -	/* Enter 4 Byte Mode (Micron) */
> -	lut_base = SEQID_EN4B * 4;
> -	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_EN4B),
> -			base + QUADSPI_LUT(lut_base));
> -
> -	/* Enter 4 Byte Mode (Spansion) */
> -	lut_base = SEQID_BRWR * 4;
> -	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
> -			base + QUADSPI_LUT(lut_base));
> -
> -	fsl_qspi_lock_lut(q);
> -}
> -
> -/* Get the SEQID for the command */
> -static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) -{
> -	switch (cmd) {
> -	case SPINOR_OP_READ_1_1_4:
> -	case SPINOR_OP_READ_1_1_4_4B:
> -		return SEQID_READ;
> -	case SPINOR_OP_WREN:
> -		return SEQID_WREN;
> -	case SPINOR_OP_WRDI:
> -		return SEQID_WRDI;
> -	case SPINOR_OP_RDSR:
> -		return SEQID_RDSR;
> -	case SPINOR_OP_SE:
> -		return SEQID_SE;
> -	case SPINOR_OP_CHIP_ERASE:
> -		return SEQID_CHIP_ERASE;
> -	case SPINOR_OP_PP:
> -		return SEQID_PP;
> -	case SPINOR_OP_RDID:
> -		return SEQID_RDID;
> -	case SPINOR_OP_WRSR:
> -		return SEQID_WRSR;
> -	case SPINOR_OP_RDCR:
> -		return SEQID_RDCR;
> -	case SPINOR_OP_EN4B:
> -		return SEQID_EN4B;
> -	case SPINOR_OP_BRWR:
> -		return SEQID_BRWR;
> -	default:
> -		if (cmd == q->nor[0].erase_opcode)
> -			return SEQID_SE;
> -		dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
> -		break;
> -	}
> -	return -EINVAL;
> -}
> -
> -static int
> -fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len) -{
> -	void __iomem *base = q->iobase;
> -	int seqid;
> -	u32 reg, reg2;
> -	int err;
> -
> -	init_completion(&q->c);
> -	dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
> -			q->chip_base_addr, addr, len, cmd);
> -
> -	/* save the reg */
> -	reg = qspi_readl(q, base + QUADSPI_MCR);
> -
> -	qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
> -			base + QUADSPI_SFAR);
> -	qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
> QUADSPI_RBCT_RXBRD_USEIPS,
> -			base + QUADSPI_RBCT);
> -	qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base +
> QUADSPI_MCR);
> -
> -	do {
> -		reg2 = qspi_readl(q, base + QUADSPI_SR);
> -		if (reg2 & (QUADSPI_SR_IP_ACC_MASK |
> QUADSPI_SR_AHB_ACC_MASK)) {
> -			udelay(1);
> -			dev_dbg(q->dev, "The controller is busy, 0x%x\n",
> reg2);
> -			continue;
> -		}
> -		break;
> -	} while (1);
> -
> -	/* trigger the LUT now */
> -	seqid = fsl_qspi_get_seqid(q, cmd);
> -	if (seqid < 0)
> -		return seqid;
> -
> -	qspi_writel(q, (seqid << QUADSPI_IPCR_SEQID_SHIFT) | len,
> -			base + QUADSPI_IPCR);
> -
> -	/* Wait for the interrupt. */
> -	if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) {
> -		dev_err(q->dev,
> -			"cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x,
> SR:0x%.8x\n",
> -			cmd, addr, qspi_readl(q, base + QUADSPI_FR),
> -			qspi_readl(q, base + QUADSPI_SR));
> -		err = -ETIMEDOUT;
> -	} else {
> -		err = 0;
> -	}
> -
> -	/* restore the MCR */
> -	qspi_writel(q, reg, base + QUADSPI_MCR);
> -
> -	return err;
> -}
> -
> -/* Read out the data from the QUADSPI_RBDR buffer registers. */ -static
> void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf) -{
> -	u32 tmp;
> -	int i = 0;
> -
> -	while (len > 0) {
> -		tmp = qspi_readl(q, q->iobase + QUADSPI_RBDR + i * 4);
> -		tmp = fsl_qspi_endian_xchg(q, tmp);
> -		dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
> -				q->chip_base_addr, tmp);
> -
> -		if (len >= 4) {
> -			*((u32 *)rxbuf) = tmp;
> -			rxbuf += 4;
> -		} else {
> -			memcpy(rxbuf, &tmp, len);
> -			break;
> -		}
> -
> -		len -= 4;
> -		i++;
> -	}
> -}
> -
> -/*
> - * If we have changed the content of the flash by writing or erasing,
> - * we need to invalidate the AHB buffer. If we do not do so, we may read
> out
> - * the wrong data. The spec tells us reset the AHB domain and Serial Flash
> - * domain at the same time.
> - */
> -static inline void fsl_qspi_invalid(struct fsl_qspi *q) -{
> -	u32 reg;
> -
> -	reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
> -	reg |= QUADSPI_MCR_SWRSTHD_MASK |
> QUADSPI_MCR_SWRSTSD_MASK;
> -	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
> -
> -	/*
> -	 * The minimum delay : 1 AHB + 2 SFCK clocks.
> -	 * Delay 1 us is enough.
> -	 */
> -	udelay(1);
> -
> -	reg &= ~(QUADSPI_MCR_SWRSTHD_MASK |
> QUADSPI_MCR_SWRSTSD_MASK);
> -	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
> -}
> -
> -static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
> -				u8 opcode, unsigned int to, u32 *txbuf,
> -				unsigned count)
> -{
> -	int ret, i, j;
> -	u32 tmp;
> -
> -	dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
> -		q->chip_base_addr, to, count);
> -
> -	/* clear the TX FIFO. */
> -	tmp = qspi_readl(q, q->iobase + QUADSPI_MCR);
> -	qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase +
> QUADSPI_MCR);
> -
> -	/* fill the TX data to the FIFO */
> -	for (j = 0, i = ((count + 3) / 4); j < i; j++) {
> -		tmp = fsl_qspi_endian_xchg(q, *txbuf);
> -		qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
> -		txbuf++;
> -	}
> -
> -	/* fill the TXFIFO upto 16 bytes for i.MX7d */
> -	if (needs_fill_txfifo(q))
> -		for (; i < 4; i++)
> -			qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
> -
> -	/* Trigger it */
> -	ret = fsl_qspi_runcmd(q, opcode, to, count);
> -
> -	if (ret == 0)
> -		return count;
> -
> -	return ret;
> -}
> -
> -static void fsl_qspi_set_map_addr(struct fsl_qspi *q) -{
> -	int nor_size = q->nor_size;
> -	void __iomem *base = q->iobase;
> -
> -	qspi_writel(q, nor_size + q->memmap_phy, base +
> QUADSPI_SFA1AD);
> -	qspi_writel(q, nor_size * 2 + q->memmap_phy, base +
> QUADSPI_SFA2AD);
> -	qspi_writel(q, nor_size * 3 + q->memmap_phy, base +
> QUADSPI_SFB1AD);
> -	qspi_writel(q, nor_size * 4 + q->memmap_phy, base +
> QUADSPI_SFB2AD);
> -}
> -
> -/*
> - * There are two different ways to read out the data from the flash:
> - *  the "IP Command Read" and the "AHB Command Read".
> - *
> - * The IC guy suggests we use the "AHB Command Read" which is faster
> - * then the "IP Command Read". (What's more is that there is a bug in
> - * the "IP Command Read" in the Vybrid.)
> - *
> - * After we set up the registers for the "AHB Command Read", we can use
> - * the memcpy to read the data directly. A "missed" access to the buffer
> - * causes the controller to clear the buffer, and use the sequence pointed
> - * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
> - */
> -static int fsl_qspi_init_ahb_read(struct fsl_qspi *q) -{
> -	void __iomem *base = q->iobase;
> -	int seqid;
> -
> -	/* AHB configuration for access buffer 0/1/2 .*/
> -	qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base +
> QUADSPI_BUF0CR);
> -	qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base +
> QUADSPI_BUF1CR);
> -	qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base +
> QUADSPI_BUF2CR);
> -	/*
> -	 * Set ADATSZ with the maximum AHB buffer size to improve the
> -	 * read performance.
> -	 */
> -	qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
> -			((q->devtype_data->ahb_buf_size / 8)
> -			<< QUADSPI_BUF3CR_ADATSZ_SHIFT),
> -			base + QUADSPI_BUF3CR);
> -
> -	/* We only use the buffer3 */
> -	qspi_writel(q, 0, base + QUADSPI_BUF0IND);
> -	qspi_writel(q, 0, base + QUADSPI_BUF1IND);
> -	qspi_writel(q, 0, base + QUADSPI_BUF2IND);
> -
> -	/* Set the default lut sequence for AHB Read. */
> -	seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
> -	if (seqid < 0)
> -		return seqid;
> -
> -	qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
> -		q->iobase + QUADSPI_BFGENCR);
> -
> -	return 0;
> -}
> -
> -/* This function was used to prepare and enable QSPI clock */ -static int
> fsl_qspi_clk_prep_enable(struct fsl_qspi *q) -{
> -	int ret;
> -
> -	ret = clk_prepare_enable(q->clk_en);
> -	if (ret)
> -		return ret;
> -
> -	ret = clk_prepare_enable(q->clk);
> -	if (ret) {
> -		clk_disable_unprepare(q->clk_en);
> -		return ret;
> -	}
> -
> -	if (needs_wakeup_wait_mode(q))
> -		pm_qos_add_request(&q->pm_qos_req,
> PM_QOS_CPU_DMA_LATENCY, 0);
> -
> -	return 0;
> -}
> -
> -/* This function was used to disable and unprepare QSPI clock */ -static void
> fsl_qspi_clk_disable_unprep(struct fsl_qspi *q) -{
> -	if (needs_wakeup_wait_mode(q))
> -		pm_qos_remove_request(&q->pm_qos_req);
> -
> -	clk_disable_unprepare(q->clk);
> -	clk_disable_unprepare(q->clk_en);
> -
> -}
> -
> -/* We use this function to do some basic init for spi_nor_scan(). */ -static int
> fsl_qspi_nor_setup(struct fsl_qspi *q) -{
> -	void __iomem *base = q->iobase;
> -	u32 reg;
> -	int ret;
> -
> -	/* disable and unprepare clock to avoid glitch pass to controller */
> -	fsl_qspi_clk_disable_unprep(q);
> -
> -	/* the default frequency, we will change it in the future. */
> -	ret = clk_set_rate(q->clk, 66000000);
> -	if (ret)
> -		return ret;
> -
> -	ret = fsl_qspi_clk_prep_enable(q);
> -	if (ret)
> -		return ret;
> -
> -	/* Reset the module */
> -	qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK |
> QUADSPI_MCR_SWRSTHD_MASK,
> -		base + QUADSPI_MCR);
> -	udelay(1);
> -
> -	/* Init the LUT table. */
> -	fsl_qspi_init_lut(q);
> -
> -	/* Disable the module */
> -	qspi_writel(q, QUADSPI_MCR_MDIS_MASK |
> QUADSPI_MCR_RESERVED_MASK,
> -			base + QUADSPI_MCR);
> -
> -	reg = qspi_readl(q, base + QUADSPI_SMPR);
> -	qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
> -			| QUADSPI_SMPR_FSPHS_MASK
> -			| QUADSPI_SMPR_HSENA_MASK
> -			| QUADSPI_SMPR_DDRSMP_MASK), base +
> QUADSPI_SMPR);
> -
> -	/* Enable the module */
> -	qspi_writel(q, QUADSPI_MCR_RESERVED_MASK |
> QUADSPI_MCR_END_CFG_MASK,
> -			base + QUADSPI_MCR);
> -
> -	/* clear all interrupt status */
> -	qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
> -
> -	/* enable the interrupt */
> -	qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
> -
> -	return 0;
> -}
> -
> -static int fsl_qspi_nor_setup_last(struct fsl_qspi *q) -{
> -	unsigned long rate = q->clk_rate;
> -	int ret;
> -
> -	if (needs_4x_clock(q))
> -		rate *= 4;
> -
> -	/* disable and unprepare clock to avoid glitch pass to controller */
> -	fsl_qspi_clk_disable_unprep(q);
> -
> -	ret = clk_set_rate(q->clk, rate);
> -	if (ret)
> -		return ret;
> -
> -	ret = fsl_qspi_clk_prep_enable(q);
> -	if (ret)
> -		return ret;
> -
> -	/* Init the LUT table again. */
> -	fsl_qspi_init_lut(q);
> -
> -	/* Init for AHB read */
> -	return fsl_qspi_init_ahb_read(q);
> -}
> -
> -static const struct of_device_id fsl_qspi_dt_ids[] = {
> -	{ .compatible = "fsl,vf610-qspi", .data = &vybrid_data, },
> -	{ .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, },
> -	{ .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, },
> -	{ .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
> -	{ .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
> -	{ .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
> -	{ /* sentinel */ }
> -};
> -MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
> -
> -static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor) -{
> -	q->chip_base_addr = q->nor_size * (nor - q->nor);
> -}
> -
> -static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
> -{
> -	int ret;
> -	struct fsl_qspi *q = nor->priv;
> -
> -	ret = fsl_qspi_runcmd(q, opcode, 0, len);
> -	if (ret)
> -		return ret;
> -
> -	fsl_qspi_read_data(q, len, buf);
> -	return 0;
> -}
> -
> -static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
> -{
> -	struct fsl_qspi *q = nor->priv;
> -	int ret;
> -
> -	if (!buf) {
> -		ret = fsl_qspi_runcmd(q, opcode, 0, 1);
> -		if (ret)
> -			return ret;
> -
> -		if (opcode == SPINOR_OP_CHIP_ERASE)
> -			fsl_qspi_invalid(q);
> -
> -	} else if (len > 0) {
> -		ret = fsl_qspi_nor_write(q, nor, opcode, 0,
> -					(u32 *)buf, len);
> -		if (ret > 0)
> -			return 0;
> -	} else {
> -		dev_err(q->dev, "invalid cmd %d\n", opcode);
> -		ret = -EINVAL;
> -	}
> -
> -	return ret;
> -}
> -
> -static ssize_t fsl_qspi_write(struct spi_nor *nor, loff_t to,
> -			      size_t len, const u_char *buf)
> -{
> -	struct fsl_qspi *q = nor->priv;
> -	ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
> -					 (u32 *)buf, len);
> -
> -	/* invalid the data in the AHB buffer. */
> -	fsl_qspi_invalid(q);
> -	return ret;
> -}
> -
> -static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from,
> -			     size_t len, u_char *buf)
> -{
> -	struct fsl_qspi *q = nor->priv;
> -	u8 cmd = nor->read_opcode;
> -
> -	/* if necessary,ioremap buffer before AHB read, */
> -	if (!q->ahb_addr) {
> -		q->memmap_offs = q->chip_base_addr + from;
> -		q->memmap_len = len > QUADSPI_MIN_IOMAP ? len :
> QUADSPI_MIN_IOMAP;
> -
> -		q->ahb_addr = ioremap_nocache(
> -				q->memmap_phy + q->memmap_offs,
> -				q->memmap_len);
> -		if (!q->ahb_addr) {
> -			dev_err(q->dev, "ioremap failed\n");
> -			return -ENOMEM;
> -		}
> -	/* ioremap if the data requested is out of range */
> -	} else if (q->chip_base_addr + from < q->memmap_offs
> -			|| q->chip_base_addr + from + len >
> -			q->memmap_offs + q->memmap_len) {
> -		iounmap(q->ahb_addr);
> -
> -		q->memmap_offs = q->chip_base_addr + from;
> -		q->memmap_len = len > QUADSPI_MIN_IOMAP ? len :
> QUADSPI_MIN_IOMAP;
> -		q->ahb_addr = ioremap_nocache(
> -				q->memmap_phy + q->memmap_offs,
> -				q->memmap_len);
> -		if (!q->ahb_addr) {
> -			dev_err(q->dev, "ioremap failed\n");
> -			return -ENOMEM;
> -		}
> -	}
> -
> -	dev_dbg(q->dev, "cmd [%x],read from %p, len:%zd\n",
> -		cmd, q->ahb_addr + q->chip_base_addr + from - q-
> >memmap_offs,
> -		len);
> -
> -	/* Read out the data directly from the AHB buffer.*/
> -	memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q-
> >memmap_offs,
> -		len);
> -
> -	return len;
> -}
> -
> -static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs) -{
> -	struct fsl_qspi *q = nor->priv;
> -	int ret;
> -
> -	dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
> -		nor->mtd.erasesize / 1024, q->chip_base_addr, (u32)offs);
> -
> -	ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
> -	if (ret)
> -		return ret;
> -
> -	fsl_qspi_invalid(q);
> -	return 0;
> -}
> -
> -static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops) -{
> -	struct fsl_qspi *q = nor->priv;
> -	int ret;
> -
> -	mutex_lock(&q->lock);
> -
> -	ret = fsl_qspi_clk_prep_enable(q);
> -	if (ret)
> -		goto err_mutex;
> -
> -	fsl_qspi_set_base_addr(q, nor);
> -	return 0;
> -
> -err_mutex:
> -	mutex_unlock(&q->lock);
> -	return ret;
> -}
> -
> -static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops) -{
> -	struct fsl_qspi *q = nor->priv;
> -
> -	fsl_qspi_clk_disable_unprep(q);
> -	mutex_unlock(&q->lock);
> -}
> -
> -static int fsl_qspi_probe(struct platform_device *pdev) -{
> -	const struct spi_nor_hwcaps hwcaps = {
> -		.mask = SNOR_HWCAPS_READ_1_1_4 |
> -			SNOR_HWCAPS_PP,
> -	};
> -	struct device_node *np = pdev->dev.of_node;
> -	struct device *dev = &pdev->dev;
> -	struct fsl_qspi *q;
> -	struct resource *res;
> -	struct spi_nor *nor;
> -	struct mtd_info *mtd;
> -	int ret, i = 0;
> -
> -	q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
> -	if (!q)
> -		return -ENOMEM;
> -
> -	q->nor_num = of_get_child_count(dev->of_node);
> -	if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
> -		return -ENODEV;
> -
> -	q->dev = dev;
> -	q->devtype_data = of_device_get_match_data(dev);
> -	if (!q->devtype_data)
> -		return -ENODEV;
> -	platform_set_drvdata(pdev, q);
> -
> -	/* find the resources */
> -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> "QuadSPI");
> -	q->iobase = devm_ioremap_resource(dev, res);
> -	if (IS_ERR(q->iobase))
> -		return PTR_ERR(q->iobase);
> -
> -	q->big_endian = of_property_read_bool(np, "big-endian");
> -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> -					"QuadSPI-memory");
> -	if (!devm_request_mem_region(dev, res->start, resource_size(res),
> -				     res->name)) {
> -		dev_err(dev, "can't request region for resource %pR\n", res);
> -		return -EBUSY;
> -	}
> -
> -	q->memmap_phy = res->start;
> -
> -	/* find the clocks */
> -	q->clk_en = devm_clk_get(dev, "qspi_en");
> -	if (IS_ERR(q->clk_en))
> -		return PTR_ERR(q->clk_en);
> -
> -	q->clk = devm_clk_get(dev, "qspi");
> -	if (IS_ERR(q->clk))
> -		return PTR_ERR(q->clk);
> -
> -	ret = fsl_qspi_clk_prep_enable(q);
> -	if (ret) {
> -		dev_err(dev, "can not enable the clock\n");
> -		goto clk_failed;
> -	}
> -
> -	/* find the irq */
> -	ret = platform_get_irq(pdev, 0);
> -	if (ret < 0) {
> -		dev_err(dev, "failed to get the irq: %d\n", ret);
> -		goto irq_failed;
> -	}
> -
> -	ret = devm_request_irq(dev, ret,
> -			fsl_qspi_irq_handler, 0, pdev->name, q);
> -	if (ret) {
> -		dev_err(dev, "failed to request irq: %d\n", ret);
> -		goto irq_failed;
> -	}
> -
> -	ret = fsl_qspi_nor_setup(q);
> -	if (ret)
> -		goto irq_failed;
> -
> -	if (of_get_property(np, "fsl,qspi-has-second-chip", NULL))
> -		q->has_second_chip = true;
> -
> -	mutex_init(&q->lock);
> -
> -	/* iterate the subnodes. */
> -	for_each_available_child_of_node(dev->of_node, np) {
> -		/* skip the holes */
> -		if (!q->has_second_chip)
> -			i *= 2;
> -
> -		nor = &q->nor[i];
> -		mtd = &nor->mtd;
> -
> -		nor->dev = dev;
> -		spi_nor_set_flash_node(nor, np);
> -		nor->priv = q;
> -
> -		if (q->nor_num > 1 && !mtd->name) {
> -			int spiflash_idx;
> -
> -			ret = of_property_read_u32(np, "reg", &spiflash_idx);
> -			if (!ret) {
> -				mtd->name = devm_kasprintf(dev,
> GFP_KERNEL,
> -							   "%s-%d",
> -							   dev_name(dev),
> -							   spiflash_idx);
> -				if (!mtd->name) {
> -					ret = -ENOMEM;
> -					goto mutex_failed;
> -				}
> -			} else {
> -				dev_warn(dev, "reg property is missing\n");
> -			}
> -		}
> -
> -		/* fill the hooks */
> -		nor->read_reg = fsl_qspi_read_reg;
> -		nor->write_reg = fsl_qspi_write_reg;
> -		nor->read = fsl_qspi_read;
> -		nor->write = fsl_qspi_write;
> -		nor->erase = fsl_qspi_erase;
> -
> -		nor->prepare = fsl_qspi_prep;
> -		nor->unprepare = fsl_qspi_unprep;
> -
> -		ret = of_property_read_u32(np, "spi-max-frequency",
> -				&q->clk_rate);
> -		if (ret < 0)
> -			goto mutex_failed;
> -
> -		/* set the chip address for READID */
> -		fsl_qspi_set_base_addr(q, nor);
> -
> -		ret = spi_nor_scan(nor, NULL, &hwcaps);
> -		if (ret)
> -			goto mutex_failed;
> -
> -		ret = mtd_device_register(mtd, NULL, 0);
> -		if (ret)
> -			goto mutex_failed;
> -
> -		/* Set the correct NOR size now. */
> -		if (q->nor_size == 0) {
> -			q->nor_size = mtd->size;
> -
> -			/* Map the SPI NOR to accessiable address */
> -			fsl_qspi_set_map_addr(q);
> -		}
> -
> -		/*
> -		 * The TX FIFO is 64 bytes in the Vybrid, but the Page Program
> -		 * may writes 265 bytes per time. The write is working in the
> -		 * unit of the TX FIFO, not in the unit of the SPI NOR's page
> -		 * size.
> -		 *
> -		 * So shrink the spi_nor->page_size if it is larger then the
> -		 * TX FIFO.
> -		 */
> -		if (nor->page_size > q->devtype_data->txfifo)
> -			nor->page_size = q->devtype_data->txfifo;
> -
> -		i++;
> -	}
> -
> -	/* finish the rest init. */
> -	ret = fsl_qspi_nor_setup_last(q);
> -	if (ret)
> -		goto last_init_failed;
> -
> -	fsl_qspi_clk_disable_unprep(q);
> -	return 0;
> -
> -last_init_failed:
> -	for (i = 0; i < q->nor_num; i++) {
> -		/* skip the holes */
> -		if (!q->has_second_chip)
> -			i *= 2;
> -		mtd_device_unregister(&q->nor[i].mtd);
> -	}
> -mutex_failed:
> -	mutex_destroy(&q->lock);
> -irq_failed:
> -	fsl_qspi_clk_disable_unprep(q);
> -clk_failed:
> -	dev_err(dev, "Freescale QuadSPI probe failed\n");
> -	return ret;
> -}
> -
> -static int fsl_qspi_remove(struct platform_device *pdev) -{
> -	struct fsl_qspi *q = platform_get_drvdata(pdev);
> -	int i;
> -
> -	for (i = 0; i < q->nor_num; i++) {
> -		/* skip the holes */
> -		if (!q->has_second_chip)
> -			i *= 2;
> -		mtd_device_unregister(&q->nor[i].mtd);
> -	}
> -
> -	/* disable the hardware */
> -	qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase +
> QUADSPI_MCR);
> -	qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
> -
> -	mutex_destroy(&q->lock);
> -
> -	if (q->ahb_addr)
> -		iounmap(q->ahb_addr);
> -
> -	return 0;
> -}
> -
> -static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t
> state) -{
> -	return 0;
> -}
> -
> -static int fsl_qspi_resume(struct platform_device *pdev) -{
> -	int ret;
> -	struct fsl_qspi *q = platform_get_drvdata(pdev);
> -
> -	ret = fsl_qspi_clk_prep_enable(q);
> -	if (ret)
> -		return ret;
> -
> -	fsl_qspi_nor_setup(q);
> -	fsl_qspi_set_map_addr(q);
> -	fsl_qspi_nor_setup_last(q);
> -
> -	fsl_qspi_clk_disable_unprep(q);
> -
> -	return 0;
> -}
> -
> -static struct platform_driver fsl_qspi_driver = {
> -	.driver = {
> -		.name	= "fsl-quadspi",
> -		.of_match_table = fsl_qspi_dt_ids,
> -	},
> -	.probe          = fsl_qspi_probe,
> -	.remove		= fsl_qspi_remove,
> -	.suspend	= fsl_qspi_suspend,
> -	.resume		= fsl_qspi_resume,
> -};
> -module_platform_driver(fsl_qspi_driver);
> -
> -MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver"); -
> MODULE_AUTHOR("Freescale Semiconductor Inc."); -MODULE_LICENSE("GPL
> v2");
> --
> 2.7.4

Acked-by: Han Xu <han.xu@nxp.com>
Tested-by: Han Xu <han.xu@nxp.com>

Re: [PATCH v7 6/9] mtd: fsl-quadspi: Remove the driver as it was replaced by spi-fsl-qspi.c

[Schrempf Frieder]

Hi Han,

On 14.12.18 18:05, Han Xu wrote:
> 
> 
>> -----Original Message-----
>> From: Schrempf Frieder <frieder.schrempf@kontron.de>
>> Sent: Tuesday, December 4, 2018 8:15 AM
>> To: linux-mtd@lists.infradead.org; boris.brezillon@bootlin.com; linux-
>> spi@vger.kernel.org; Marek Vasut <marek.vasut@gmail.com>
>> Cc: dwmw2@infradead.org; computersforpeace@gmail.com;
>> richard@nod.at; miquel.raynal@bootlin.com; broonie@kernel.org; David
>> Wolfe <david.wolfe@nxp.com>; Fabio Estevam <fabio.estevam@nxp.com>;
>> Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; Yogesh Narayan
>> Gaur <yogeshnarayan.gaur@nxp.com>; Han Xu <han.xu@nxp.com>;
>> shawnguo@kernel.org; Schrempf Frieder <frieder.schrempf@kontron.de>;
>> linux-kernel@vger.kernel.org
>> Subject: [PATCH v7 6/9] mtd: fsl-quadspi: Remove the driver as it was
>> replaced by spi-fsl-qspi.c
>>
>> From: Frieder Schrempf <frieder.schrempf@kontron.de>
>>
>> There's a new driver using the SPI memory interface of the SPI framework at
>> spi/spi-fsl-qspi.c, which can be used together with m25p80.c to replace the
>> functionality of this SPI NOR driver.
>>
>> The new driver is already in use and this code is not compiled anymore, so
>> let's remove it.
>>
>> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
>> ---
>>   drivers/mtd/spi-nor/fsl-quadspi.c | 1224 --------------------------------
>>   1 file changed, 1224 deletions(-)
>>
>> diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-
>> quadspi.c
>> deleted file mode 100644
>> index 1ff3430..0000000
>> --- a/drivers/mtd/spi-nor/fsl-quadspi.c
>> +++ /dev/null
>> @@ -1,1224 +0,0 @@
>> -/*
>> - * Freescale QuadSPI driver.
>> - *
>> - * Copyright (C) 2013 Freescale Semiconductor, Inc.
>> - *
>> - * This program is free software; you can redistribute it and/or modify
>> - * it under the terms of the GNU General Public License as published by
>> - * the Free Software Foundation; either version 2 of the License, or
>> - * (at your option) any later version.
>> - */
>> -#include <linux/kernel.h>
>> -#include <linux/module.h>
>> -#include <linux/interrupt.h>
>> -#include <linux/errno.h>
>> -#include <linux/platform_device.h>
>> -#include <linux/sched.h>
>> -#include <linux/delay.h>
>> -#include <linux/io.h>
>> -#include <linux/clk.h>
>> -#include <linux/err.h>
>> -#include <linux/of.h>
>> -#include <linux/of_device.h>
>> -#include <linux/timer.h>
>> -#include <linux/jiffies.h>
>> -#include <linux/completion.h>
>> -#include <linux/mtd/mtd.h>
>> -#include <linux/mtd/partitions.h>
>> -#include <linux/mtd/spi-nor.h>
>> -#include <linux/mutex.h>
>> -#include <linux/pm_qos.h>
>> -#include <linux/sizes.h>
>> -
>> -/* Controller needs driver to swap endian */
>> -#define QUADSPI_QUIRK_SWAP_ENDIAN	(1 << 0)
>> -/* Controller needs 4x internal clock */
>> -#define QUADSPI_QUIRK_4X_INT_CLK	(1 << 1)
>> -/*
>> - * TKT253890, Controller needs driver to fill txfifo till 16 byte to
>> - * trigger data transfer even though extern data will not transferred.
>> - */
>> -#define QUADSPI_QUIRK_TKT253890		(1 << 2)
>> -/* Controller cannot wake up from wait mode, TKT245618 */
>> -#define QUADSPI_QUIRK_TKT245618         (1 << 3)
>> -
>> -/* The registers */
>> -#define QUADSPI_MCR			0x00
>> -#define QUADSPI_MCR_RESERVED_SHIFT	16
>> -#define QUADSPI_MCR_RESERVED_MASK	(0xF <<
>> QUADSPI_MCR_RESERVED_SHIFT)
>> -#define QUADSPI_MCR_MDIS_SHIFT		14
>> -#define QUADSPI_MCR_MDIS_MASK		(1 <<
>> QUADSPI_MCR_MDIS_SHIFT)
>> -#define QUADSPI_MCR_CLR_TXF_SHIFT	11
>> -#define QUADSPI_MCR_CLR_TXF_MASK	(1 <<
>> QUADSPI_MCR_CLR_TXF_SHIFT)
>> -#define QUADSPI_MCR_CLR_RXF_SHIFT	10
>> -#define QUADSPI_MCR_CLR_RXF_MASK	(1 <<
>> QUADSPI_MCR_CLR_RXF_SHIFT)
>> -#define QUADSPI_MCR_DDR_EN_SHIFT	7
>> -#define QUADSPI_MCR_DDR_EN_MASK		(1 <<
>> QUADSPI_MCR_DDR_EN_SHIFT)
>> -#define QUADSPI_MCR_END_CFG_SHIFT	2
>> -#define QUADSPI_MCR_END_CFG_MASK	(3 <<
>> QUADSPI_MCR_END_CFG_SHIFT)
>> -#define QUADSPI_MCR_SWRSTHD_SHIFT	1
>> -#define QUADSPI_MCR_SWRSTHD_MASK	(1 <<
>> QUADSPI_MCR_SWRSTHD_SHIFT)
>> -#define QUADSPI_MCR_SWRSTSD_SHIFT	0
>> -#define QUADSPI_MCR_SWRSTSD_MASK	(1 <<
>> QUADSPI_MCR_SWRSTSD_SHIFT)
>> -
>> -#define QUADSPI_IPCR			0x08
>> -#define QUADSPI_IPCR_SEQID_SHIFT	24
>> -#define QUADSPI_IPCR_SEQID_MASK		(0xF <<
>> QUADSPI_IPCR_SEQID_SHIFT)
>> -
>> -#define QUADSPI_BUF0CR			0x10
>> -#define QUADSPI_BUF1CR			0x14
>> -#define QUADSPI_BUF2CR			0x18
>> -#define QUADSPI_BUFXCR_INVALID_MSTRID	0xe
>> -
>> -#define QUADSPI_BUF3CR			0x1c
>> -#define QUADSPI_BUF3CR_ALLMST_SHIFT	31
>> -#define QUADSPI_BUF3CR_ALLMST_MASK	(1 <<
>> QUADSPI_BUF3CR_ALLMST_SHIFT)
>> -#define QUADSPI_BUF3CR_ADATSZ_SHIFT		8
>> -#define QUADSPI_BUF3CR_ADATSZ_MASK	(0xFF <<
>> QUADSPI_BUF3CR_ADATSZ_SHIFT)
>> -
>> -#define QUADSPI_BFGENCR			0x20
>> -#define QUADSPI_BFGENCR_PAR_EN_SHIFT	16
>> -#define QUADSPI_BFGENCR_PAR_EN_MASK	(1 <<
>> (QUADSPI_BFGENCR_PAR_EN_SHIFT))
>> -#define QUADSPI_BFGENCR_SEQID_SHIFT	12
>> -#define QUADSPI_BFGENCR_SEQID_MASK	(0xF <<
>> QUADSPI_BFGENCR_SEQID_SHIFT)
>> -
>> -#define QUADSPI_BUF0IND			0x30
>> -#define QUADSPI_BUF1IND			0x34
>> -#define QUADSPI_BUF2IND			0x38
>> -#define QUADSPI_SFAR			0x100
>> -
>> -#define QUADSPI_SMPR			0x108
>> -#define QUADSPI_SMPR_DDRSMP_SHIFT	16
>> -#define QUADSPI_SMPR_DDRSMP_MASK	(7 <<
>> QUADSPI_SMPR_DDRSMP_SHIFT)
>> -#define QUADSPI_SMPR_FSDLY_SHIFT	6
>> -#define QUADSPI_SMPR_FSDLY_MASK		(1 <<
>> QUADSPI_SMPR_FSDLY_SHIFT)
>> -#define QUADSPI_SMPR_FSPHS_SHIFT	5
>> -#define QUADSPI_SMPR_FSPHS_MASK		(1 <<
>> QUADSPI_SMPR_FSPHS_SHIFT)
>> -#define QUADSPI_SMPR_HSENA_SHIFT	0
>> -#define QUADSPI_SMPR_HSENA_MASK		(1 <<
>> QUADSPI_SMPR_HSENA_SHIFT)
>> -
>> -#define QUADSPI_RBSR			0x10c
>> -#define QUADSPI_RBSR_RDBFL_SHIFT	8
>> -#define QUADSPI_RBSR_RDBFL_MASK		(0x3F <<
>> QUADSPI_RBSR_RDBFL_SHIFT)
>> -
>> -#define QUADSPI_RBCT			0x110
>> -#define QUADSPI_RBCT_WMRK_MASK		0x1F
>> -#define QUADSPI_RBCT_RXBRD_SHIFT	8
>> -#define QUADSPI_RBCT_RXBRD_USEIPS	(0x1 <<
>> QUADSPI_RBCT_RXBRD_SHIFT)
>> -
>> -#define QUADSPI_TBSR			0x150
>> -#define QUADSPI_TBDR			0x154
>> -#define QUADSPI_SR			0x15c
>> -#define QUADSPI_SR_IP_ACC_SHIFT		1
>> -#define QUADSPI_SR_IP_ACC_MASK		(0x1 <<
>> QUADSPI_SR_IP_ACC_SHIFT)
>> -#define QUADSPI_SR_AHB_ACC_SHIFT	2
>> -#define QUADSPI_SR_AHB_ACC_MASK		(0x1 <<
>> QUADSPI_SR_AHB_ACC_SHIFT)
>> -
>> -#define QUADSPI_FR			0x160
>> -#define QUADSPI_FR_TFF_MASK		0x1
>> -
>> -#define QUADSPI_SFA1AD			0x180
>> -#define QUADSPI_SFA2AD			0x184
>> -#define QUADSPI_SFB1AD			0x188
>> -#define QUADSPI_SFB2AD			0x18c
>> -#define QUADSPI_RBDR			0x200
>> -
>> -#define QUADSPI_LUTKEY			0x300
>> -#define QUADSPI_LUTKEY_VALUE		0x5AF05AF0
>> -
>> -#define QUADSPI_LCKCR			0x304
>> -#define QUADSPI_LCKER_LOCK		0x1
>> -#define QUADSPI_LCKER_UNLOCK		0x2
>> -
>> -#define QUADSPI_RSER			0x164
>> -#define QUADSPI_RSER_TFIE		(0x1 << 0)
>> -
>> -#define QUADSPI_LUT_BASE		0x310
>> -
>> -/*
>> - * The definition of the LUT register shows below:
>> - *
>> - *  ---------------------------------------------------
>> - *  | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
>> - *  ---------------------------------------------------
>> - */
>> -#define OPRND0_SHIFT		0
>> -#define PAD0_SHIFT		8
>> -#define INSTR0_SHIFT		10
>> -#define OPRND1_SHIFT		16
>> -
>> -/* Instruction set for the LUT register. */
>> -#define LUT_STOP		0
>> -#define LUT_CMD			1
>> -#define LUT_ADDR		2
>> -#define LUT_DUMMY		3
>> -#define LUT_MODE		4
>> -#define LUT_MODE2		5
>> -#define LUT_MODE4		6
>> -#define LUT_FSL_READ		7
>> -#define LUT_FSL_WRITE		8
>> -#define LUT_JMP_ON_CS		9
>> -#define LUT_ADDR_DDR		10
>> -#define LUT_MODE_DDR		11
>> -#define LUT_MODE2_DDR		12
>> -#define LUT_MODE4_DDR		13
>> -#define LUT_FSL_READ_DDR		14
>> -#define LUT_FSL_WRITE_DDR		15
>> -#define LUT_DATA_LEARN		16
>> -
>> -/*
>> - * The PAD definitions for LUT register.
>> - *
>> - * The pad stands for the lines number of IO[0:3].
>> - * For example, the Quad read need four IO lines, so you should
>> - * set LUT_PAD4 which means we use four IO lines.
>> - */
>> -#define LUT_PAD1		0
>> -#define LUT_PAD2		1
>> -#define LUT_PAD4		2
>> -
>> -/* Oprands for the LUT register. */
>> -#define ADDR24BIT		0x18
>> -#define ADDR32BIT		0x20
>> -
>> -/* Macros for constructing the LUT register. */
>> -#define LUT0(ins, pad, opr)						\
>> -		(((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
>> -		((LUT_##ins) << INSTR0_SHIFT))
>> -
>> -#define LUT1(ins, pad, opr)	(LUT0(ins, pad, opr) << OPRND1_SHIFT)
>> -
>> -/* other macros for LUT register. */
>> -#define QUADSPI_LUT(x)          (QUADSPI_LUT_BASE + (x) * 4)
>> -#define QUADSPI_LUT_NUM		64
>> -
>> -/* SEQID -- we can have 16 seqids at most. */
>> -#define SEQID_READ		0
>> -#define SEQID_WREN		1
>> -#define SEQID_WRDI		2
>> -#define SEQID_RDSR		3
>> -#define SEQID_SE		4
>> -#define SEQID_CHIP_ERASE	5
>> -#define SEQID_PP		6
>> -#define SEQID_RDID		7
>> -#define SEQID_WRSR		8
>> -#define SEQID_RDCR		9
>> -#define SEQID_EN4B		10
>> -#define SEQID_BRWR		11
>> -
>> -#define QUADSPI_MIN_IOMAP SZ_4M
>> -
>> -enum fsl_qspi_devtype {
>> -	FSL_QUADSPI_VYBRID,
>> -	FSL_QUADSPI_IMX6SX,
>> -	FSL_QUADSPI_IMX7D,
>> -	FSL_QUADSPI_IMX6UL,
>> -	FSL_QUADSPI_LS1021A,
>> -	FSL_QUADSPI_LS2080A,
>> -};
>> -
>> -struct fsl_qspi_devtype_data {
>> -	enum fsl_qspi_devtype devtype;
>> -	int rxfifo;
>> -	int txfifo;
>> -	int ahb_buf_size;
>> -	int driver_data;
>> -};
>> -
>> -static const struct fsl_qspi_devtype_data vybrid_data = {
>> -	.devtype = FSL_QUADSPI_VYBRID,
>> -	.rxfifo = 128,
>> -	.txfifo = 64,
>> -	.ahb_buf_size = 1024,
>> -	.driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
>> -};
>> -
>> -static const struct fsl_qspi_devtype_data imx6sx_data = {
>> -	.devtype = FSL_QUADSPI_IMX6SX,
>> -	.rxfifo = 128,
>> -	.txfifo = 512,
>> -	.ahb_buf_size = 1024,
>> -	.driver_data = QUADSPI_QUIRK_4X_INT_CLK
>> -		       | QUADSPI_QUIRK_TKT245618,
>> -};
>> -
>> -static const struct fsl_qspi_devtype_data imx7d_data = {
>> -	.devtype = FSL_QUADSPI_IMX7D,
>> -	.rxfifo = 512,
>> -	.txfifo = 512,
>> -	.ahb_buf_size = 1024,
>> -	.driver_data = QUADSPI_QUIRK_TKT253890
>> -		       | QUADSPI_QUIRK_4X_INT_CLK,
>> -};
>> -
>> -static const struct fsl_qspi_devtype_data imx6ul_data = {
>> -	.devtype = FSL_QUADSPI_IMX6UL,
>> -	.rxfifo = 128,
>> -	.txfifo = 512,
>> -	.ahb_buf_size = 1024,
>> -	.driver_data = QUADSPI_QUIRK_TKT253890
>> -		       | QUADSPI_QUIRK_4X_INT_CLK,
>> -};
>> -
>> -static struct fsl_qspi_devtype_data ls1021a_data = {
>> -	.devtype = FSL_QUADSPI_LS1021A,
>> -	.rxfifo = 128,
>> -	.txfifo = 64,
>> -	.ahb_buf_size = 1024,
>> -	.driver_data = 0,
>> -};
>> -
>> -static const struct fsl_qspi_devtype_data ls2080a_data = {
>> -	.devtype = FSL_QUADSPI_LS2080A,
>> -	.rxfifo = 128,
>> -	.txfifo = 64,
>> -	.ahb_buf_size = 1024,
>> -	.driver_data = QUADSPI_QUIRK_TKT253890,
>> -};
>> -
>> -
>> -#define FSL_QSPI_MAX_CHIP	4
>> -struct fsl_qspi {
>> -	struct spi_nor nor[FSL_QSPI_MAX_CHIP];
>> -	void __iomem *iobase;
>> -	void __iomem *ahb_addr;
>> -	u32 memmap_phy;
>> -	u32 memmap_offs;
>> -	u32 memmap_len;
>> -	struct clk *clk, *clk_en;
>> -	struct device *dev;
>> -	struct completion c;
>> -	const struct fsl_qspi_devtype_data *devtype_data;
>> -	u32 nor_size;
>> -	u32 nor_num;
>> -	u32 clk_rate;
>> -	unsigned int chip_base_addr; /* We may support two chips. */
>> -	bool has_second_chip;
>> -	bool big_endian;
>> -	struct mutex lock;
>> -	struct pm_qos_request pm_qos_req;
>> -};
>> -
>> -static inline int needs_swap_endian(struct fsl_qspi *q) -{
>> -	return q->devtype_data->driver_data &
>> QUADSPI_QUIRK_SWAP_ENDIAN;
>> -}
>> -
>> -static inline int needs_4x_clock(struct fsl_qspi *q) -{
>> -	return q->devtype_data->driver_data &
>> QUADSPI_QUIRK_4X_INT_CLK;
>> -}
>> -
>> -static inline int needs_fill_txfifo(struct fsl_qspi *q) -{
>> -	return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890;
>> -}
>> -
>> -static inline int needs_wakeup_wait_mode(struct fsl_qspi *q) -{
>> -	return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
>> -}
>> -
>> -/*
>> - * R/W functions for big- or little-endian registers:
>> - * The qSPI controller's endian is independent of the CPU core's endian.
>> - * So far, although the CPU core is little-endian but the qSPI have two
>> - * versions for big-endian and little-endian.
>> - */
>> -static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr) -{
>> -	if (q->big_endian)
>> -		iowrite32be(val, addr);
>> -	else
>> -		iowrite32(val, addr);
>> -}
>> -
>> -static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr) -{
>> -	if (q->big_endian)
>> -		return ioread32be(addr);
>> -	else
>> -		return ioread32(addr);
>> -}
>> -
>> -/*
>> - * An IC bug makes us to re-arrange the 32-bit data.
>> - * The following chips, such as IMX6SLX, have fixed this bug.
>> - */
>> -static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a) -{
>> -	return needs_swap_endian(q) ? __swab32(a) : a;
>> -}
>> -
>> -static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q) -{
>> -	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase +
>> QUADSPI_LUTKEY);
>> -	qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase +
>> QUADSPI_LCKCR);
>> -}
>> -
>> -static inline void fsl_qspi_lock_lut(struct fsl_qspi *q) -{
>> -	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase +
>> QUADSPI_LUTKEY);
>> -	qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
>> -}
>> -
>> -static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id) -{
>> -	struct fsl_qspi *q = dev_id;
>> -	u32 reg;
>> -
>> -	/* clear interrupt */
>> -	reg = qspi_readl(q, q->iobase + QUADSPI_FR);
>> -	qspi_writel(q, reg, q->iobase + QUADSPI_FR);
>> -
>> -	if (reg & QUADSPI_FR_TFF_MASK)
>> -		complete(&q->c);
>> -
>> -	dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q-
>>> chip_base_addr, reg);
>> -	return IRQ_HANDLED;
>> -}
>> -
>> -static void fsl_qspi_init_lut(struct fsl_qspi *q) -{
>> -	void __iomem *base = q->iobase;
>> -	int rxfifo = q->devtype_data->rxfifo;
>> -	u32 lut_base;
>> -	int i;
>> -
>> -	struct spi_nor *nor = &q->nor[0];
>> -	u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
>> -	u8 read_op = nor->read_opcode;
>> -	u8 read_dm = nor->read_dummy;
>> -
>> -	fsl_qspi_unlock_lut(q);
>> -
>> -	/* Clear all the LUT table */
>> -	for (i = 0; i < QUADSPI_LUT_NUM; i++)
>> -		qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
>> -
>> -	/* Read */
>> -	lut_base = SEQID_READ * 4;
>> -
>> -	qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1,
>> addrlen),
>> -			base + QUADSPI_LUT(lut_base));
>> -	qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
>> -		    LUT1(FSL_READ, PAD4, rxfifo),
>> -			base + QUADSPI_LUT(lut_base + 1));
>> -
>> -	/* Write enable */
>> -	lut_base = SEQID_WREN * 4;
>> -	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
>> -			base + QUADSPI_LUT(lut_base));
>> -
>> -	/* Page Program */
>> -	lut_base = SEQID_PP * 4;
>> -
>> -	qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
>> -		    LUT1(ADDR, PAD1, addrlen),
>> -			base + QUADSPI_LUT(lut_base));
>> -	qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
>> -			base + QUADSPI_LUT(lut_base + 1));
>> -
>> -	/* Read Status */
>> -	lut_base = SEQID_RDSR * 4;
>> -	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
>> -			LUT1(FSL_READ, PAD1, 0x1),
>> -			base + QUADSPI_LUT(lut_base));
>> -
>> -	/* Erase a sector */
>> -	lut_base = SEQID_SE * 4;
>> -
>> -	qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
>> -		    LUT1(ADDR, PAD1, addrlen),
>> -			base + QUADSPI_LUT(lut_base));
>> -
>> -	/* Erase the whole chip */
>> -	lut_base = SEQID_CHIP_ERASE * 4;
>> -	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
>> -			base + QUADSPI_LUT(lut_base));
>> -
>> -	/* READ ID */
>> -	lut_base = SEQID_RDID * 4;
>> -	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDID) |
>> -			LUT1(FSL_READ, PAD1, 0x8),
>> -			base + QUADSPI_LUT(lut_base));
>> -
>> -	/* Write Register */
>> -	lut_base = SEQID_WRSR * 4;
>> -	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRSR) |
>> -			LUT1(FSL_WRITE, PAD1, 0x2),
>> -			base + QUADSPI_LUT(lut_base));
>> -
>> -	/* Read Configuration Register */
>> -	lut_base = SEQID_RDCR * 4;
>> -	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDCR) |
>> -			LUT1(FSL_READ, PAD1, 0x1),
>> -			base + QUADSPI_LUT(lut_base));
>> -
>> -	/* Write disable */
>> -	lut_base = SEQID_WRDI * 4;
>> -	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRDI),
>> -			base + QUADSPI_LUT(lut_base));
>> -
>> -	/* Enter 4 Byte Mode (Micron) */
>> -	lut_base = SEQID_EN4B * 4;
>> -	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_EN4B),
>> -			base + QUADSPI_LUT(lut_base));
>> -
>> -	/* Enter 4 Byte Mode (Spansion) */
>> -	lut_base = SEQID_BRWR * 4;
>> -	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
>> -			base + QUADSPI_LUT(lut_base));
>> -
>> -	fsl_qspi_lock_lut(q);
>> -}
>> -
>> -/* Get the SEQID for the command */
>> -static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) -{
>> -	switch (cmd) {
>> -	case SPINOR_OP_READ_1_1_4:
>> -	case SPINOR_OP_READ_1_1_4_4B:
>> -		return SEQID_READ;
>> -	case SPINOR_OP_WREN:
>> -		return SEQID_WREN;
>> -	case SPINOR_OP_WRDI:
>> -		return SEQID_WRDI;
>> -	case SPINOR_OP_RDSR:
>> -		return SEQID_RDSR;
>> -	case SPINOR_OP_SE:
>> -		return SEQID_SE;
>> -	case SPINOR_OP_CHIP_ERASE:
>> -		return SEQID_CHIP_ERASE;
>> -	case SPINOR_OP_PP:
>> -		return SEQID_PP;
>> -	case SPINOR_OP_RDID:
>> -		return SEQID_RDID;
>> -	case SPINOR_OP_WRSR:
>> -		return SEQID_WRSR;
>> -	case SPINOR_OP_RDCR:
>> -		return SEQID_RDCR;
>> -	case SPINOR_OP_EN4B:
>> -		return SEQID_EN4B;
>> -	case SPINOR_OP_BRWR:
>> -		return SEQID_BRWR;
>> -	default:
>> -		if (cmd == q->nor[0].erase_opcode)
>> -			return SEQID_SE;
>> -		dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
>> -		break;
>> -	}
>> -	return -EINVAL;
>> -}
>> -
>> -static int
>> -fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len) -{
>> -	void __iomem *base = q->iobase;
>> -	int seqid;
>> -	u32 reg, reg2;
>> -	int err;
>> -
>> -	init_completion(&q->c);
>> -	dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
>> -			q->chip_base_addr, addr, len, cmd);
>> -
>> -	/* save the reg */
>> -	reg = qspi_readl(q, base + QUADSPI_MCR);
>> -
>> -	qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
>> -			base + QUADSPI_SFAR);
>> -	qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
>> QUADSPI_RBCT_RXBRD_USEIPS,
>> -			base + QUADSPI_RBCT);
>> -	qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base +
>> QUADSPI_MCR);
>> -
>> -	do {
>> -		reg2 = qspi_readl(q, base + QUADSPI_SR);
>> -		if (reg2 & (QUADSPI_SR_IP_ACC_MASK |
>> QUADSPI_SR_AHB_ACC_MASK)) {
>> -			udelay(1);
>> -			dev_dbg(q->dev, "The controller is busy, 0x%x\n",
>> reg2);
>> -			continue;
>> -		}
>> -		break;
>> -	} while (1);
>> -
>> -	/* trigger the LUT now */
>> -	seqid = fsl_qspi_get_seqid(q, cmd);
>> -	if (seqid < 0)
>> -		return seqid;
>> -
>> -	qspi_writel(q, (seqid << QUADSPI_IPCR_SEQID_SHIFT) | len,
>> -			base + QUADSPI_IPCR);
>> -
>> -	/* Wait for the interrupt. */
>> -	if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) {
>> -		dev_err(q->dev,
>> -			"cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x,
>> SR:0x%.8x\n",
>> -			cmd, addr, qspi_readl(q, base + QUADSPI_FR),
>> -			qspi_readl(q, base + QUADSPI_SR));
>> -		err = -ETIMEDOUT;
>> -	} else {
>> -		err = 0;
>> -	}
>> -
>> -	/* restore the MCR */
>> -	qspi_writel(q, reg, base + QUADSPI_MCR);
>> -
>> -	return err;
>> -}
>> -
>> -/* Read out the data from the QUADSPI_RBDR buffer registers. */ -static
>> void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf) -{
>> -	u32 tmp;
>> -	int i = 0;
>> -
>> -	while (len > 0) {
>> -		tmp = qspi_readl(q, q->iobase + QUADSPI_RBDR + i * 4);
>> -		tmp = fsl_qspi_endian_xchg(q, tmp);
>> -		dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
>> -				q->chip_base_addr, tmp);
>> -
>> -		if (len >= 4) {
>> -			*((u32 *)rxbuf) = tmp;
>> -			rxbuf += 4;
>> -		} else {
>> -			memcpy(rxbuf, &tmp, len);
>> -			break;
>> -		}
>> -
>> -		len -= 4;
>> -		i++;
>> -	}
>> -}
>> -
>> -/*
>> - * If we have changed the content of the flash by writing or erasing,
>> - * we need to invalidate the AHB buffer. If we do not do so, we may read
>> out
>> - * the wrong data. The spec tells us reset the AHB domain and Serial Flash
>> - * domain at the same time.
>> - */
>> -static inline void fsl_qspi_invalid(struct fsl_qspi *q) -{
>> -	u32 reg;
>> -
>> -	reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
>> -	reg |= QUADSPI_MCR_SWRSTHD_MASK |
>> QUADSPI_MCR_SWRSTSD_MASK;
>> -	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
>> -
>> -	/*
>> -	 * The minimum delay : 1 AHB + 2 SFCK clocks.
>> -	 * Delay 1 us is enough.
>> -	 */
>> -	udelay(1);
>> -
>> -	reg &= ~(QUADSPI_MCR_SWRSTHD_MASK |
>> QUADSPI_MCR_SWRSTSD_MASK);
>> -	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
>> -}
>> -
>> -static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
>> -				u8 opcode, unsigned int to, u32 *txbuf,
>> -				unsigned count)
>> -{
>> -	int ret, i, j;
>> -	u32 tmp;
>> -
>> -	dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
>> -		q->chip_base_addr, to, count);
>> -
>> -	/* clear the TX FIFO. */
>> -	tmp = qspi_readl(q, q->iobase + QUADSPI_MCR);
>> -	qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase +
>> QUADSPI_MCR);
>> -
>> -	/* fill the TX data to the FIFO */
>> -	for (j = 0, i = ((count + 3) / 4); j < i; j++) {
>> -		tmp = fsl_qspi_endian_xchg(q, *txbuf);
>> -		qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
>> -		txbuf++;
>> -	}
>> -
>> -	/* fill the TXFIFO upto 16 bytes for i.MX7d */
>> -	if (needs_fill_txfifo(q))
>> -		for (; i < 4; i++)
>> -			qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
>> -
>> -	/* Trigger it */
>> -	ret = fsl_qspi_runcmd(q, opcode, to, count);
>> -
>> -	if (ret == 0)
>> -		return count;
>> -
>> -	return ret;
>> -}
>> -
>> -static void fsl_qspi_set_map_addr(struct fsl_qspi *q) -{
>> -	int nor_size = q->nor_size;
>> -	void __iomem *base = q->iobase;
>> -
>> -	qspi_writel(q, nor_size + q->memmap_phy, base +
>> QUADSPI_SFA1AD);
>> -	qspi_writel(q, nor_size * 2 + q->memmap_phy, base +
>> QUADSPI_SFA2AD);
>> -	qspi_writel(q, nor_size * 3 + q->memmap_phy, base +
>> QUADSPI_SFB1AD);
>> -	qspi_writel(q, nor_size * 4 + q->memmap_phy, base +
>> QUADSPI_SFB2AD);
>> -}
>> -
>> -/*
>> - * There are two different ways to read out the data from the flash:
>> - *  the "IP Command Read" and the "AHB Command Read".
>> - *
>> - * The IC guy suggests we use the "AHB Command Read" which is faster
>> - * then the "IP Command Read". (What's more is that there is a bug in
>> - * the "IP Command Read" in the Vybrid.)
>> - *
>> - * After we set up the registers for the "AHB Command Read", we can use
>> - * the memcpy to read the data directly. A "missed" access to the buffer
>> - * causes the controller to clear the buffer, and use the sequence pointed
>> - * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
>> - */
>> -static int fsl_qspi_init_ahb_read(struct fsl_qspi *q) -{
>> -	void __iomem *base = q->iobase;
>> -	int seqid;
>> -
>> -	/* AHB configuration for access buffer 0/1/2 .*/
>> -	qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base +
>> QUADSPI_BUF0CR);
>> -	qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base +
>> QUADSPI_BUF1CR);
>> -	qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base +
>> QUADSPI_BUF2CR);
>> -	/*
>> -	 * Set ADATSZ with the maximum AHB buffer size to improve the
>> -	 * read performance.
>> -	 */
>> -	qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
>> -			((q->devtype_data->ahb_buf_size / 8)
>> -			<< QUADSPI_BUF3CR_ADATSZ_SHIFT),
>> -			base + QUADSPI_BUF3CR);
>> -
>> -	/* We only use the buffer3 */
>> -	qspi_writel(q, 0, base + QUADSPI_BUF0IND);
>> -	qspi_writel(q, 0, base + QUADSPI_BUF1IND);
>> -	qspi_writel(q, 0, base + QUADSPI_BUF2IND);
>> -
>> -	/* Set the default lut sequence for AHB Read. */
>> -	seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
>> -	if (seqid < 0)
>> -		return seqid;
>> -
>> -	qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
>> -		q->iobase + QUADSPI_BFGENCR);
>> -
>> -	return 0;
>> -}
>> -
>> -/* This function was used to prepare and enable QSPI clock */ -static int
>> fsl_qspi_clk_prep_enable(struct fsl_qspi *q) -{
>> -	int ret;
>> -
>> -	ret = clk_prepare_enable(q->clk_en);
>> -	if (ret)
>> -		return ret;
>> -
>> -	ret = clk_prepare_enable(q->clk);
>> -	if (ret) {
>> -		clk_disable_unprepare(q->clk_en);
>> -		return ret;
>> -	}
>> -
>> -	if (needs_wakeup_wait_mode(q))
>> -		pm_qos_add_request(&q->pm_qos_req,
>> PM_QOS_CPU_DMA_LATENCY, 0);
>> -
>> -	return 0;
>> -}
>> -
>> -/* This function was used to disable and unprepare QSPI clock */ -static void
>> fsl_qspi_clk_disable_unprep(struct fsl_qspi *q) -{
>> -	if (needs_wakeup_wait_mode(q))
>> -		pm_qos_remove_request(&q->pm_qos_req);
>> -
>> -	clk_disable_unprepare(q->clk);
>> -	clk_disable_unprepare(q->clk_en);
>> -
>> -}
>> -
>> -/* We use this function to do some basic init for spi_nor_scan(). */ -static int
>> fsl_qspi_nor_setup(struct fsl_qspi *q) -{
>> -	void __iomem *base = q->iobase;
>> -	u32 reg;
>> -	int ret;
>> -
>> -	/* disable and unprepare clock to avoid glitch pass to controller */
>> -	fsl_qspi_clk_disable_unprep(q);
>> -
>> -	/* the default frequency, we will change it in the future. */
>> -	ret = clk_set_rate(q->clk, 66000000);
>> -	if (ret)
>> -		return ret;
>> -
>> -	ret = fsl_qspi_clk_prep_enable(q);
>> -	if (ret)
>> -		return ret;
>> -
>> -	/* Reset the module */
>> -	qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK |
>> QUADSPI_MCR_SWRSTHD_MASK,
>> -		base + QUADSPI_MCR);
>> -	udelay(1);
>> -
>> -	/* Init the LUT table. */
>> -	fsl_qspi_init_lut(q);
>> -
>> -	/* Disable the module */
>> -	qspi_writel(q, QUADSPI_MCR_MDIS_MASK |
>> QUADSPI_MCR_RESERVED_MASK,
>> -			base + QUADSPI_MCR);
>> -
>> -	reg = qspi_readl(q, base + QUADSPI_SMPR);
>> -	qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
>> -			| QUADSPI_SMPR_FSPHS_MASK
>> -			| QUADSPI_SMPR_HSENA_MASK
>> -			| QUADSPI_SMPR_DDRSMP_MASK), base +
>> QUADSPI_SMPR);
>> -
>> -	/* Enable the module */
>> -	qspi_writel(q, QUADSPI_MCR_RESERVED_MASK |
>> QUADSPI_MCR_END_CFG_MASK,
>> -			base + QUADSPI_MCR);
>> -
>> -	/* clear all interrupt status */
>> -	qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
>> -
>> -	/* enable the interrupt */
>> -	qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
>> -
>> -	return 0;
>> -}
>> -
>> -static int fsl_qspi_nor_setup_last(struct fsl_qspi *q) -{
>> -	unsigned long rate = q->clk_rate;
>> -	int ret;
>> -
>> -	if (needs_4x_clock(q))
>> -		rate *= 4;
>> -
>> -	/* disable and unprepare clock to avoid glitch pass to controller */
>> -	fsl_qspi_clk_disable_unprep(q);
>> -
>> -	ret = clk_set_rate(q->clk, rate);
>> -	if (ret)
>> -		return ret;
>> -
>> -	ret = fsl_qspi_clk_prep_enable(q);
>> -	if (ret)
>> -		return ret;
>> -
>> -	/* Init the LUT table again. */
>> -	fsl_qspi_init_lut(q);
>> -
>> -	/* Init for AHB read */
>> -	return fsl_qspi_init_ahb_read(q);
>> -}
>> -
>> -static const struct of_device_id fsl_qspi_dt_ids[] = {
>> -	{ .compatible = "fsl,vf610-qspi", .data = &vybrid_data, },
>> -	{ .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, },
>> -	{ .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, },
>> -	{ .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
>> -	{ .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
>> -	{ .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
>> -	{ /* sentinel */ }
>> -};
>> -MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
>> -
>> -static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor) -{
>> -	q->chip_base_addr = q->nor_size * (nor - q->nor);
>> -}
>> -
>> -static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
>> -{
>> -	int ret;
>> -	struct fsl_qspi *q = nor->priv;
>> -
>> -	ret = fsl_qspi_runcmd(q, opcode, 0, len);
>> -	if (ret)
>> -		return ret;
>> -
>> -	fsl_qspi_read_data(q, len, buf);
>> -	return 0;
>> -}
>> -
>> -static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
>> -{
>> -	struct fsl_qspi *q = nor->priv;
>> -	int ret;
>> -
>> -	if (!buf) {
>> -		ret = fsl_qspi_runcmd(q, opcode, 0, 1);
>> -		if (ret)
>> -			return ret;
>> -
>> -		if (opcode == SPINOR_OP_CHIP_ERASE)
>> -			fsl_qspi_invalid(q);
>> -
>> -	} else if (len > 0) {
>> -		ret = fsl_qspi_nor_write(q, nor, opcode, 0,
>> -					(u32 *)buf, len);
>> -		if (ret > 0)
>> -			return 0;
>> -	} else {
>> -		dev_err(q->dev, "invalid cmd %d\n", opcode);
>> -		ret = -EINVAL;
>> -	}
>> -
>> -	return ret;
>> -}
>> -
>> -static ssize_t fsl_qspi_write(struct spi_nor *nor, loff_t to,
>> -			      size_t len, const u_char *buf)
>> -{
>> -	struct fsl_qspi *q = nor->priv;
>> -	ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
>> -					 (u32 *)buf, len);
>> -
>> -	/* invalid the data in the AHB buffer. */
>> -	fsl_qspi_invalid(q);
>> -	return ret;
>> -}
>> -
>> -static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from,
>> -			     size_t len, u_char *buf)
>> -{
>> -	struct fsl_qspi *q = nor->priv;
>> -	u8 cmd = nor->read_opcode;
>> -
>> -	/* if necessary,ioremap buffer before AHB read, */
>> -	if (!q->ahb_addr) {
>> -		q->memmap_offs = q->chip_base_addr + from;
>> -		q->memmap_len = len > QUADSPI_MIN_IOMAP ? len :
>> QUADSPI_MIN_IOMAP;
>> -
>> -		q->ahb_addr = ioremap_nocache(
>> -				q->memmap_phy + q->memmap_offs,
>> -				q->memmap_len);
>> -		if (!q->ahb_addr) {
>> -			dev_err(q->dev, "ioremap failed\n");
>> -			return -ENOMEM;
>> -		}
>> -	/* ioremap if the data requested is out of range */
>> -	} else if (q->chip_base_addr + from < q->memmap_offs
>> -			|| q->chip_base_addr + from + len >
>> -			q->memmap_offs + q->memmap_len) {
>> -		iounmap(q->ahb_addr);
>> -
>> -		q->memmap_offs = q->chip_base_addr + from;
>> -		q->memmap_len = len > QUADSPI_MIN_IOMAP ? len :
>> QUADSPI_MIN_IOMAP;
>> -		q->ahb_addr = ioremap_nocache(
>> -				q->memmap_phy + q->memmap_offs,
>> -				q->memmap_len);
>> -		if (!q->ahb_addr) {
>> -			dev_err(q->dev, "ioremap failed\n");
>> -			return -ENOMEM;
>> -		}
>> -	}
>> -
>> -	dev_dbg(q->dev, "cmd [%x],read from %p, len:%zd\n",
>> -		cmd, q->ahb_addr + q->chip_base_addr + from - q-
>>> memmap_offs,
>> -		len);
>> -
>> -	/* Read out the data directly from the AHB buffer.*/
>> -	memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q-
>>> memmap_offs,
>> -		len);
>> -
>> -	return len;
>> -}
>> -
>> -static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs) -{
>> -	struct fsl_qspi *q = nor->priv;
>> -	int ret;
>> -
>> -	dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
>> -		nor->mtd.erasesize / 1024, q->chip_base_addr, (u32)offs);
>> -
>> -	ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
>> -	if (ret)
>> -		return ret;
>> -
>> -	fsl_qspi_invalid(q);
>> -	return 0;
>> -}
>> -
>> -static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops) -{
>> -	struct fsl_qspi *q = nor->priv;
>> -	int ret;
>> -
>> -	mutex_lock(&q->lock);
>> -
>> -	ret = fsl_qspi_clk_prep_enable(q);
>> -	if (ret)
>> -		goto err_mutex;
>> -
>> -	fsl_qspi_set_base_addr(q, nor);
>> -	return 0;
>> -
>> -err_mutex:
>> -	mutex_unlock(&q->lock);
>> -	return ret;
>> -}
>> -
>> -static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops) -{
>> -	struct fsl_qspi *q = nor->priv;
>> -
>> -	fsl_qspi_clk_disable_unprep(q);
>> -	mutex_unlock(&q->lock);
>> -}
>> -
>> -static int fsl_qspi_probe(struct platform_device *pdev) -{
>> -	const struct spi_nor_hwcaps hwcaps = {
>> -		.mask = SNOR_HWCAPS_READ_1_1_4 |
>> -			SNOR_HWCAPS_PP,
>> -	};
>> -	struct device_node *np = pdev->dev.of_node;
>> -	struct device *dev = &pdev->dev;
>> -	struct fsl_qspi *q;
>> -	struct resource *res;
>> -	struct spi_nor *nor;
>> -	struct mtd_info *mtd;
>> -	int ret, i = 0;
>> -
>> -	q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
>> -	if (!q)
>> -		return -ENOMEM;
>> -
>> -	q->nor_num = of_get_child_count(dev->of_node);
>> -	if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
>> -		return -ENODEV;
>> -
>> -	q->dev = dev;
>> -	q->devtype_data = of_device_get_match_data(dev);
>> -	if (!q->devtype_data)
>> -		return -ENODEV;
>> -	platform_set_drvdata(pdev, q);
>> -
>> -	/* find the resources */
>> -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
>> "QuadSPI");
>> -	q->iobase = devm_ioremap_resource(dev, res);
>> -	if (IS_ERR(q->iobase))
>> -		return PTR_ERR(q->iobase);
>> -
>> -	q->big_endian = of_property_read_bool(np, "big-endian");
>> -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
>> -					"QuadSPI-memory");
>> -	if (!devm_request_mem_region(dev, res->start, resource_size(res),
>> -				     res->name)) {
>> -		dev_err(dev, "can't request region for resource %pR\n", res);
>> -		return -EBUSY;
>> -	}
>> -
>> -	q->memmap_phy = res->start;
>> -
>> -	/* find the clocks */
>> -	q->clk_en = devm_clk_get(dev, "qspi_en");
>> -	if (IS_ERR(q->clk_en))
>> -		return PTR_ERR(q->clk_en);
>> -
>> -	q->clk = devm_clk_get(dev, "qspi");
>> -	if (IS_ERR(q->clk))
>> -		return PTR_ERR(q->clk);
>> -
>> -	ret = fsl_qspi_clk_prep_enable(q);
>> -	if (ret) {
>> -		dev_err(dev, "can not enable the clock\n");
>> -		goto clk_failed;
>> -	}
>> -
>> -	/* find the irq */
>> -	ret = platform_get_irq(pdev, 0);
>> -	if (ret < 0) {
>> -		dev_err(dev, "failed to get the irq: %d\n", ret);
>> -		goto irq_failed;
>> -	}
>> -
>> -	ret = devm_request_irq(dev, ret,
>> -			fsl_qspi_irq_handler, 0, pdev->name, q);
>> -	if (ret) {
>> -		dev_err(dev, "failed to request irq: %d\n", ret);
>> -		goto irq_failed;
>> -	}
>> -
>> -	ret = fsl_qspi_nor_setup(q);
>> -	if (ret)
>> -		goto irq_failed;
>> -
>> -	if (of_get_property(np, "fsl,qspi-has-second-chip", NULL))
>> -		q->has_second_chip = true;
>> -
>> -	mutex_init(&q->lock);
>> -
>> -	/* iterate the subnodes. */
>> -	for_each_available_child_of_node(dev->of_node, np) {
>> -		/* skip the holes */
>> -		if (!q->has_second_chip)
>> -			i *= 2;
>> -
>> -		nor = &q->nor[i];
>> -		mtd = &nor->mtd;
>> -
>> -		nor->dev = dev;
>> -		spi_nor_set_flash_node(nor, np);
>> -		nor->priv = q;
>> -
>> -		if (q->nor_num > 1 && !mtd->name) {
>> -			int spiflash_idx;
>> -
>> -			ret = of_property_read_u32(np, "reg", &spiflash_idx);
>> -			if (!ret) {
>> -				mtd->name = devm_kasprintf(dev,
>> GFP_KERNEL,
>> -							   "%s-%d",
>> -							   dev_name(dev),
>> -							   spiflash_idx);
>> -				if (!mtd->name) {
>> -					ret = -ENOMEM;
>> -					goto mutex_failed;
>> -				}
>> -			} else {
>> -				dev_warn(dev, "reg property is missing\n");
>> -			}
>> -		}
>> -
>> -		/* fill the hooks */
>> -		nor->read_reg = fsl_qspi_read_reg;
>> -		nor->write_reg = fsl_qspi_write_reg;
>> -		nor->read = fsl_qspi_read;
>> -		nor->write = fsl_qspi_write;
>> -		nor->erase = fsl_qspi_erase;
>> -
>> -		nor->prepare = fsl_qspi_prep;
>> -		nor->unprepare = fsl_qspi_unprep;
>> -
>> -		ret = of_property_read_u32(np, "spi-max-frequency",
>> -				&q->clk_rate);
>> -		if (ret < 0)
>> -			goto mutex_failed;
>> -
>> -		/* set the chip address for READID */
>> -		fsl_qspi_set_base_addr(q, nor);
>> -
>> -		ret = spi_nor_scan(nor, NULL, &hwcaps);
>> -		if (ret)
>> -			goto mutex_failed;
>> -
>> -		ret = mtd_device_register(mtd, NULL, 0);
>> -		if (ret)
>> -			goto mutex_failed;
>> -
>> -		/* Set the correct NOR size now. */
>> -		if (q->nor_size == 0) {
>> -			q->nor_size = mtd->size;
>> -
>> -			/* Map the SPI NOR to accessiable address */
>> -			fsl_qspi_set_map_addr(q);
>> -		}
>> -
>> -		/*
>> -		 * The TX FIFO is 64 bytes in the Vybrid, but the Page Program
>> -		 * may writes 265 bytes per time. The write is working in the
>> -		 * unit of the TX FIFO, not in the unit of the SPI NOR's page
>> -		 * size.
>> -		 *
>> -		 * So shrink the spi_nor->page_size if it is larger then the
>> -		 * TX FIFO.
>> -		 */
>> -		if (nor->page_size > q->devtype_data->txfifo)
>> -			nor->page_size = q->devtype_data->txfifo;
>> -
>> -		i++;
>> -	}
>> -
>> -	/* finish the rest init. */
>> -	ret = fsl_qspi_nor_setup_last(q);
>> -	if (ret)
>> -		goto last_init_failed;
>> -
>> -	fsl_qspi_clk_disable_unprep(q);
>> -	return 0;
>> -
>> -last_init_failed:
>> -	for (i = 0; i < q->nor_num; i++) {
>> -		/* skip the holes */
>> -		if (!q->has_second_chip)
>> -			i *= 2;
>> -		mtd_device_unregister(&q->nor[i].mtd);
>> -	}
>> -mutex_failed:
>> -	mutex_destroy(&q->lock);
>> -irq_failed:
>> -	fsl_qspi_clk_disable_unprep(q);
>> -clk_failed:
>> -	dev_err(dev, "Freescale QuadSPI probe failed\n");
>> -	return ret;
>> -}
>> -
>> -static int fsl_qspi_remove(struct platform_device *pdev) -{
>> -	struct fsl_qspi *q = platform_get_drvdata(pdev);
>> -	int i;
>> -
>> -	for (i = 0; i < q->nor_num; i++) {
>> -		/* skip the holes */
>> -		if (!q->has_second_chip)
>> -			i *= 2;
>> -		mtd_device_unregister(&q->nor[i].mtd);
>> -	}
>> -
>> -	/* disable the hardware */
>> -	qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase +
>> QUADSPI_MCR);
>> -	qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
>> -
>> -	mutex_destroy(&q->lock);
>> -
>> -	if (q->ahb_addr)
>> -		iounmap(q->ahb_addr);
>> -
>> -	return 0;
>> -}
>> -
>> -static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t
>> state) -{
>> -	return 0;
>> -}
>> -
>> -static int fsl_qspi_resume(struct platform_device *pdev) -{
>> -	int ret;
>> -	struct fsl_qspi *q = platform_get_drvdata(pdev);
>> -
>> -	ret = fsl_qspi_clk_prep_enable(q);
>> -	if (ret)
>> -		return ret;
>> -
>> -	fsl_qspi_nor_setup(q);
>> -	fsl_qspi_set_map_addr(q);
>> -	fsl_qspi_nor_setup_last(q);
>> -
>> -	fsl_qspi_clk_disable_unprep(q);
>> -
>> -	return 0;
>> -}
>> -
>> -static struct platform_driver fsl_qspi_driver = {
>> -	.driver = {
>> -		.name	= "fsl-quadspi",
>> -		.of_match_table = fsl_qspi_dt_ids,
>> -	},
>> -	.probe          = fsl_qspi_probe,
>> -	.remove		= fsl_qspi_remove,
>> -	.suspend	= fsl_qspi_suspend,
>> -	.resume		= fsl_qspi_resume,
>> -};
>> -module_platform_driver(fsl_qspi_driver);
>> -
>> -MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver"); -
>> MODULE_AUTHOR("Freescale Semiconductor Inc."); -MODULE_LICENSE("GPL
>> v2");
>> --
>> 2.7.4
> 
> Acked-by: Han Xu <han.xu@nxp.com>
> Tested-by: Han Xu <han.xu@nxp.com>

Could you also add the tags to the patch that adds the new driver?
https://patchwork.ozlabs.org/patch/1007650/

Thanks,
Frieder

[PATCH v7 7/9] ARM: dts: ls1021a: Remove fsl,qspi-has-second-chip as it is not used

[Schrempf Frieder]

From: Frieder Schrempf <frieder.schrempf@kontron.de>

After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.

The driver now uses the 'reg' property to determine the bus and
the chipselect.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
---
 arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
index 6a83f30..d3a1a73 100644
--- a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
+++ b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
@@ -203,7 +203,6 @@
 };
 
 &qspi {
-	fsl,qspi-has-second-chip;
 	status = "okay";
 
 	flash: flash@0 {
-- 
2.7.4

[PATCH v7 8/9] ARM64: dts: ls1046a: Remove fsl,qspi-has-second-chip as it is not used

[Schrempf Frieder]

From: Frieder Schrempf <frieder.schrempf@kontron.de>

After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.

The driver now uses the 'reg' property to determine the bus and
the chipselect.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
---
 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 51cbd50..9e083f6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -213,7 +213,6 @@
 			clock-names = "qspi_en", "qspi";
 			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 			big-endian;
-			fsl,qspi-has-second-chip;
 			status = "disabled";
 		};
 
-- 
2.7.4

[PATCH v7 9/9] MAINTAINERS: Move the Freescale QSPI driver to the SPI framework

[Schrempf Frieder]

From: Frieder Schrempf <frieder.schrempf@kontron.de>

The driver was ported to the SPI framework so it can be used as
a generic SPI memory driver and not only for SPI NOR.
Reflect this transition in the MAINTAINERS file.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
---
 MAINTAINERS | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 6682420..e2689ba 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5998,9 +5998,9 @@ F:	Documentation/devicetree/bindings/ptp/ptp-qoriq.txt
 
 FREESCALE QUAD SPI DRIVER
 M:	Han Xu <han.xu@nxp.com>
-L:	linux-mtd@lists.infradead.org
+L:	linux-spi@vger.kernel.org
 S:	Maintained
-F:	drivers/mtd/spi-nor/fsl-quadspi.c
+F:	drivers/spi/spi-fsl-qspi.c
 
 FREESCALE QUICC ENGINE LIBRARY
 M:	Qiang Zhao <qiang.zhao@nxp.com>
-- 
2.7.4