From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: <adrian.hunter@intel.com>, <ulf.hansson@linaro.org>,
<mperttunen@nvidia.com>
Cc: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-mmc@vger.kernel.org>,
Sowjanya Komatineni <skomatineni@nvidia.com>
Subject: [PATCH V6 0/2] HW Command Queue support for Tegra SDMMC
Date: Thu, 27 Dec 2018 13:58:00 -0800 [thread overview]
Message-ID: <1545947882-18875-1-git-send-email-skomatineni@nvidia.com> (raw)
This patch series is for HW Command Queue support for Tegra SDMMC.
Patch[2] adds HW Command Queue support for Tegra SDMMC and has
dependencies on other patches in this series as explained below.
Patch[1] SDMMC address range:
This patch defines exact register space for all the SDMMC
Controllers. Controllers supporting command queue are having
CQHCI register space from offset 0xF000.
Patch[2] uses address range of sdmmc controllers to identify command
queue supported controllers
Sowjanya Komatineni (2):
arm64: dtsi: Fix SDMMC address range
mmc: tegra: HW Command Queue Support for Tegra SDMMC
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 6 +-
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 +-
drivers/mmc/host/Kconfig | 1 +
drivers/mmc/host/sdhci-tegra.c | 107 ++++++++++++++++++++++++++++++-
drivers/mmc/host/sdhci.c | 6 +-
5 files changed, 117 insertions(+), 7 deletions(-)
--
2.7.4
next reply other threads:[~2018-12-27 21:58 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-27 21:58 Sowjanya Komatineni [this message]
2018-12-27 21:58 ` [PATCH V6 1/2] arm64: dtsi: Fix SDMMC address range Sowjanya Komatineni
2018-12-27 21:58 ` [PATCH V6 2/2] mmc: tegra: HW Command Queue Support for Tegra SDMMC Sowjanya Komatineni
2018-12-28 8:58 ` Adrian Hunter
2018-12-28 20:16 ` Sowjanya Komatineni
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