* MIPS: DTS: CI20 board DT updates.
@ 2019-01-30 13:14 Zhou Yanjie
2019-01-30 13:14 ` [PATCH 1/2] dt-bindings: MIPS: Add doc about Ingenic CPU node Zhou Yanjie
2019-01-30 13:14 ` [PATCH 2/2] DTS: CI20: Add CPU nodes and L2 cache nodes Zhou Yanjie
0 siblings, 2 replies; 4+ messages in thread
From: Zhou Yanjie @ 2019-01-30 13:14 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, devicetree, paul.burton, ralf, jhogan, robh+dt,
ezequiel, paul, mark.rutland, syq, jiaxun.yang, 772753199,
ulf.hansson, malat
Fix booting time warnings.
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] dt-bindings: MIPS: Add doc about Ingenic CPU node.
2019-01-30 13:14 MIPS: DTS: CI20 board DT updates Zhou Yanjie
@ 2019-01-30 13:14 ` Zhou Yanjie
2019-02-25 16:17 ` Rob Herring
2019-01-30 13:14 ` [PATCH 2/2] DTS: CI20: Add CPU nodes and L2 cache nodes Zhou Yanjie
1 sibling, 1 reply; 4+ messages in thread
From: Zhou Yanjie @ 2019-01-30 13:14 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, devicetree, paul.burton, ralf, jhogan, robh+dt,
ezequiel, paul, mark.rutland, syq, jiaxun.yang, 772753199,
ulf.hansson, malat
Dt-bindings doc about CPU node of Ingenic XBurst based SOCs.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
.../devicetree/bindings/mips/ingenic/ingenic,cpu.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt
diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt
new file mode 100644
index 0000000..38e3cd3
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt
@@ -0,0 +1,17 @@
+Ingenic Soc CPU
+
+Required properties:
+- device_type: Must be "cpu".
+- compatible: One of:
+ - "ingenic,xburst".
+- reg: The number of the CPU.
+- next-level-cache: If there is a next level cache, point to it.
+
+Example:
+cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst";
+ reg = <0>;
+ next-level-cache = <&l2c>;
+};
+
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] DTS: CI20: Add CPU nodes and L2 cache nodes.
2019-01-30 13:14 MIPS: DTS: CI20 board DT updates Zhou Yanjie
2019-01-30 13:14 ` [PATCH 1/2] dt-bindings: MIPS: Add doc about Ingenic CPU node Zhou Yanjie
@ 2019-01-30 13:14 ` Zhou Yanjie
1 sibling, 0 replies; 4+ messages in thread
From: Zhou Yanjie @ 2019-01-30 13:14 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, devicetree, paul.burton, ralf, jhogan, robh+dt,
ezequiel, paul, mark.rutland, syq, jiaxun.yang, 772753199,
ulf.hansson, malat
Current kernels complain when booting on CI20:
[ 0.329630] cacheinfo: Failed to find cpu0 device node
[ 0.335023] cacheinfo: Unable to detect cache hierarchy for CPU 0
Add the CPU node and the L2 cache node, then let each CPU point to it.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index b03cdec..7c0a853 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -7,6 +7,31 @@
#size-cells = <1>;
compatible = "ingenic,jz4780";
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst";
+ reg = <0>;
+ next-level-cache = <&l2c>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst";
+ reg = <1>;
+ next-level-cache = <&l2c>;
+ clocks = <&cgu JZ4780_CLK_CORE1>;
+ };
+
+ l2c: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] dt-bindings: MIPS: Add doc about Ingenic CPU node.
2019-01-30 13:14 ` [PATCH 1/2] dt-bindings: MIPS: Add doc about Ingenic CPU node Zhou Yanjie
@ 2019-02-25 16:17 ` Rob Herring
0 siblings, 0 replies; 4+ messages in thread
From: Rob Herring @ 2019-02-25 16:17 UTC (permalink / raw)
To: Zhou Yanjie
Cc: linux-mips, linux-kernel, devicetree, paul.burton, ralf, jhogan,
ezequiel, paul, mark.rutland, syq, jiaxun.yang, 772753199,
ulf.hansson, malat
On Wed, Jan 30, 2019 at 09:14:03PM +0800, Zhou Yanjie wrote:
> Dt-bindings doc about CPU node of Ingenic XBurst based SOCs.
>
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
> ---
> .../devicetree/bindings/mips/ingenic/ingenic,cpu.txt | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt
>
> diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt
> new file mode 100644
> index 0000000..38e3cd3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt
> @@ -0,0 +1,17 @@
> +Ingenic Soc CPU
> +
> +Required properties:
> +- device_type: Must be "cpu".
> +- compatible: One of:
> + - "ingenic,xburst".
Only 1 version?
Is everything else discoverable or implied by this? Cache sizes,
instruction set features, bugs, etc.?
> +- reg: The number of the CPU.
Ideally, this should be based on some h/w id, but generally only SMP
processors have that.
BTW, is SMP supported? If so, you need to define how secondary cores get
booted (unless that is standard and implied).
> +- next-level-cache: If there is a next level cache, point to it.
> +
> +Example:
> +cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "ingenic,xburst";
> + reg = <0>;
> + next-level-cache = <&l2c>;
> +};
> +
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-02-25 16:17 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2019-01-30 13:14 MIPS: DTS: CI20 board DT updates Zhou Yanjie
2019-01-30 13:14 ` [PATCH 1/2] dt-bindings: MIPS: Add doc about Ingenic CPU node Zhou Yanjie
2019-02-25 16:17 ` Rob Herring
2019-01-30 13:14 ` [PATCH 2/2] DTS: CI20: Add CPU nodes and L2 cache nodes Zhou Yanjie
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