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From: Tomasz Figa <t.figa@samsung.com>
To: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: Chander Kashyap <chander.kashyap@linaro.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Kukjin Kim <kgene.kim@samsung.com>,
	Tomasz Figa <tomasz.figa@gmail.com>,
	"linux-samsung-soc@vger.kernel.org" 
	<linux-samsung-soc@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	Russell King - ARM Linux <linux@arm.linux.org.uk>,
	Jingoo Han <jg1.han@samsung.com>,
	Jonghwan Choi <jhbird.choi@samsung.com>,
	Abhilash Kesavan <a.kesavan@samsung.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"stable@vger.kernel.org" <stable@vger.kernel.org>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Arnd Bergmann <arnd@arndb.de>, Olof Johansson <olof@lixom.net>,
	Will Deacon <Will.Deacon@arm.com>,
	Stephen Boyd <sboyd@codeaurora.org>
Subject: Re: [PATCH] ARM: EXYNOS: Fix incorrect usage of S5P_ARM_CORE1_* registers
Date: Thu, 20 Jun 2013 12:16:55 +0200	[thread overview]
Message-ID: <1550511.tLVEbtuIcN@amdc1227> (raw)
In-Reply-To: <alpine.LFD.2.03.1306191110130.18597@syhkavp.arg>

On Wednesday 19 of June 2013 11:19:30 Nicolas Pitre wrote:
> On Wed, 19 Jun 2013, Tomasz Figa wrote:
> > On Wednesday 19 of June 2013 20:26:50 Chander Kashyap wrote:
> > > On 19 June 2013 19:58, Tomasz Figa <t.figa@samsung.com> wrote:
> > > > I mean, calculate register offset based on two parameters - cluster
> > > > ID
> > > > and>
> > > > 
> > > > CPU ID, like:
> > > >         ...
> > > >         
> > > >         u32 mpidr = cpu_logical_map(cpu);
> > > >         u32 phys_cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
> > > >         
> > > >         if (soc_is_exynosXXXX()) {
> > > >         
> > > >                 u32 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
> > > >                 
> > > >                 phys_cpu += EXYNOSXXXX_CPUS_PER_CLUSTER * cluster;
> > > >         
> > > >         }
> > > >         
> > > >         reg_base = S5P_ARM_CORE_CONFIGURATION(phys_cpu);
> > > >         __raw_writel(0, reg_base);
> > > 
> > > This does not seems to viable solution, as eg. clusterID for
> > > exynos4210 is 0x9 and exynos 4412 is 0xa.
> > 
> > We don't need to consider cluster ID for any SoC that has just one
> > cluster. That's why there is the if (soc_is_exynosXXXX()) clause,
> > where exynosXXXX is the SoC that we support and has more clusters.
> > 
> > > But if we wass the cpu nodes
> > > thru DT, the we can comfortably rely on the logical cpu number. Also
> > > EXYNOSXXXX_CPUS_PER_CLUSTER can vary from cluster to cluster.
> > 
> > There is nothing that prevents you from specifying the CPUs in DT in
> > different order. Moreover, even if you specify them in correct order,
> > there is nothing that prevents you from using any of the listed CPUs
> > as boot CPU, which will get the logical ID of 0.
> 
> Relying on the logical CPU number to index into hardware related
> register space is wrong, please don't do that.
> 
> If the MPIDR allocation isn't linear then this cannot be used either.
> 
> The best solution is probably to add this reg_base as a property of each
> CPU node in DT, and extract it at boot time to stash it into an array
> which can be indexed with the logical CPU number afterwards.

Currently we don't specify the cpu node in DT at all for Exynos 4210, 4212 
and 4412. It's sure that their device tree sources need to be modified to 
correct his, but since DT is considered an ABI, we should keep 
compatibility with old device tree blobs. 

This means that we can't strictly require this property to be present in 
device tree, because it will break existing boards with older device trees. 
So my suggestion is to user cluster ID and CPU ID to calculate the offset by 
default and add possibility to override it with a property in device tree 
if such need shows up.

What do you think?

Best regards,
Tomasz

> Nicolas
> --
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      reply	other threads:[~2013-06-20 10:17 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-06-18 15:26 [PATCH] ARM: EXYNOS: Fix incorrect usage of S5P_ARM_CORE1_* registers Tomasz Figa
2013-06-18 17:45 ` Tomasz Figa
2013-06-18 17:59   ` Kukjin Kim
2013-06-19 12:09     ` Chander Kashyap
2013-06-19 12:50       ` Tomasz Figa
2013-06-19 13:24         ` Chander Kashyap
2013-06-19 13:24         ` Lorenzo Pieralisi
2013-06-19 13:31           ` Chander Kashyap
2013-06-19 13:49           ` Tomasz Figa
2013-06-19 13:55             ` Chander Kashyap
2013-06-19 14:28               ` Tomasz Figa
2013-06-19 14:56                 ` Chander Kashyap
2013-06-19 15:01                   ` Tomasz Figa
2013-06-19 15:07                     ` Chander Kashyap
2013-06-19 15:19                     ` Nicolas Pitre
2013-06-20 10:16                       ` Tomasz Figa [this message]

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