From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0A26C43381 for ; Tue, 19 Feb 2019 02:46:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B03FB21773 for ; Tue, 19 Feb 2019 02:46:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727286AbfBSCqN (ORCPT ); Mon, 18 Feb 2019 21:46:13 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:55323 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726413AbfBSCqM (ORCPT ); Mon, 18 Feb 2019 21:46:12 -0500 X-UUID: b66e9a5f864d42d18f647a76ed5889f1-20190219 X-UUID: b66e9a5f864d42d18f647a76ed5889f1-20190219 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 641928010; Tue, 19 Feb 2019 10:46:00 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 19 Feb 2019 10:45:58 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 19 Feb 2019 10:45:57 +0800 Message-ID: <1550544357.4739.32.camel@mhfsdcap03> Subject: Re: [PATCH v7 3/6] dt-bindings: pinctrl: mt8183: add binding document From: Zhiyong Tao To: Rob Herring CC: Erin Lo , Linus Walleij , Matthias Brugger , Mark Rutland , Thomas Gleixner , Jason Cooper , Marc Zyngier , Greg Kroah-Hartman , Stephen Boyd , , srv_heupstream , , , , , , , , Date: Tue, 19 Feb 2019 10:45:57 +0800 In-Reply-To: <20190218163211.GB2714@bogus> References: <1550210558-30516-1-git-send-email-erin.lo@mediatek.com> <1550210558-30516-4-git-send-email-erin.lo@mediatek.com> <20190218163211.GB2714@bogus> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2019-02-18 at 10:32 -0600, Rob Herring wrote: > On Fri, Feb 15, 2019 at 02:02:35PM +0800, Erin Lo wrote: > > From: Zhiyong Tao > > > > The commit adds mt8183 compatible node in binding document. > > > > Signed-off-by: Zhiyong Tao > > Signed-off-by: Erin Lo > > --- > > .../devicetree/bindings/pinctrl/pinctrl-mt8183.txt | 115 +++++++++++++++++++++ > > 1 file changed, 115 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt > > new file mode 100644 > > index 0000000..364e673 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt > > @@ -0,0 +1,115 @@ > > +* Mediatek MT8183 Pin Controller > > + > > +The Mediatek's Pin controller is used to control SoC pins. > > + > > +Required properties: > > +- compatible: value should be one of the following. > > + "mediatek,mt8183-pinctrl", compatible with mt8183 pinctrl. > > +- gpio-controller : Marks the device node as a gpio controller. > > +- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO > > + binding is used, the amount of cells must be specified as 2. See the below > > + mentioned gpio binding representation for description of particular cells. > > +- gpio-ranges : gpio valid number range. > > +- reg: physicall address base for gpio base registers. There are nine > > + physicall address base in mt8183. They are 0x10005000, 0x11F20000, > > + 0x11E80000, 0x11E70000, 0x11E90000, 0x11D30000, 0x11D20000, 0x11C50000, > > + 0x11F30000. > > You don't need to list out each address, just what each address is. (Or > just '9 GPIO base addresses'.) ==>ok, we will change it. > > > + > > + Eg: <&pio 6 0> > > How is this an example of reg? Seems something is missing. > > > + <[phandle of the gpio controller node] > > + [line number within the gpio controller] > > + [flags]> > > + > > + Values for gpio specifier: > > + - Line number: is a value between 0 to 202. > > + - Flags: bit field of flags, as defined in . > > + Only the following flags are supported: > > + 0 - GPIO_ACTIVE_HIGH > > + 1 - GPIO_ACTIVE_LOW > > + > > +Optional properties: > > +- reg-names: gpio base register names. There are nine gpio base register > > + names in mt8183. They are "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4", > > + "iocfg5", "iocfg6", "iocfg7", "iocfg8". > > +- interrupt-controller: Marks the device node as an interrupt controller > > +- #interrupt-cells: Should be two. > > +- interrupts : The interrupt outputs from the controller. > > outputs? More than 1? If so, need to say what they are and the order. > ==> there is only use one interrupt in mt8183. we will change "interrupts" to "interrupt" in v8. > > + > > +Please refer to pinctrl-bindings.txt in this directory for details of the > > +common pinctrl bindings used by client devices. > > + > > +Subnode format > > +A pinctrl node should contain at least one subnodes representing the > > +pinctrl groups available on the machine. Each subnode will list the > > +pins it needs, and how they should be configured, with regard to muxer > > +configuration, pullups, drive strength, input enable/disable and input schmitt. > > + > > + node { > > + pinmux = ; > > + GENERIC_PINCONFIG; > > + }; > > + > > +Required properties: > > +- pinmux: integer array, represents gpio pin number and mux setting. > > + Supported pin number and mux varies for different SoCs, and are defined > > + as macros in boot/dts/-pinfunc.h directly. > > + > > +Optional properties: > > +- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable, > > + bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high, > > + input-schmitt-enable, input-schmitt-disable and drive-strength are valid. > > + > > + Some special pins have extra pull up strength, there are R0 and R1 pull-up > > + resistors available, but for user, it's only need to set R1R0 as 00, 01, 10 or 11. > > + So when config mediatek,pull-up-adv or mediatek,pull-down-adv, > > + it support arguments for those special pins. > > + > > + When config drive-strength, it can support some arguments, such as > > + MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h. > > + > > +Examples: > > + > > +#include "mt8183-pinfunc.h" > > + > > +... > > +{ > > + pio: pinctrl@10005000 { > > + compatible = "mediatek,mt8183-pinctrl"; > > + reg = <0 0x10005000 0 0x1000>, > > + <0 0x11F20000 0 0x1000>, > > + <0 0x11E80000 0 0x1000>, > > + <0 0x11E70000 0 0x1000>, > > + <0 0x11E90000 0 0x1000>, > > + <0 0x11D30000 0 0x1000>, > > + <0 0x11D20000 0 0x1000>, > > + <0 0x11C50000 0 0x1000>, > > + <0 0x11F30000 0 0x1000>; > > + reg-names = "iocfg0", "iocfg1", "iocfg2", > > + "iocfg3", "iocfg4", "iocfg5", > > + "iocfg6", "iocfg7", "iocfg8"; > > + gpio-controller; > > + #gpio-cells = <2>; > > + gpio-ranges = <&pio 0 0 192>; > > + interrupt-controller; > > + interrupts = ; > > + interrupt-parent = <&gic>; > > + #interrupt-cells = <2>; > > + > > + i2c0_pins_a: i2c0 { > > + pins1 { > > + pinmux = , > > + ; > > + mediatek,pull-up-adv = <11>; > > + }; > > + }; > > + > > + i2c1_pins_a: i2c1 { > > + pins { > > + pinmux = , > > + ; > > + mediatek,pull-down-adv = <10>; > > + }; > > + }; > > + ... > > + }; > > +}; > > -- > > 1.9.1 > >