From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53AAFC43381 for ; Wed, 13 Mar 2019 08:27:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0F8ED21855 for ; Wed, 13 Mar 2019 08:27:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726920AbfCMI1A (ORCPT ); Wed, 13 Mar 2019 04:27:00 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:23119 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726539AbfCMI07 (ORCPT ); Wed, 13 Mar 2019 04:26:59 -0400 X-UUID: 9f983502083646bca1a002186023192f-20190313 X-UUID: 9f983502083646bca1a002186023192f-20190313 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1729510662; Wed, 13 Mar 2019 16:26:52 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 13 Mar 2019 16:26:51 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 13 Mar 2019 16:26:51 +0800 Message-ID: <1552465611.21996.11.camel@mtksdaap41> Subject: Re: [PATCH v8 2/2] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile From: Erin Lo To: Matthias Brugger CC: Rob Herring , Mark Rutland , Thomas Gleixner , Jason Cooper , Marc Zyngier , Greg Kroah-Hartman , Stephen Boyd , , srv_heupstream , , , , , , , , , , , Ben Ho , Seiya Wang , Weiyi Lu , Hsin-Hsiung Wang Date: Wed, 13 Mar 2019 16:26:51 +0800 In-Reply-To: References: <1552294472-32929-1-git-send-email-erin.lo@mediatek.com> <1552294472-32929-3-git-send-email-erin.lo@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2019-03-12 at 13:22 +0100, Matthias Brugger wrote: > > On 11/03/2019 09:54, Erin Lo wrote: > > From: Ben Ho > > > > Add basic chip support for Mediatek 8183, include > > uart node with correct uart clocks, pwrap device > > > > Add clock controller nodes, include topckgen, infracfg, > > apmixedsys and subsystem. > > > > Signed-off-by: Ben Ho > > Signed-off-by: Erin Lo > > Signed-off-by: Seiya Wang > > Signed-off-by: Weiyi Lu > > Signed-off-by: Zhiyong Tao > > Signed-off-by: Hsin-Hsiung Wang > > Signed-off-by: Eddie Huang > > --- > > arch/arm64/boot/dts/mediatek/Makefile | 1 + > > arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 31 +++ > > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 335 ++++++++++++++++++++++++++++ > > 3 files changed, 367 insertions(+) > > create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts > > create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi > > > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile > > index e8f952f..458bbc4 100644 > > --- a/arch/arm64/boot/dts/mediatek/Makefile > > +++ b/arch/arm64/boot/dts/mediatek/Makefile > > @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb > > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > > new file mode 100644 > > index 0000000..9b52559 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > > @@ -0,0 +1,31 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* > > + * Copyright (c) 2018 MediaTek Inc. > > + * Author: Ben Ho > > + * Erin Lo > > + */ > > + > > +/dts-v1/; > > +#include "mt8183.dtsi" > > + > > +/ { > > + model = "MediaTek MT8183 evaluation board"; > > + compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; > > + > > + aliases { > > + serial0 = &uart0; > > + }; > > + > > + memory@40000000 { > > + device_type = "memory"; > > + reg = <0 0x40000000 0 0x80000000>; > > + }; > > + > > + chosen { > > + stdout-path = "serial0:921600n8"; > > + }; > > +}; > > + > > +&uart0 { > > + status = "okay"; > > +}; > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > > new file mode 100644 > > index 0000000..64f8bd6 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > > @@ -0,0 +1,335 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* > > + * Copyright (c) 2018 MediaTek Inc. > > + * Author: Ben Ho > > + * Erin Lo > > + */ > > + > > +#include > > +#include > > +#include > > + > > +/ { > > + compatible = "mediatek,mt8183"; > > + interrupt-parent = <&sysirq>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu-map { > > + cluster0 { > > + core0 { > > + cpu = <&cpu0>; > > + }; > > + core1 { > > + cpu = <&cpu1>; > > + }; > > + core2 { > > + cpu = <&cpu2>; > > + }; > > + core3 { > > + cpu = <&cpu3>; > > + }; > > + }; > > + > > + cluster1 { > > + core0 { > > + cpu = <&cpu4>; > > + }; > > + core1 { > > + cpu = <&cpu5>; > > + }; > > + core2 { > > + cpu = <&cpu6>; > > + }; > > + core3 { > > + cpu = <&cpu7>; > > + }; > > + }; > > + }; > > + > > + cpu0: cpu@0 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x000>; > > + enable-method = "psci"; > > + }; > > + > > + cpu1: cpu@1 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x001>; > > + enable-method = "psci"; > > + }; > > + > > + cpu2: cpu@2 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x002>; > > + enable-method = "psci"; > > + }; > > + > > + cpu3: cpu@3 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x003>; > > + enable-method = "psci"; > > + }; > > + > > + cpu4: cpu@100 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a73"; > > + reg = <0x100>; > > + enable-method = "psci"; > > + }; > > + > > + cpu5: cpu@101 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a73"; > > + reg = <0x101>; > > + enable-method = "psci"; > > + }; > > + > > + cpu6: cpu@102 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a73"; > > + reg = <0x102>; > > + enable-method = "psci"; > > + }; > > + > > + cpu7: cpu@103 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a73"; > > + reg = <0x103>; > > + enable-method = "psci"; > > + }; > > + }; > > + > > + pmu-a53 { > > + compatible = "arm,cortex-a53-pmu"; > > + interrupt-parent = <&gic>; > > + interrupts = ; > > + }; > > + > > + pmu-a73 { > > + compatible = "arm,cortex-a73-pmu"; > > + interrupt-parent = <&gic>; > > + interrupts = ; > > + }; > > + > > + psci { > > + compatible = "arm,psci-1.0"; > > + method = "smc"; > > + }; > > + > > + clk26m: oscillator { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <26000000>; > > + clock-output-names = "clk26m"; > > + }; > > + > > + timer { > > + compatible = "arm,armv8-timer"; > > + interrupt-parent = <&gic>; > > + interrupts = , > > + , > > + , > > + ; > > + }; > > + > > + soc { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + compatible = "simple-bus"; > > + ranges; > > + > > + gic: interrupt-controller@c000000 { > > + compatible = "arm,gic-v3"; > > + #interrupt-cells = <4>; > > + interrupt-parent = <&gic>; > > + interrupt-controller; > > + reg = <0 0x0c000000 0 0x40000>, /* GICD */ > > + <0 0x0c100000 0 0x200000>, /* GICR */ > > + <0 0x0c400000 0 0x2000>, /* GICC */ > > + <0 0x0c410000 0 0x1000>, /* GICH */ > > + <0 0x0c420000 0 0x2000>; /* GICV */ > > + > > + interrupts = ; > > + ppi-partitions { > > + ppi_cluster0: interrupt-partition-0 { > > + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; > > + }; > > + ppi_cluster1: interrupt-partition-1 { > > + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; > > + }; > > + }; > > + }; > > + > > + mcucfg: syscon@c530000 { > > + compatible = "mediatek,mt8183-mcucfg", "syscon"; > > Binding is not documented. I found some other bindings not documented as well. > Please update the binding documentation to add this compatible, otherwise I > won't be able to take this patch. > > Regards, > Matthias > The binding is http://lists.infradead.org/pipermail/linux-mediatek/2018-December/016249.html which is included in below series as cover letter mentioned. http://lists.infradead.org/pipermail/linux-mediatek/2018-December/016243.html Do you have any idea about how we arrange it in next version? > > + reg = <0 0x0c530000 0 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + sysirq: interrupt-controller@c530a80 { > > + compatible = "mediatek,mt8183-sysirq", > > + "mediatek,mt6577-sysirq"; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > + interrupt-parent = <&gic>; > > + reg = <0 0x0c530a80 0 0x50>; > > + }; > > + > > + topckgen: syscon@10000000 { > > + compatible = "mediatek,mt8183-topckgen", "syscon"; > > + reg = <0 0x10000000 0 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + infracfg: syscon@10001000 { > > + compatible = "mediatek,mt8183-infracfg", "syscon"; > > + reg = <0 0x10001000 0 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + pio: pinctrl@10005000 { > > + compatible = "mediatek,mt8183-pinctrl"; > > + reg = <0 0x10005000 0 0x1000>, > > + <0 0x11f20000 0 0x1000>, > > + <0 0x11e80000 0 0x1000>, > > + <0 0x11e70000 0 0x1000>, > > + <0 0x11e90000 0 0x1000>, > > + <0 0x11d30000 0 0x1000>, > > + <0 0x11d20000 0 0x1000>, > > + <0 0x11c50000 0 0x1000>, > > + <0 0x11f30000 0 0x1000>, > > + <0 0x1000b000 0 0x1000>; > > + reg-names = "iocfg0", "iocfg1", "iocfg2", > > + "iocfg3", "iocfg4", "iocfg5", > > + "iocfg6", "iocfg7", "iocfg8", > > + "eint"; > > + gpio-controller; > > + #gpio-cells = <2>; > > + gpio-ranges = <&pio 0 0 192>; > > + interrupt-controller; > > + interrupts = ; > > + #interrupt-cells = <3>; > > + }; I will remove it in next version since the binding is not ready. Best Regards, Erin. > > + > > + apmixedsys: syscon@1000c000 { > > + compatible = "mediatek,mt8183-apmixedsys", "syscon"; > > + reg = <0 0x1000c000 0 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + pwrap: pwrap@1000d000 { > > + compatible = "mediatek,mt8183-pwrap"; > > + reg = <0 0x1000d000 0 0x1000>; > > + reg-names = "pwrap"; > > + interrupts = ; > > + clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, > > + <&infracfg CLK_INFRA_PMIC_AP>; > > + clock-names = "spi", "wrap"; > > + }; > > + > > + uart0: serial@11002000 { > > + compatible = "mediatek,mt8183-uart", > > + "mediatek,mt6577-uart"; > > + reg = <0 0x11002000 0 0x1000>; > > + interrupts = ; > > + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; > > + clock-names = "baud", "bus"; > > + status = "disabled"; > > + }; > > + > > + uart1: serial@11003000 { > > + compatible = "mediatek,mt8183-uart", > > + "mediatek,mt6577-uart"; > > + reg = <0 0x11003000 0 0x1000>; > > + interrupts = ; > > + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; > > + clock-names = "baud", "bus"; > > + status = "disabled"; > > + }; > > + > > + uart2: serial@11004000 { > > + compatible = "mediatek,mt8183-uart", > > + "mediatek,mt6577-uart"; > > + reg = <0 0x11004000 0 0x1000>; > > + interrupts = ; > > + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; > > + clock-names = "baud", "bus"; > > + status = "disabled"; > > + }; > > + > > + audiosys: syscon@11220000 { > > + compatible = "mediatek,mt8183-audiosys", "syscon"; > > + reg = <0 0x11220000 0 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + mfgcfg: syscon@13000000 { > > + compatible = "mediatek,mt8183-mfgcfg", "syscon"; > > + reg = <0 0x13000000 0 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + mmsys: syscon@14000000 { > > + compatible = "mediatek,mt8183-mmsys", "syscon"; > > + reg = <0 0x14000000 0 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + imgsys: syscon@15020000 { > > + compatible = "mediatek,mt8183-imgsys", "syscon"; > > + reg = <0 0x15020000 0 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + vdecsys: syscon@16000000 { > > + compatible = "mediatek,mt8183-vdecsys", "syscon"; > > + reg = <0 0x16000000 0 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + vencsys: syscon@17000000 { > > + compatible = "mediatek,mt8183-vencsys", "syscon"; > > + reg = <0 0x17000000 0 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + ipu_conn: syscon@19000000 { > > + compatible = "mediatek,mt8183-ipu_conn", "syscon"; > > + reg = <0 0x19000000 0 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + ipu_adl: syscon@19010000 { > > + compatible = "mediatek,mt8183-ipu_adl", "syscon"; > > + reg = <0 0x19010000 0 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + ipu_core0: syscon@19180000 { > > + compatible = "mediatek,mt8183-ipu_core0", "syscon"; > > + reg = <0 0x19180000 0 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + ipu_core1: syscon@19280000 { > > + compatible = "mediatek,mt8183-ipu_core1", "syscon"; > > + reg = <0 0x19280000 0 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + camsys: syscon@1a000000 { > > + compatible = "mediatek,mt8183-camsys", "syscon"; > > + reg = <0 0x1a000000 0 0x1000>; > > + #clock-cells = <1>; > > + }; > > + }; > > +}; > >