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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: d3c9fbcb-0662-4ada-d895-08d6a899d04d X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Mar 2019 16:26:30.1142 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR11MB0061 X-OriginatorOrg: microchip.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Claudiu Beznea Hi, This series adds driver for Microchip PIT64B timer. Timer could be used in continuous or oneshot mode. It has 2x32 bit register= s to emulate a 64 bit timer. The timer's period could be configured via LSB_P= R and MSB_PR registers. The current timer's value could be checked via TLSB a= nd TMSB registers. When (TMSB << 32) | TLSB value reach the (MSB_PR << 32) | L= SB_PR interrupt is raised. If in contiuous mode the TLSB and TMSB resets and rest= art counting. This drivers uses PIT64B capabilities for clocksource and clockevent. The first requested PIT64B timer is used for clockevent. The second one is = used for clocksource. Individual PIT64B hardware resources were used for clockso= urce and clockevent to be able to support high resolution timers with this PIT64= B implementation. Thank you, Claudiu Beznea Claudiu Beznea (2): dt-bindings: arm: atmel: add bindings for PIT64B clocksource/drivers/timer-microchip-pit64b: add Microchip PIT64B support .../devicetree/bindings/arm/atmel-sysregs.txt | 7 + drivers/clocksource/Kconfig | 6 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-microchip-pit64b.c | 469 +++++++++++++++++= ++++ 4 files changed, 483 insertions(+) create mode 100644 drivers/clocksource/timer-microchip-pit64b.c --=20 2.7.4