From: Jacob Pan <jacob.jun.pan@linux.intel.com>
To: iommu@lists.linux-foundation.org,
LKML <linux-kernel@vger.kernel.org>,
Joerg Roedel <joro@8bytes.org>,
David Woodhouse <dwmw2@infradead.org>,
Alex Williamson <alex.williamson@redhat.com>,
Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Cc: "Yi Liu" <yi.l.liu@intel.com>,
"Tian, Kevin" <kevin.tian@intel.com>,
Raj Ashok <ashok.raj@intel.com>,
"Christoph Hellwig" <hch@infradead.org>,
"Lu Baolu" <baolu.lu@linux.intel.com>,
Andriy Shevchenko <andriy.shevchenko@linux.intel.com>,
Jacob Pan <jacob.jun.pan@linux.intel.com>
Subject: [PATCH 17/18] iommu/vt-d: Support flushing more translation cache types
Date: Mon, 8 Apr 2019 16:59:32 -0700 [thread overview]
Message-ID: <1554767973-30125-18-git-send-email-jacob.jun.pan@linux.intel.com> (raw)
In-Reply-To: <1554767973-30125-1-git-send-email-jacob.jun.pan@linux.intel.com>
When Shared Virtual Memory is exposed to a guest via vIOMMU, extended
IOTLB invalidation may be passed down from outside IOMMU subsystems.
This patch adds invalidation functions that can be used for additional
translation cache types.
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
---
drivers/iommu/dmar.c | 48 +++++++++++++++++++++++++++++++++++++++++++++
include/linux/intel-iommu.h | 21 ++++++++++++++++----
2 files changed, 65 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c
index 9c49300..680894e 100644
--- a/drivers/iommu/dmar.c
+++ b/drivers/iommu/dmar.c
@@ -1357,6 +1357,20 @@ void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
qi_submit_sync(&desc, iommu);
}
+void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u64 addr, u32 pasid,
+ unsigned int size_order, u64 granu)
+{
+ struct qi_desc desc;
+
+ desc.qw0 = QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) |
+ QI_EIOTLB_GRAN(granu) | QI_EIOTLB_TYPE;
+ desc.qw1 = QI_EIOTLB_ADDR(addr) | QI_EIOTLB_IH(0) |
+ QI_EIOTLB_AM(size_order);
+ desc.qw2 = 0;
+ desc.qw3 = 0;
+ qi_submit_sync(&desc, iommu);
+}
+
void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
u16 qdep, u64 addr, unsigned mask)
{
@@ -1380,6 +1394,40 @@ void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
qi_submit_sync(&desc, iommu);
}
+void qi_flush_dev_piotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
+ u32 pasid, u16 qdep, u64 addr, unsigned size, u64 granu)
+{
+ struct qi_desc desc;
+
+ desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) |
+ QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE |
+ QI_DEV_IOTLB_PFSID(pfsid);
+ desc.qw1 |= QI_DEV_EIOTLB_GLOB(granu);
+
+ /* If S bit is 0, we only flush a single page. If S bit is set,
+ * The least significant zero bit indicates the size. VT-d spec
+ * 6.5.2.6
+ */
+ if (!size)
+ desc.qw0 = QI_DEV_EIOTLB_ADDR(addr) & ~QI_DEV_EIOTLB_SIZE;
+ else {
+ unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size);
+
+ desc.qw1 = QI_DEV_EIOTLB_ADDR(addr & ~mask) | QI_DEV_EIOTLB_SIZE;
+ }
+ qi_submit_sync(&desc, iommu);
+}
+
+void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu, int pasid)
+{
+ struct qi_desc desc;
+
+ desc.qw0 = QI_PC_TYPE | QI_PC_DID(did) | QI_PC_GRAN(granu) | QI_PC_PASID(pasid);
+ desc.qw1 = 0;
+ desc.qw2 = 0;
+ desc.qw3 = 0;
+ qi_submit_sync(&desc, iommu);
+}
/*
* Disable Queued Invalidation interface.
*/
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index 29a615b..bbe53d5 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -339,7 +339,7 @@ enum {
#define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
#define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
#define QI_IOTLB_IH(ih) (((u64)ih) << 6)
-#define QI_IOTLB_AM(am) (((u8)am))
+#define QI_IOTLB_AM(am) (((u8)am) & 0x3f)
#define QI_CC_FM(fm) (((u64)fm) << 48)
#define QI_CC_SID(sid) (((u64)sid) << 32)
@@ -357,17 +357,22 @@ enum {
#define QI_PC_DID(did) (((u64)did) << 16)
#define QI_PC_GRAN(gran) (((u64)gran) << 4)
-#define QI_PC_ALL_PASIDS (QI_PC_TYPE | QI_PC_GRAN(0))
-#define QI_PC_PASID_SEL (QI_PC_TYPE | QI_PC_GRAN(1))
+/* PASID cache invalidation granu */
+#define QI_PC_ALL_PASIDS 0
+#define QI_PC_PASID_SEL 1
#define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
#define QI_EIOTLB_GL(gl) (((u64)gl) << 7)
#define QI_EIOTLB_IH(ih) (((u64)ih) << 6)
-#define QI_EIOTLB_AM(am) (((u64)am))
+#define QI_EIOTLB_AM(am) (((u64)am) & 0x3f)
#define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32)
#define QI_EIOTLB_DID(did) (((u64)did) << 16)
#define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4)
+/* QI Dev-IOTLB inv granu */
+#define QI_DEV_IOTLB_GRAN_ALL 1
+#define QI_DEV_IOTLB_GRAN_PASID_SEL 0
+
#define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
#define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
#define QI_DEV_EIOTLB_GLOB(g) ((u64)g)
@@ -646,8 +651,16 @@ extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
u8 fm, u64 type);
extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
unsigned int size_order, u64 type);
+extern void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u64 addr,
+ u32 pasid, unsigned int size_order, u64 type);
extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
u16 qdep, u64 addr, unsigned mask);
+
+extern void qi_flush_dev_piotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
+ u32 pasid, u16 qdep, u64 addr, unsigned size, u64 granu);
+
+extern void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu, int pasid);
+
extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
extern int dmar_ir_support(void);
--
2.7.4
next prev parent reply other threads:[~2019-04-08 23:57 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-08 23:59 [PATCH 00/18] Shared virtual address IOMMU and VT-d support Jacob Pan
2019-04-08 23:59 ` [PATCH 01/18] drivers core: Add I/O ASID allocator Jacob Pan
2019-04-09 10:00 ` Andriy Shevchenko
2019-04-09 10:04 ` Christoph Hellwig
2019-04-09 10:30 ` Andriy Shevchenko
2019-04-09 14:53 ` Paul E. McKenney
2019-04-09 15:21 ` Andriy Shevchenko
2019-04-09 22:08 ` Paul E. McKenney
2019-04-08 23:59 ` [PATCH 02/18] ioasid: Add custom IOASID allocator Jacob Pan
2019-04-15 18:53 ` Alex Williamson
2019-04-15 22:45 ` Jacob Pan
2019-04-08 23:59 ` [PATCH 03/18] ioasid: Convert ioasid_idr to XArray Jacob Pan
2019-04-08 23:59 ` [PATCH 04/18] driver core: add per device iommu param Jacob Pan
2019-04-08 23:59 ` [PATCH 05/18] iommu: introduce device fault data Jacob Pan
2019-04-09 10:03 ` Andriy Shevchenko
2019-04-09 16:44 ` Jacob Pan
2019-04-08 23:59 ` [PATCH 06/18] iommu: introduce device fault report API Jacob Pan
2019-04-08 23:59 ` [PATCH 07/18] iommu: Introduce attach/detach_pasid_table API Jacob Pan
2019-04-08 23:59 ` [PATCH 08/18] iommu: Introduce cache_invalidate API Jacob Pan
2019-04-09 10:07 ` Andriy Shevchenko
2019-04-09 16:43 ` Jacob Pan
2019-04-09 17:37 ` Andriy Shevchenko
2019-04-10 21:21 ` Jacob Pan
2019-04-11 10:02 ` Andriy Shevchenko
2019-04-08 23:59 ` [PATCH 09/18] iommu/vt-d: Enlightened PASID allocation Jacob Pan
2019-04-09 10:08 ` Andriy Shevchenko
2019-04-09 16:34 ` Jacob Pan
2019-04-08 23:59 ` [PATCH 10/18] iommu/vt-d: Add custom allocator for IOASID Jacob Pan
2019-04-15 20:37 ` Alex Williamson
2019-04-15 23:10 ` Jacob Pan
2019-04-18 15:36 ` Jean-Philippe Brucker
2019-04-19 4:29 ` Jacob Pan
2019-04-23 10:53 ` Jean-Philippe Brucker
2019-04-16 15:30 ` Jacob Pan
2019-04-08 23:59 ` [PATCH 11/18] iommu/vt-d: Replace Intel specific PASID allocator with IOASID Jacob Pan
2019-04-08 23:59 ` [PATCH 12/18] iommu: Add guest PASID bind function Jacob Pan
2019-04-08 23:59 ` [PATCH 13/18] iommu/vt-d: Move domain helper to header Jacob Pan
2019-04-08 23:59 ` [PATCH 14/18] iommu/vt-d: Add nested translation support Jacob Pan
2019-04-08 23:59 ` [PATCH 15/18] iommu/vt-d: Add bind guest PASID support Jacob Pan
2019-04-09 14:52 ` Andriy Shevchenko
2019-04-08 23:59 ` [PATCH 16/18] iommu: add max num of cache and granu types Jacob Pan
2019-04-09 14:53 ` Andriy Shevchenko
2019-04-08 23:59 ` Jacob Pan [this message]
2019-04-08 23:59 ` [PATCH 18/18] iommu/vt-d: Add svm/sva invalidate function Jacob Pan
2019-04-09 14:57 ` Andriy Shevchenko
2019-04-09 17:43 ` Jacob Pan
2019-04-09 9:56 ` [PATCH 00/18] Shared virtual address IOMMU and VT-d support Andriy Shevchenko
2019-04-09 16:33 ` Jacob Pan
2019-04-15 17:25 ` Jacob Pan
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