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Mon, 29 Apr 2019 09:54:45 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag4node3.st.com [10.75.127.12]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D7D7E14F5; Mon, 29 Apr 2019 09:54:44 +0000 (GMT) Received: from SFHDAG5NODE1.st.com (10.75.127.13) by SFHDAG4NODE3.st.com (10.75.127.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 29 Apr 2019 11:54:44 +0200 Received: from SFHDAG5NODE1.st.com ([fe80::cc53:528c:36c8:95f6]) by SFHDAG5NODE1.st.com ([fe80::cc53:528c:36c8:95f6%20]) with mapi id 15.00.1347.000; Mon, 29 Apr 2019 11:54:44 +0200 From: Gerald BAEZA To: "mturquette@baylibre.com" , "sboyd@kernel.org" , "mcoquelin.stm32@gmail.com" , Alexandre TORGUE CC: "linux-clk@vger.kernel.org" , "linux-stm32@st-md-mailman.stormreply.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Gabriel FERNANDEZ , Gerald BAEZA Subject: [PATCH 1/1] clk: stm32mp1: Add ddrperfm clock Thread-Topic: [PATCH 1/1] clk: stm32mp1: Add ddrperfm clock Thread-Index: AQHU/nGSI1KYPhvKvEC7x41++h176w== Date: Mon, 29 Apr 2019 09:54:44 +0000 Message-ID: <1556531652-27740-1-git-send-email-gerald.baeza@st.com> Accept-Language: fr-FR, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.47] Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-04-29_05:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Gabriel Fernandez Add ddrperfm clock for DDR Performance Monitor driver Signed-off-by: Gabriel Fernandez Signed-off-by: Gerald Baeza --- drivers/clk/clk-stm32mp1.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index a0ae8dc..a875649 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -1402,6 +1402,7 @@ enum { G_CRYP1, G_HASH1, G_BKPSRAM, + G_DDRPERFM, =20 G_LAST }; @@ -1488,6 +1489,7 @@ static struct stm32_gate_cfg per_gate_cfg[G_LAST] =3D= { K_GATE(G_STGENRO, RCC_APB4ENSETR, 20, 0), K_MGATE(G_USBPHY, RCC_APB4ENSETR, 16, 0), K_GATE(G_IWDG2, RCC_APB4ENSETR, 15, 0), + K_GATE(G_DDRPERFM, RCC_APB4ENSETR, 8, 0), K_MGATE(G_DSI, RCC_APB4ENSETR, 4, 0), K_MGATE(G_LTDC, RCC_APB4ENSETR, 0, 0), =20 @@ -1899,6 +1901,7 @@ static const struct clock_config stm32mp1_clock_cfg[]= =3D { PCLK(CRC1, "crc1", "ck_axi", 0, G_CRC1), PCLK(USBH, "usbh", "ck_axi", 0, G_USBH), PCLK(ETHSTP, "ethstp", "ck_axi", 0, G_ETHSTP), + PCLK(DDRPERFM, "ddrperfm", "pclk4", 0, G_DDRPERFM), =20 /* Kernel clocks */ KCLK(SDMMC1_K, "sdmmc1_k", sdmmc12_src, 0, G_SDMMC1, M_SDMMC12), --=20 2.7.4