From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2827DC004C9 for ; Wed, 8 May 2019 02:56:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ED39D21019 for ; Wed, 8 May 2019 02:56:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727018AbfEHC4z (ORCPT ); Tue, 7 May 2019 22:56:55 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:16116 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726670AbfEHC4y (ORCPT ); Tue, 7 May 2019 22:56:54 -0400 X-UUID: 32694377cbc74a0cb64b2150d0736679-20190508 X-UUID: 32694377cbc74a0cb64b2150d0736679-20190508 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1513612528; Wed, 08 May 2019 10:56:42 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by MTKMBS33N1.mediatek.inc (172.27.4.75) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 8 May 2019 10:56:40 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 8 May 2019 10:56:40 +0800 Message-ID: <1557284200.31731.8.camel@mtksdaap41> Subject: Re: [v2 3/5] drm/mediatek: add dsi reg commit control From: CK Hu To: Jitao Shi CC: Rob Herring , Pawel Moll , "Mark Rutland" , Ian Campbell , Kumar Gala , , David Airlie , "Matthias Brugger" , Thierry Reding , "Ajay Kumar" , Inki Dae , "Rahul Sharma" , Sean Paul , Vincent Palatin , Andy Yan , Philipp Zabel , "Russell King" , , , , , , , Sascha Hauer , , , , , Date: Wed, 8 May 2019 10:56:40 +0800 In-Reply-To: <20190416060501.76276-4-jitao.shi@mediatek.com> References: <20190416060501.76276-1-jitao.shi@mediatek.com> <20190416060501.76276-4-jitao.shi@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Jitao: On Tue, 2019-04-16 at 14:04 +0800, Jitao Shi wrote: > New DSI IP has shadow register and working reg. The register > values are writen to shadow register. And then trigger with > commit reg, the register values will be moved working register. This patch looks good, but the message is not complete. The message make us believe you use shadow register to work, but actually, shadow register is default turn on in new DSI IP and you want to turn off it. Regards, CK > > Signed-off-by: Jitao Shi > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c > index 573e6bec6d36..be42405a0a78 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -131,6 +131,10 @@ > #define VM_CMD_EN BIT(0) > #define TS_VFP_EN BIT(5) > > +#define DSI_SHADOW_DEBUG 0x190U > +#define FORCE_COMMIT BIT(0) > +#define BYPASS_SHADOW BIT(1) > + > #define CONFIG (0xff << 0) > #define SHORT_PACKET 0 > #define LONG_PACKET 2 > @@ -157,6 +161,7 @@ struct phy; > > struct mtk_dsi_driver_data { > const u32 reg_cmdq_off; > + bool has_shadow_ctl; > }; > > struct mtk_dsi { > @@ -594,6 +599,11 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > } > > mtk_dsi_enable(dsi); > + > + if (dsi->driver_data->has_shadow_ctl) > + writel(FORCE_COMMIT | BYPASS_SHADOW, > + dsi->regs + DSI_SHADOW_DEBUG); > + > mtk_dsi_reset_engine(dsi); > mtk_dsi_phy_timconfig(dsi); >