From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=3.0 tests=DATE_IN_PAST_06_12, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C058C04A6B for ; Wed, 8 May 2019 17:04:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 495C821726 for ; Wed, 8 May 2019 17:04:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729131AbfEHREA (ORCPT ); Wed, 8 May 2019 13:04:00 -0400 Received: from mga03.intel.com ([134.134.136.65]:5319 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728973AbfEHRDF (ORCPT ); Wed, 8 May 2019 13:03:05 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 May 2019 10:03:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,446,1549958400"; d="scan'208";a="169697579" Received: from chang-linux-3.sc.intel.com ([172.25.66.171]) by fmsmga002.fm.intel.com with ESMTP; 08 May 2019 10:03:03 -0700 From: "Chang S. Bae" To: Andy Lutomirski , Thomas Gleixner , Ingo Molnar , "H . Peter Anvin" , Andi Kleen Cc: Ravi Shankar , "Chang S . Bae" , LKML , Dave Hansen Subject: [PATCH v7 10/18] x86/entry/64: Switch CR3 before SWAPGS on the paranoid entry Date: Wed, 8 May 2019 03:02:25 -0700 Message-Id: <1557309753-24073-11-git-send-email-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557309753-24073-1-git-send-email-chang.seok.bae@intel.com> References: <1557309753-24073-1-git-send-email-chang.seok.bae@intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When FSGSBASE is enabled, GSBASE handling on the paranoid entry will need to retrieve the kernel GSBASE. Thus, the kernel page table should be in. As a preparation, the CR3 switching is moved to happen at first, before the SWAPGS. Current GSBASE switching mechanism is possible without the kernel page table in. No functional change is expected. Signed-off-by: Chang S. Bae Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Andy Lutomirski Cc: H. Peter Anvin Cc: Dave Hansen Cc: Andi Kleen --- arch/x86/entry/entry_64.S | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 568a491..034d8f8 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -1160,18 +1160,6 @@ ENTRY(paranoid_entry) PUSH_AND_CLEAR_REGS save_ret=1 ENCODE_FRAME_POINTER 8 - movl $1, %ebx - /* - * The kernel-enforced convention is a negative GSBASE indicates - * a kernel value. - */ - READ_MSR_GSBASE save_reg=%edx - testl %edx, %edx /* Negative -> in kernel */ - js 1f - SWAPGS - xorl %ebx, %ebx - -1: /* * Always stash CR3 in %r14. This value will be restored, * verbatim, at exit. Needed if paranoid_entry interrupted @@ -1181,9 +1169,26 @@ ENTRY(paranoid_entry) * This is also why CS (stashed in the "iret frame" by the * hardware at entry) can not be used: this may be a return * to kernel code, but with a user CR3 value. + * + * This PTI macro doesn't depend on kernel GSBASE and, with + * FSGSBASE, the GSBASE handling requires the kernel page + * tables switched in. So, do it early here. */ SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 + movl $1, %ebx + /* + * The kernel-enforced convention is a negative GSBASE indicates + * a kernel value. + */ + READ_MSR_GSBASE save_reg=%edx + testl %edx, %edx /* Negative -> in kernel */ + jns .Lparanoid_entry_swapgs + ret + +.Lparanoid_entry_swapgs: + SWAPGS + xorl %ebx, %ebx ret END(paranoid_entry) -- 2.7.4