From: Philipp Zabel <p.zabel@pengutronix.de>
To: Paul Kocialkowski <paul.kocialkowski@bootlin.com>,
Nicolas Dufresne <nicolas@ndufresne.ca>,
Hans Verkuil <hans.verkuil@cisco.com>,
Sakari Ailus <sakari.ailus@linux.intel.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Maxime Ripard <maxime.ripard@bootlin.com>,
linux-kernel@vger.kernel.org, linux-media@vger.kernel.org,
Linus Torvalds <torvalds@linux-foundation.org>,
Thierry Reding <thierry.reding@gmail.com>,
Tiffany Lin <tiffany.lin@mediatek.com>,
Andrew-CT Chen <andrew-ct.chen@mediatek.com>
Subject: Re: Hardware-accelerated video decoders used through a firmware instead of hardware registers
Date: Mon, 13 May 2019 15:47:37 +0200 [thread overview]
Message-ID: <1557755257.4442.8.camel@pengutronix.de> (raw)
In-Reply-To: <bfe1680249569241227ab90d5736b228de7b10f9.camel@bootlin.com>
Hi,
On Sun, 2019-05-12 at 18:32 +0200, Paul Kocialkowski wrote:
[...]
> I would be curious to know what the situation is on the i.MX6 coda
> block, which also seems pretty obscure.
FWIW, I had started collecting things I learned about the BIT processor
in the CODA IP cores, mostly by looking at the firmware files
distributed by Freescale/NXP: https://github.com/pH5/coda-bits
It is a somewhat strange custom 16-bit DSP architecture. There is a
rudimentary start for a disassembler in there as well, but large parts
of the instruction set are still completely unknown, and I have no idea
how the address generator / DMA units or bitstream accelerators work.
I would be delighted if somebody would like to pick up analyzing the BIT
processor ISA further. I think it could be fruitful to start
systematically throwing instructions at it and see what happens, to
learn more. I haven't had much motivation to play with this, recently.
About the internal connections and available accelerator units, there is
a block diagram in the i.MX53 TRM, but I am not aware of any register
level description for any of these.
regards
Philipp
prev parent reply other threads:[~2019-05-13 13:47 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-12 11:35 Hardware-accelerated video decoders used through a firmware instead of hardware registers Paul Kocialkowski
2019-05-12 14:17 ` Nicolas Dufresne
2019-05-12 16:32 ` Paul Kocialkowski
2019-05-12 20:11 ` Nicolas Dufresne
2019-05-13 13:47 ` Philipp Zabel [this message]
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