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From: Wu Hao <hao.wu@intel.com>
To: atull@kernel.org, mdf@kernel.org, linux-fpga@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: linux-api@vger.kernel.org, Wu Hao <hao.wu@intel.com>
Subject: [PATCH v3 01/16] fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address.
Date: Mon, 27 May 2019 13:22:11 +0800	[thread overview]
Message-ID: <1558934546-12171-2-git-send-email-hao.wu@intel.com> (raw)
In-Reply-To: <1558934546-12171-1-git-send-email-hao.wu@intel.com>

FME_PR_INTFC_ID is used as compat_id for fpga manager and region,
but high 64 bits and low 64 bits of the compat_id are swapped by
mistake. This patch fixes this problem by fixing register address.

Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
---
 drivers/fpga/dfl-fme-mgr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl-fme-mgr.c
index 76f3770..b3f7eee 100644
--- a/drivers/fpga/dfl-fme-mgr.c
+++ b/drivers/fpga/dfl-fme-mgr.c
@@ -30,8 +30,8 @@
 #define FME_PR_STS		0x10
 #define FME_PR_DATA		0x18
 #define FME_PR_ERR		0x20
-#define FME_PR_INTFC_ID_H	0xA8
-#define FME_PR_INTFC_ID_L	0xB0
+#define FME_PR_INTFC_ID_L	0xA8
+#define FME_PR_INTFC_ID_H	0xB0
 
 /* FME PR Control Register Bitfield */
 #define FME_PR_CTRL_PR_RST	BIT_ULL(0)  /* Reset PR engine */
-- 
1.8.3.1


  reply	other threads:[~2019-05-27  5:39 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-27  5:22 [PATCH v3 00/16] add new features for FPGA DFL drivers Wu Hao
2019-05-27  5:22 ` Wu Hao [this message]
2019-05-27  5:22 ` [PATCH v3 02/16] fpga: dfl: fme: remove copy_to_user() in ioctl for PR Wu Hao
2019-05-27  5:22 ` [PATCH v3 03/16] fpga: dfl: fme: align PR buffer size per PR datawidth Wu Hao
2019-05-27  5:22 ` [PATCH v3 04/16] fpga: dfl: fme: support 512bit data width PR Wu Hao
2019-05-27  5:22 ` [PATCH v3 05/16] Documentation: fpga: dfl: add descriptions for virtualization and new interfaces Wu Hao
2019-05-27  5:22 ` [PATCH v3 06/16] fpga: dfl: fme: add DFL_FPGA_FME_PORT_RELEASE/ASSIGN ioctl support Wu Hao
2019-05-27  5:22 ` [PATCH v3 07/16] fpga: dfl: pci: enable SRIOV support Wu Hao
2019-05-27  5:22 ` [PATCH v3 08/16] fpga: dfl: afu: add AFU state related sysfs interfaces Wu Hao
2019-05-27  5:22 ` [PATCH v3 09/16] fpga: dfl: afu: add userclock " Wu Hao
2019-05-27  5:22 ` [PATCH v3 10/16] fpga: dfl: add id_table for dfl private feature driver Wu Hao
2019-05-27  5:22 ` [PATCH v3 11/16] fpga: dfl: afu: export __port_enable/disable function Wu Hao
2019-05-27  5:22 ` [PATCH v3 12/16] fpga: dfl: afu: add error reporting support Wu Hao
2019-05-27  5:22 ` [PATCH v3 13/16] fpga: dfl: afu: add STP (SignalTap) support Wu Hao
2019-05-27  5:22 ` [PATCH v3 14/16] fpga: dfl: fme: add capability sysfs interfaces Wu Hao
2019-05-27  5:22 ` [PATCH v3 15/16] fpga: dfl: fme: add global error reporting support Wu Hao
2019-05-27  5:22 ` [PATCH v3 16/16] fpga: dfl: fme: add performance " Wu Hao
2019-05-30 18:53   ` Alan Tull
2019-06-01  8:04     ` Wu Hao
2019-05-30 19:03   ` Greg KH
2019-06-01  9:11     ` Wu Hao
2019-06-01  9:42       ` Greg KH
2019-06-04 14:47         ` Wu Hao

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