From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.4 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B424FC4321A for ; Fri, 28 Jun 2019 05:57:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8BE9C2086D for ; Fri, 28 Jun 2019 05:57:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727035AbfF1F5f (ORCPT ); Fri, 28 Jun 2019 01:57:35 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:2133 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726574AbfF1F5f (ORCPT ); Fri, 28 Jun 2019 01:57:35 -0400 X-UUID: 78ed0b10d4474fc08ffd9dfae75b74b0-20190628 X-UUID: 78ed0b10d4474fc08ffd9dfae75b74b0-20190628 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 885150733; Fri, 28 Jun 2019 13:57:16 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 28 Jun 2019 13:57:14 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 28 Jun 2019 13:57:14 +0800 Message-ID: <1561701434.18399.3.camel@mtksdaap41> Subject: Re: [v5 2/7] drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701 From: CK Hu To: Jitao Shi CC: Rob Herring , Pawel Moll , "Mark Rutland" , Ian Campbell , , David Airlie , Matthias Brugger , "Thierry Reding" , Ajay Kumar , "Inki Dae" , Rahul Sharma , "Sean Paul" , Vincent Palatin , "Andy Yan" , Philipp Zabel , Russell King , , , , , , , Sascha Hauer , , , , , Date: Fri, 28 Jun 2019 13:57:14 +0800 In-Reply-To: <20190627080116.40264-3-jitao.shi@mediatek.com> References: <20190627080116.40264-1-jitao.shi@mediatek.com> <20190627080116.40264-3-jitao.shi@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-SNTS-SMTP: EFC69EF3637C30387605FE58F2031FD41C3BF0457DDCD7D8088A30B41732E1EB2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Jitao: On Thu, 2019-06-27 at 16:01 +0800, Jitao Shi wrote: > Config the different CMDQ reg address in driver data. > > Signed-off-by: Jitao Shi > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 29 ++++++++++++++++++++++++----- > 1 file changed, 24 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c > index 595b3b047c7b..bd37d823c762 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -131,7 +131,6 @@ > #define VM_CMD_EN BIT(0) > #define TS_VFP_EN BIT(5) > > -#define DSI_CMDQ0 0x180 > #define CONFIG (0xff << 0) > #define SHORT_PACKET 0 > #define LONG_PACKET 2 > @@ -156,6 +155,10 @@ > > struct phy; > > +struct mtk_dsi_driver_data { > + const u32 reg_cmdq_off; > +}; > + > struct mtk_dsi { > struct mtk_ddp_comp ddp_comp; > struct device *dev; > @@ -182,6 +185,7 @@ struct mtk_dsi { > bool enabled; > u32 irq_data; > wait_queue_head_t irq_wait_queue; > + const struct mtk_dsi_driver_data *driver_data; > }; > > static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e) > @@ -934,6 +938,7 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg) > const char *tx_buf = msg->tx_buf; > u8 config, cmdq_size, cmdq_off, type = msg->type; > u32 reg_val, cmdq_mask, i; > + u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off; > > if (MTK_DSI_HOST_IS_READ(type)) > config = BTA; > @@ -953,9 +958,11 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg) > } > > for (i = 0; i < msg->tx_len; i++) > - writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i); > + mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U), > + (0xffUL << (((i + cmdq_off) & 3U) * 8U)), > + tx_buf[i] << (((i + cmdq_off) & 3U) * 8U)); If writeb() has the same problem in MT2701, I think we need a patch that just change writeb() to mtk_dsi_mask(), and then a patch to fix CMDQ reg address of MT8173. So break this patch into two patches. Regards, CK > > - mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val); > + mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val); > mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size); > } > > @@ -1099,6 +1106,8 @@ static int mtk_dsi_probe(struct platform_device *pdev) > if (ret) > goto err_unregister_host; > > + dsi->driver_data = of_device_get_match_data(dev); > + > dsi->engine_clk = devm_clk_get(dev, "engine"); > if (IS_ERR(dsi->engine_clk)) { > ret = PTR_ERR(dsi->engine_clk); > @@ -1192,9 +1201,19 @@ static int mtk_dsi_remove(struct platform_device *pdev) > return 0; > } > > +static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = { > + .reg_cmdq_off = 0x200, > +}; > + > +static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = { > + .reg_cmdq_off = 0x180, > +}; > + > static const struct of_device_id mtk_dsi_of_match[] = { > - { .compatible = "mediatek,mt2701-dsi" }, > - { .compatible = "mediatek,mt8173-dsi" }, > + { .compatible = "mediatek,mt2701-dsi", > + .data = &mt2701_dsi_driver_data }, > + { .compatible = "mediatek,mt8173-dsi", > + .data = &mt8173_dsi_driver_data }, > { }, > }; >