From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,UNWANTED_LANGUAGE_BODY,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B990EC06508 for ; Mon, 1 Jul 2019 01:29:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 976AC2145D for ; Mon, 1 Jul 2019 01:29:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727220AbfGAB3u (ORCPT ); Sun, 30 Jun 2019 21:29:50 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:57351 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727159AbfGAB3t (ORCPT ); Sun, 30 Jun 2019 21:29:49 -0400 X-UUID: d29bdff237594c7c81a1686025d435ae-20190701 X-UUID: d29bdff237594c7c81a1686025d435ae-20190701 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 872957804; Mon, 01 Jul 2019 09:29:35 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS33DR.mediatek.inc (172.27.6.106) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 1 Jul 2019 09:29:25 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 1 Jul 2019 09:29:23 +0800 Message-ID: <1561944562.17120.1.camel@mtksdaap41> Subject: Re: [v5 4/7] drm/mediatek: add frame size control From: CK Hu To: Jitao Shi CC: Rob Herring , Pawel Moll , "Mark Rutland" , Ian Campbell , , David Airlie , Matthias Brugger , "Thierry Reding" , Ajay Kumar , "Inki Dae" , Rahul Sharma , "Sean Paul" , Vincent Palatin , "Andy Yan" , Philipp Zabel , Russell King , , , , , , , Sascha Hauer , , , , , Date: Mon, 1 Jul 2019 09:29:22 +0800 In-Reply-To: <20190627080116.40264-5-jitao.shi@mediatek.com> References: <20190627080116.40264-1-jitao.shi@mediatek.com> <20190627080116.40264-5-jitao.shi@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-Product-Ver: SMEX-12.5.0.1684-8.5.1010-24732.000 X-TM-AS-Result: No-12.337600-8.000000-10 X-TMASE-MatchedRID: zGP2F0O7j/vmLzc6AOD8DfHkpkyUphL9xXRDKEyu2zF+SLLtNOiBhmmd 1p2wVSdNRw3fpQHgw3t0pmQclXiHl4UJf3YQjB6CiJwEp8weVXwxXH/dlhvLv2q646qiEnRz7yL x17DX9aet2gtuWr1Lmt52diAVzqN2Z/mERv8EXlX754IB1tyKcqg3Fm19nZrJ0u/U/L+rNlES99 dUV0LYkjvFiNq8G3M5EiVVgKqFXk5Nfs8n85Te8oMbH85DUZXyseWplitmp0j6C0ePs7A07RRAJ C2k3BZ6qjisAJ9xR93/FHz8N5NA/ciiN6rHv+xKGCY6L4Z1ACk= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--12.337600-8.000000 X-TMASE-Version: SMEX-12.5.0.1684-8.5.1010-24732.000 X-TM-SNTS-SMTP: A90BCEAADDCB8D640566EAD2CCD718AC8B8A63ED6C117C0EF66499DE0C7667252000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Jitao: On Thu, 2019-06-27 at 16:01 +0800, Jitao Shi wrote: > Our new DSI chip has frame size control. > So add the driver data to control for different chips. > > Signed-off-by: Jitao Shi > Reviewed-by: CK Hu This version is different than previous version, so you should remove the reviewed-by tag. For this version, I still give you a Reviewed-by: CK Hu > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c > index 6b6550926db6..45e331055842 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -78,6 +78,7 @@ > #define DSI_VBP_NL 0x24 > #define DSI_VFP_NL 0x28 > #define DSI_VACT_NL 0x2C > +#define DSI_SIZE_CON 0x38 > #define DSI_HSA_WC 0x50 > #define DSI_HBP_WC 0x54 > #define DSI_HFP_WC 0x58 > @@ -162,6 +163,7 @@ struct phy; > struct mtk_dsi_driver_data { > const u32 reg_cmdq_off; > bool has_shadow_ctl; > + bool has_size_ctl; > }; > > struct mtk_dsi { > @@ -430,6 +432,10 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) > writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL); > writel(vm->vactive, dsi->regs + DSI_VACT_NL); > > + if (dsi->driver_data->has_size_ctl) > + writel(vm->vactive << 16 | vm->hactive, > + dsi->regs + DSI_SIZE_CON); > + > horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10); > > if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)