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Sun, 30 Jun 2019 22:29:56 -0700 Received: from [172.23.64.106] (helo=xhdvnc125.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1hhot2-0003Cf-4S; Sun, 30 Jun 2019 22:29:56 -0700 Received: by xhdvnc125.xilinx.com (Postfix, from userid 16987) id 47271121746; Mon, 1 Jul 2019 10:59:54 +0530 (IST) From: Manish Narani To: ulf.hansson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, heiko@sntech.de, michal.simek@xilinx.com, adrian.hunter@intel.com, christoph.muellner@theobroma-systems.com, philipp.tomsich@theobroma-systems.com, viresh.kumar@linaro.org, scott.branden@broadcom.com, ayaka@soulik.info, kernel@esmil.dk, tony.xie@rock-chips.com, rajan.vaja@xilinx.com, jolly.shah@xilinx.com, nava.manne@xilinx.com, mdf@kernel.org, manish.narani@xilinx.com, olof@lixom.net Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v2 06/11] mmc: sdhci-of-arasan: Add sampling clock for a phy to use Date: Mon, 1 Jul 2019 10:59:46 +0530 Message-Id: <1561958991-21935-7-git-send-email-manish.narani@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1561958991-21935-1-git-send-email-manish.narani@xilinx.com> References: <1561958991-21935-1-git-send-email-manish.narani@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(396003)(39860400002)(376002)(136003)(346002)(2980300002)(189003)(199004)(8676002)(446003)(2906002)(51416003)(72206003)(81166006)(81156014)(26005)(16586007)(48376002)(316002)(5660300002)(76176011)(36386004)(11346002)(336012)(36756003)(103686004)(50226002)(426003)(8936002)(52956003)(44832011)(2616005)(7416002)(106002)(476003)(14444005)(126002)(4326008)(47776003)(478600001)(6666004)(356004)(42186006)(6266002)(70206006)(305945005)(70586007)(50466002)(186003)(63266004)(486006)(921003)(42866002)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:CH2PR02MB6326;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; MIME-Version: 1.0 Content-Type: text/plain X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0cf47994-d542-47e9-92e6-08d6fde52d6d X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(4709080)(1401327)(2017052603328);SRVR:CH2PR02MB6326; X-MS-TrafficTypeDiagnostic: CH2PR02MB6326: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-Forefront-PRVS: 00851CA28B X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: mN2kIH1lJKbt9MFOHicH/hBDPBnlIa8L/EVttPdKrwSZ7Mqy0XRndC2tp8LLfTDIAoBTEUAhMg/RZevc/cKZj0aqVoifoibEI0SzdygTvhCtDZLjasLGk5eAsRFGLoImNMkDedQjz6Xvfwg7HxH+/nL4abgszofNc70I8wrO0mgeY1w/qhCMVY4wI9Ei/xiz3swAU0qxWMrEHG6XyBKj7Qsm/09y2ua2tcgh9AzA57sYCiNxix0cFjcLzOOe2ifBXoUMga+My1oFoYiFg4q3MaAuDGwJsZG5JDcsTQEDGoAG8+3eOwM1ev/+BDl+qkr6E+LlFR7ovBIwWQApIkKMd6WxIexRzFLSs11UyeZgwRAsY8Uf9IdXROyvWBg4AuZ/wr+w/9Tlvle/a942sFZaqG8gJbgBDBPHy8QqKpLBmt8= X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jul 2019 05:30:06.3261 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0cf47994-d542-47e9-92e6-08d6fde52d6d X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR02MB6326 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There are some operations like setting the clock delays may need to have two clocks, one for output path and one for input path. Adding input path clock for some phys to use. Signed-off-by: Manish Narani --- drivers/mmc/host/sdhci-of-arasan.c | 118 ++++++++++++++++++++++++++++++++++--- 1 file changed, 110 insertions(+), 8 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index c7586f5..9513813 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -75,10 +75,14 @@ struct sdhci_arasan_soc_ctl_map { * struct sdhci_arasan_clk_data * @sdcardclk_hw: Struct for the clock we might provide to a PHY. * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw. + * @sampleclk_hw: Struct for the clock we might provide to a PHY. + * @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw. */ struct sdhci_arasan_clk_data { struct clk_hw sdcardclk_hw; struct clk *sdcardclk; + struct clk_hw sampleclk_hw; + struct clk *sampleclk; }; /** @@ -527,6 +531,33 @@ static const struct clk_ops arasan_sdcardclk_ops = { }; /** + * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate + * + * Return the current actual rate of the sampling clock. This can be used + * to communicate with out PHY. + * + * @hw: Pointer to the hardware clock structure. + * @parent_rate The parent rate (should be rate of clk_xin). + * Returns the sample clock rate. + */ +static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) + +{ + struct sdhci_arasan_clk_data *clk_data = + container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw); + struct sdhci_arasan_data *sdhci_arasan = + container_of(clk_data, struct sdhci_arasan_data, clk_data); + struct sdhci_host *host = sdhci_arasan->host; + + return host->mmc->actual_clock; +} + +static const struct clk_ops arasan_sampleclk_ops = { + .recalc_rate = sdhci_arasan_sampleclk_recalc_rate, +}; + +/** * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier * * The corecfg_clockmultiplier is supposed to contain clock multiplier @@ -605,7 +636,7 @@ static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) } /** - * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use + * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use * * Some PHY devices need to know what the actual card clock is. In order for * them to find out, we'll provide a clock through the common clock framework @@ -624,9 +655,10 @@ static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) * @dev: Pointer to our struct device. * Returns 0 on success and error value on error */ -static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, - struct clk *clk_xin, - struct device *dev) +static int +sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan, + struct clk *clk_xin, + struct device *dev) { struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; struct device_node *np = dev->of_node; @@ -662,7 +694,7 @@ static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &clk_data->sdcardclk_hw); if (ret) { - dev_err(dev, "Failed to add clock provider\n"); + dev_err(dev, "Failed to add sdcard clock provider\n"); return ret; } @@ -676,10 +708,74 @@ static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, } /** + * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use + * + * Some PHY devices need to know what the actual card clock is. In order for + * them to find out, we'll provide a clock through the common clock framework + * for them to query. + * + * @sdhci_arasan: Our private data structure. + * @clk_xin: Pointer to the functional clock + * @dev: Pointer to our struct device. + * Returns 0 on success and error value on error + */ +static int +sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan, + struct clk *clk_xin, + struct device *dev) +{ + struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; + struct device_node *np = dev->of_node; + struct clk_init_data sampleclk_init; + const char *parent_clk_name; + int ret; + + /* Providing a clock to the PHY is optional; no error if missing */ + if (!of_find_property(np, "#clock-cells", NULL)) + return 0; + + ret = of_property_read_string_index(np, "clock-output-names", 1, + &sampleclk_init.name); + if (ret) { + dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); + return ret; + } + + parent_clk_name = __clk_get_name(clk_xin); + sampleclk_init.parent_names = &parent_clk_name; + sampleclk_init.num_parents = 1; + sampleclk_init.flags = CLK_GET_RATE_NOCACHE; + sampleclk_init.ops = &arasan_sampleclk_ops; + + clk_data->sampleclk_hw.init = &sampleclk_init; + ret = devm_clk_hw_register(dev, &clk_data->sampleclk_hw); + if (ret) { + dev_err(dev, "Failed to register SD clk_hw\n"); + return ret; + } + clk_data->sampleclk_hw.init = NULL; + + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, + &clk_data->sampleclk_hw); + if (ret) { + dev_err(dev, "Failed to add sample clock provider\n"); + return ret; + } + + clk_data->sampleclk = devm_clk_get(dev, "clk_sample"); + if (IS_ERR(clk_data->sampleclk)) { + dev_err(dev, "sampleclk clock not found.\n"); + ret = PTR_ERR(clk_data->sampleclk); + } + + return ret; +} + +/** * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk() * - * Should be called any time we're exiting and sdhci_arasan_register_sdclk() - * returned success. + * Should be called any time we're exiting and sdhci_arasan_register_sdcardclk() + * /sampleclk() returned success. * * @dev: Pointer to our struct device. */ @@ -817,10 +913,16 @@ static int sdhci_arasan_probe(struct platform_device *pdev) sdhci_arasan_update_baseclkfreq(host); - ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev); + ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, + &pdev->dev); if (ret) goto clk_disable_all; + ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin, + &pdev->dev); + if (ret) + goto unreg_clk; + ret = mmc_of_parse(host->mmc); if (ret) { if (ret != -EPROBE_DEFER) -- 2.1.1