From: Zhou Yanjie <email@example.com> To: firstname.lastname@example.org Cc: email@example.com, firstname.lastname@example.org, email@example.com, firstname.lastname@example.org, email@example.com, firstname.lastname@example.org, email@example.com Subject: [PATCH 3/6] dt-bindings: pinctrl: Add X1000 and X1000E bindings. Date: Sun, 14 Jul 2019 11:53:53 +0800 [thread overview] Message-ID: <firstname.lastname@example.org> (raw) In-Reply-To: <email@example.com> Add the pinctrl bindings for the X1000 Soc and the X1000E Soc from Ingenic. Signed-off-by: Zhou Yanjie <firstname.lastname@example.org> --- .../devicetree/bindings/pinctrl/ingenic,pinctrl.txt | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt index a80ff68..7e2ee46 100644 --- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt @@ -1,18 +1,18 @@ -Ingenic jz47xx pin controller +Ingenic XBurst pin controller Please refer to pinctrl-bindings.txt in this directory for details of the common pinctrl bindings used by client devices, including the meaning of the phrase "pin configuration node". -For the jz47xx SoCs, pin control is tightly bound with GPIO ports. All pins may +For the XBurst SoCs, pin control is tightly bound with GPIO ports. All pins may be used as GPIOs, multiplexed device functions are configured within the GPIO port configuration registers and it is typical to refer to pins using the naming scheme "PxN" where x is a character identifying the GPIO port with which the pin is associated and N is an integer from 0 to 31 identifying the pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and -PB31 is the last pin in GPIO port B. The jz4740 contains 4 GPIO ports, PA to -PD, for a total of 128 pins. The jz4760, the jz4770 and the jz4780 contains 6 -GPIO ports, PA to PF, for a total of 192 pins. +PB31 is the last pin in GPIO port B. The jz4740 and the x1000 contains 4 GPIO +ports, PA to PD, for a total of 128 pins. The jz4760, the jz4770 and the jz4780 +contains 6 GPIO ports, PA to PF, for a total of 192 pins. Required properties: @@ -25,6 +25,8 @@ Required properties: - "ingenic,jz4760b-pinctrl" - "ingenic,jz4770-pinctrl" - "ingenic,jz4780-pinctrl" + - "ingenic,x1000-pinctrl" + - "ingenic,x1000e-pinctrl" - reg: Address range of the pinctrl registers. @@ -36,6 +38,7 @@ Required properties for sub-nodes (GPIO chips): - "ingenic,jz4760-gpio" - "ingenic,jz4770-gpio" - "ingenic,jz4780-gpio" + - "ingenic,x1000-gpio" - reg: The GPIO bank number. - interrupt-controller: Marks the device node as an interrupt controller. - interrupts: Interrupt specifier for the controllers interrupt. -- 2.7.4
next prev parent reply other threads:[~2019-07-14 7:11 UTC|newest] Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-07-14 3:53 Ingenic pinctrl patchs Zhou Yanjie 2019-07-14 3:53 ` [PATCH 1/6] dt-bindings: pinctrl: Add JZ4760 and JZ4760B bindings Zhou Yanjie 2019-07-14 3:53 ` [PATCH 2/6] pinctrl: Ingenic: Add pinctrl driver for JZ4760 and JZ4760B Zhou Yanjie 2019-07-14 3:53 ` Zhou Yanjie [this message] 2019-07-14 3:53 ` [PATCH 4/6] pinctrl: Ingenic: Add pinctrl driver for X1000 and X1000E Zhou Yanjie 2019-07-14 3:53 ` [PATCH 5/6] dt-bindings: pinctrl: Add X1500 bindings Zhou Yanjie 2019-07-14 3:53 ` [PATCH 6/6] pinctrl: Ingenic: Add pinctrl driver for X1500 Zhou Yanjie 2019-07-29 21:42 ` Ingenic pinctrl patchs Linus Walleij
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