From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55FEDC76186 for ; Wed, 17 Jul 2019 05:35:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 34BA020818 for ; Wed, 17 Jul 2019 05:35:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726882AbfGQFfn (ORCPT ); Wed, 17 Jul 2019 01:35:43 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:6337 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725856AbfGQFfm (ORCPT ); Wed, 17 Jul 2019 01:35:42 -0400 X-UUID: 53bbb227bb8d453680d5355fdfb934ef-20190717 X-UUID: 53bbb227bb8d453680d5355fdfb934ef-20190717 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 693698133; Wed, 17 Jul 2019 13:35:38 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 17 Jul 2019 13:35:35 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 17 Jul 2019 13:35:36 +0800 Message-ID: <1563341736.29169.15.camel@mtksdaap41> Subject: Re: [PATCH v4, 12/33] drm/mediatek: split DISP_REG_CONFIG_DSI_SEL setting into another use case From: CK Hu To: CC: Philipp Zabel , Rob Herring , Matthias Brugger , "David Airlie" , Daniel Vetter , Mark Rutland , , , , , Date: Wed, 17 Jul 2019 13:35:36 +0800 In-Reply-To: <1562625253-29254-13-git-send-email-yongqiang.niu@mediatek.com> References: <1562625253-29254-1-git-send-email-yongqiang.niu@mediatek.com> <1562625253-29254-13-git-send-email-yongqiang.niu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-SNTS-SMTP: F9D2280166EF5AA1468B07A64B20AE04654710B0E0A7273E89A21F547161FA5F2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Yongqiang: On Tue, 2019-07-09 at 06:33 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu > > Here is two modifition in this patch: > 1.bls->dpi0 and rdma1->dsi are differen usecase, > Split DISP_REG_CONFIG_DSI_SEL setting into anther usecase > 2.remove DISP_REG_CONFIG_DPI_SEL setting, DPI_SEL_IN_BLS is 0 and > this is same with hardware defautl setting, > You move 2 register setting out of the path from BLS to DPI0, does this path still work? Please make sure that all modification could work on all supported SoC. Regards, CK > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index d015c1a..47b3e35 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -400,10 +400,9 @@ static void mtk_ddp_sout_sel(void __iomem *config_regs, > } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > config_regs + DISP_REG_CONFIG_OUT_SEL); > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > writel_relaxed(DSI_SEL_IN_RDMA, > config_regs + DISP_REG_CONFIG_DSI_SEL); > - writel_relaxed(DPI_SEL_IN_BLS, > - config_regs + DISP_REG_CONFIG_DPI_SEL); > } > } >