From: Zhou Yanjie <zhouyanjie@zoho.com>
To: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, ralf@linux-mips.org,
paul@crapouillou.net, paul.burton@mips.com, jhogan@kernel.org,
malat@debian.org, gregkh@linuxfoundation.org, tglx@linutronix.de,
allison@lohutok.net, syq@debian.org, chenhc@lemote.com,
jiaxun.yang@flygoat.com
Subject: [PATCH 1/2 v3] MIPS: Ingenic: Fix bugs when detecting X1000's L2 cache.
Date: Thu, 1 Aug 2019 20:16:30 +0800 [thread overview]
Message-ID: <1564661791-47731-2-git-send-email-zhouyanjie@zoho.com> (raw)
In-Reply-To: <1564661791-47731-1-git-send-email-zhouyanjie@zoho.com>
1.fix bugs when detecting L2 cache sets value.
2.fix bugs when detecting L2 cache ways value.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
arch/mips/mm/sc-mips.c | 27 ++++++++++++++++++++-------
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 9385ddb..dbdbfe5 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -221,13 +221,26 @@ static inline int __init mips_sc_probe(void)
else
return 0;
- /*
- * According to config2 it would be 5-ways, but that is contradicted
- * by all documentation.
- */
- if (current_cpu_type() == CPU_XBURST &&
- mips_machtype == MACH_INGENIC_JZ4770)
- c->scache.ways = 4;
+ if (current_cpu_type() == CPU_XBURST) {
+ switch (mips_machtype) {
+ /*
+ * According to config2 it would be 5-ways, but that is
+ * contradicted by all documentation.
+ */
+ case MACH_INGENIC_JZ4770:
+ c->scache.ways = 4;
+ break;
+
+ /*
+ * According to config2 it would be 5-ways and 512-sets,
+ * but that is contradicted by all documentation.
+ */
+ case MACH_INGENIC_X1000:
+ c->scache.sets = 256;
+ c->scache.ways = 4;
+ break;
+ }
+ }
c->scache.waysize = c->scache.sets * c->scache.linesz;
c->scache.waybit = __ffs(c->scache.waysize);
--
2.7.4
next prev parent reply other threads:[~2019-08-01 12:18 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-30 14:55 MIPS: Ingenic: Fix bugs when detecting X1000's parameters Zhou Yanjie
2019-07-30 14:55 ` [PATCH] " Zhou Yanjie
2019-07-30 18:02 ` Paul Cercueil
2019-07-31 4:32 ` Zhou Yanjie
2019-07-31 4:39 ` MIPS: Ingenic: Fix bugs when detecting X1000's parameters v2 Zhou Yanjie
2019-07-31 4:39 ` [PATCH v2] MIPS: Ingenic: Fix bugs when detecting X1000's parameters Zhou Yanjie
2019-07-31 20:34 ` Paul Burton
2019-08-01 10:55 ` Zhou Yanjie
2019-08-01 12:16 ` MIPS: Ingenic: Fix bugs when detecting X1000's parameters v3 Zhou Yanjie
2019-08-01 12:16 ` Zhou Yanjie [this message]
2019-08-01 12:16 ` [PATCH 2/2 v3] MIPS: Ingenic: Fix bugs when calculate bogomips/lpj Zhou Yanjie
2019-08-02 1:26 ` Paul Cercueil
2019-08-02 8:13 ` Zhou Yanjie
2019-08-02 17:32 ` Paul Burton
2019-08-02 8:27 ` MIPS: Ingenic: Fix bugs when detecting X1000's parameters v4 Zhou Yanjie
2019-08-02 8:27 ` [PATCH 1/2 v4] MIPS: Ingenic: Fix bugs when detecting X1000's L2 cache Zhou Yanjie
2019-08-06 23:02 ` Paul Burton
2019-08-02 8:27 ` [PATCH 2/2 v4] MIPS: Ingenic: Disable broken BTB lookup optimization Zhou Yanjie
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