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From: Paul Cercueil <paul@crapouillou.net>
To: Zhou Yanjie <zhouyanjie@zoho.com>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
	ralf@linux-mips.org, paul.burton@mips.com, jhogan@kernel.org,
	malat@debian.org, gregkh@linuxfoundation.org, tglx@linutronix.de,
	allison@lohutok.net, syq@debian.org, chenhc@lemote.com,
	jiaxun.yang@flygoat.com
Subject: Re: [PATCH 2/2 v3] MIPS: Ingenic: Fix bugs when calculate bogomips/lpj.
Date: Thu, 01 Aug 2019 21:26:09 -0400	[thread overview]
Message-ID: <1564709169.1988.0@crapouillou.net> (raw)
In-Reply-To: <1564661791-47731-3-git-send-email-zhouyanjie@zoho.com>

Hi Zhou,



Le jeu. 1 août 2019 à 8:16, Zhou Yanjie <zhouyanjie@zoho.com> a 
écrit :
> Enable BTB lookups for short loops to fix bugs when calculate
> bogomips and loops_per_jiffy.

The commit description and the code comment below seem to say two
different things. Are we enabling the BTB lookup optimization, or not?

Also, maybe change the commit title to something more meaningful, e.g.
"MIPS: ingenic: Disable broken BTB lookup optimization" or similar.


> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
> ---
>  arch/mips/include/asm/mipsregs.h | 4 ++++
>  arch/mips/kernel/cpu-probe.c     | 7 +++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/arch/mips/include/asm/mipsregs.h 
> b/arch/mips/include/asm/mipsregs.h
> index 1e6966e..bdbdc19 100644
> --- a/arch/mips/include/asm/mipsregs.h
> +++ b/arch/mips/include/asm/mipsregs.h
> @@ -689,6 +689,9 @@
>  #define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)
>  #define MIPS_CONF7_AR		(_ULCAST_(1) << 16)
> 
> +/* Ingenic Config7 bits */
> +#define MIPS_CONF7_BTB_LOOP_EN	(_ULCAST_(1) << 4)
> +
>  /* Config7 Bits specific to MIPS Technologies. */
> 
>  /* Performance counters implemented Per TC */
> @@ -2813,6 +2816,7 @@ __BUILD_SET_C0(status)
>  __BUILD_SET_C0(cause)
>  __BUILD_SET_C0(config)
>  __BUILD_SET_C0(config5)
> +__BUILD_SET_C0(config7)
>  __BUILD_SET_C0(intcontrol)
>  __BUILD_SET_C0(intctl)
>  __BUILD_SET_C0(srsmap)
> diff --git a/arch/mips/kernel/cpu-probe.c 
> b/arch/mips/kernel/cpu-probe.c
> index eb527a1..2bdd3e1 100644
> --- a/arch/mips/kernel/cpu-probe.c
> +++ b/arch/mips/kernel/cpu-probe.c
> @@ -1964,6 +1964,13 @@ static inline void cpu_probe_ingenic(struct 
> cpuinfo_mips *c, unsigned int cpu)
>  		c->cputype = CPU_XBURST;
>  		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
>  		__cpu_name[cpu] = "Ingenic XBurst";
> +		/*
> +		 * The XBurst core by default attempts to avoid branch target
> +		 * buffer lookups by detecting & special casing loops. This
> +		 * feature will cause BogoMIPS and lpj calculate in error.
> +		 * Set cp0 config7 bit 4 to disable this feature.
> +		 */
> +		set_c0_config7(MIPS_CONF7_BTB_LOOP_EN);

Shouldn't it be MIPS_CONF7_BTB_LOOP_DIS then?
Since the feature is disabled when the bit is set.


>  		break;
>  	default:
>  		panic("Unknown Ingenic Processor ID!");
> --
> 2.7.4
> 
> 



  reply	other threads:[~2019-08-02  1:26 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-30 14:55 MIPS: Ingenic: Fix bugs when detecting X1000's parameters Zhou Yanjie
2019-07-30 14:55 ` [PATCH] " Zhou Yanjie
2019-07-30 18:02   ` Paul Cercueil
2019-07-31  4:32     ` Zhou Yanjie
2019-07-31  4:39 ` MIPS: Ingenic: Fix bugs when detecting X1000's parameters v2 Zhou Yanjie
2019-07-31  4:39   ` [PATCH v2] MIPS: Ingenic: Fix bugs when detecting X1000's parameters Zhou Yanjie
2019-07-31 20:34     ` Paul Burton
2019-08-01 10:55       ` Zhou Yanjie
2019-08-01 12:16 ` MIPS: Ingenic: Fix bugs when detecting X1000's parameters v3 Zhou Yanjie
2019-08-01 12:16   ` [PATCH 1/2 v3] MIPS: Ingenic: Fix bugs when detecting X1000's L2 cache Zhou Yanjie
2019-08-01 12:16   ` [PATCH 2/2 v3] MIPS: Ingenic: Fix bugs when calculate bogomips/lpj Zhou Yanjie
2019-08-02  1:26     ` Paul Cercueil [this message]
2019-08-02  8:13       ` Zhou Yanjie
2019-08-02 17:32       ` Paul Burton
2019-08-02  8:27 ` MIPS: Ingenic: Fix bugs when detecting X1000's parameters v4 Zhou Yanjie
2019-08-02  8:27   ` [PATCH 1/2 v4] MIPS: Ingenic: Fix bugs when detecting X1000's L2 cache Zhou Yanjie
2019-08-06 23:02     ` Paul Burton
2019-08-02  8:27   ` [PATCH 2/2 v4] MIPS: Ingenic: Disable broken BTB lookup optimization Zhou Yanjie

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