From: Zhou Wang <wangzhou1@hisilicon.com>
To: <herbert@gondor.apana.org.au>, <davem@davemloft.net>,
<linux-crypto@vger.kernel.org>
Cc: <linuxarm@huawei.com>, <linux-kernel@vger.kernel.org>,
Zhou Wang <wangzhou1@hisilicon.com>
Subject: [PATCH v3 5/7] Documentation: Add debugfs doc for hisi_zip
Date: Fri, 2 Aug 2019 15:57:54 +0800 [thread overview]
Message-ID: <1564732676-35987-6-git-send-email-wangzhou1@hisilicon.com> (raw)
In-Reply-To: <1564732676-35987-1-git-send-email-wangzhou1@hisilicon.com>
Add debugfs descriptions for HiSilicon ZIP and QM driver.
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Documentation/ABI/testing/debugfs-hisi-zip | 50 ++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/ABI/testing/debugfs-hisi-zip
diff --git a/Documentation/ABI/testing/debugfs-hisi-zip b/Documentation/ABI/testing/debugfs-hisi-zip
new file mode 100644
index 0000000..a7c63e6
--- /dev/null
+++ b/Documentation/ABI/testing/debugfs-hisi-zip
@@ -0,0 +1,50 @@
+What: /sys/kernel/debug/hisi_zip/<bdf>/comp_core[01]/regs
+Date: Nov 2018
+Contact: linux-crypto@vger.kernel.org
+Description: Dump of compression cores related debug registers.
+ Only available for PF.
+
+What: /sys/kernel/debug/hisi_zip/<bdf>/decomp_core[0-5]/regs
+Date: Nov 2018
+Contact: linux-crypto@vger.kernel.org
+Description: Dump of decompression cores related debug registers.
+ Only available for PF.
+
+What: /sys/kernel/debug/hisi_zip/<bdf>/clear_enable
+Date: Nov 2018
+Contact: linux-crypto@vger.kernel.org
+Description: Compression/decompression core debug registers read clear
+ control. 1 means enable register read clear, otherwise 0.
+ Writing to this file has no functional effect, only enable or
+ disable counters clear after reading of these registers.
+ Only available for PF.
+
+What: /sys/kernel/debug/hisi_zip/<bdf>/current_qm
+Date: Nov 2018
+Contact: linux-crypto@vger.kernel.org
+Description: One ZIP controller has one PF and multiple VFs, each function
+ has a QM. Select the QM which below qm refers to.
+ Only available for PF.
+
+What: /sys/kernel/debug/hisi_zip/<bdf>/qm/qm_regs
+Date: Nov 2018
+Contact: linux-crypto@vger.kernel.org
+Description: Dump of QM related debug registers.
+ Available for PF and VF in host. VF in guest currently only
+ has one debug register.
+
+What: /sys/kernel/debug/hisi_zip/<bdf>/qm/current_q
+Date: Nov 2018
+Contact: linux-crypto@vger.kernel.org
+Description: One QM may contain multiple queues. Select specific queue to
+ show its debug registers in above qm_regs.
+ Only available for PF.
+
+What: /sys/kernel/debug/hisi_zip/<bdf>/qm/clear_enable
+Date: Nov 2018
+Contact: linux-crypto@vger.kernel.org
+Description: QM debug registers(qm_regs) read clear control. 1 means enable
+ register read clear, otherwise 0.
+ Writing to this file has no functional effect, only enable or
+ disable counters clear after reading of these registers.
+ Only available for PF.
--
2.8.1
next prev parent reply other threads:[~2019-08-02 8:16 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-02 7:57 [PATCH v3 0/7] crypto: hisilicon: Add HiSilicon QM and ZIP controller driver Zhou Wang
2019-08-02 7:57 ` [PATCH v3 1/7] crypto: hisilicon - add queue management driver for HiSilicon QM module Zhou Wang
2019-08-02 7:57 ` [PATCH v3 2/7] crypto: hisilicon - add hardware SGL support Zhou Wang
2019-08-02 7:57 ` [PATCH v3 3/7] crypto: hisilicon - add HiSilicon ZIP accelerator support Zhou Wang
2019-08-02 7:57 ` [PATCH v3 4/7] crypto: hisilicon - add SRIOV support for ZIP Zhou Wang
2019-08-02 7:57 ` Zhou Wang [this message]
2019-08-02 7:57 ` [PATCH v3 6/7] crypto: hisilicon - add debugfs for ZIP and QM Zhou Wang
2019-08-02 7:57 ` [PATCH v3 7/7] MAINTAINERS: add maintainer for HiSilicon QM and ZIP controller driver Zhou Wang
2019-08-08 12:41 ` [PATCH v3 0/7] crypto: hisilicon: Add " Zhou Wang
2019-08-09 6:19 ` Herbert Xu
2019-08-09 7:14 ` Zhou Wang
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