From: Krishna Yarlagadda <kyarlagadda@nvidia.com>
To: <gregkh@linuxfoundation.org>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <ldewangan@nvidia.com>, <jslaby@suse.com>
Cc: <linux-serial@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Krishna Yarlagadda <kyarlagadda@nvidia.com>,
Shardar Shariff Md <smohammed@nvidia.com>
Subject: [PATCH V2 07/12] serial: tegra: set maximum num of uart ports to 8
Date: Wed, 4 Sep 2019 10:13:02 +0530 [thread overview]
Message-ID: <1567572187-29820-8-git-send-email-kyarlagadda@nvidia.com> (raw)
In-Reply-To: <1567572187-29820-1-git-send-email-kyarlagadda@nvidia.com>
Set maximum number of UART ports to 8 as older chips have 5 ports and
Tergra186 and later chips will have 8 ports. Add this info to chip
data. Read device tree compatible of this driver and register uart
driver with max ports of matching chip data.
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
---
drivers/tty/serial/serial-tegra.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c
index 69af621..8422516 100644
--- a/drivers/tty/serial/serial-tegra.c
+++ b/drivers/tty/serial/serial-tegra.c
@@ -62,7 +62,7 @@
#define TEGRA_UART_TX_TRIG_4B 0x20
#define TEGRA_UART_TX_TRIG_1B 0x30
-#define TEGRA_UART_MAXIMUM 5
+#define TEGRA_UART_MAXIMUM 8
/* Default UART setting when started: 115200 no parity, stop, 8 data bits */
#define TEGRA_UART_DEFAULT_BAUD 115200
@@ -87,6 +87,7 @@ struct tegra_uart_chip_data {
bool allow_txfifo_reset_fifo_mode;
bool support_clk_src_div;
bool fifo_mode_enable_status;
+ int uart_max_port;
};
struct tegra_uart_port {
@@ -1322,6 +1323,7 @@ static struct tegra_uart_chip_data tegra20_uart_chip_data = {
.allow_txfifo_reset_fifo_mode = true,
.support_clk_src_div = false,
.fifo_mode_enable_status = false,
+ .uart_max_port = 5,
};
static struct tegra_uart_chip_data tegra30_uart_chip_data = {
@@ -1329,6 +1331,7 @@ static struct tegra_uart_chip_data tegra30_uart_chip_data = {
.allow_txfifo_reset_fifo_mode = false,
.support_clk_src_div = true,
.fifo_mode_enable_status = false,
+ .uart_max_port = 5,
};
static struct tegra_uart_chip_data tegra186_uart_chip_data = {
@@ -1336,6 +1339,7 @@ static struct tegra_uart_chip_data tegra186_uart_chip_data = {
.allow_txfifo_reset_fifo_mode = false,
.support_clk_src_div = true,
.fifo_mode_enable_status = true,
+ .uart_max_port = 8,
};
static const struct of_device_id tegra_uart_of_match[] = {
@@ -1468,11 +1472,22 @@ static struct platform_driver tegra_uart_platform_driver = {
static int __init tegra_uart_init(void)
{
int ret;
+ struct device_node *node;
+ const struct of_device_id *match = NULL;
+ const struct tegra_uart_chip_data *cdata = NULL;
+
+ node = of_find_matching_node(NULL, tegra_uart_of_match);
+ if (node)
+ match = of_match_node(tegra_uart_of_match, node);
+ if (match)
+ cdata = match->data;
+ if (cdata)
+ tegra_uart_driver.nr = cdata->uart_max_port;
ret = uart_register_driver(&tegra_uart_driver);
if (ret < 0) {
pr_err("Could not register %s driver\n",
- tegra_uart_driver.driver_name);
+ tegra_uart_driver.driver_name);
return ret;
}
--
2.7.4
next prev parent reply other threads:[~2019-09-04 4:43 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-04 4:42 [PATCH V2 00/12] serial: tegra: Tegra186 support and fixes Krishna Yarlagadda
2019-09-04 4:42 ` [PATCH V2 01/12] serial: tegra: add support to ignore read Krishna Yarlagadda
2019-09-04 4:42 ` [PATCH V2 02/12] serial: tegra: avoid reg access when clk disabled Krishna Yarlagadda
2019-09-04 4:42 ` [PATCH V2 03/12] serial: tegra: flush the RX fifo on frame error Krishna Yarlagadda
2019-09-04 4:42 ` [PATCH V2 04/12] serial: tegra: report error to upper tty layer Krishna Yarlagadda
2019-09-04 4:43 ` [PATCH V2 05/12] dt-binding: serial: tegra: add new chips Krishna Yarlagadda
2019-09-04 4:43 ` [PATCH V2 06/12] serial: tegra: check for FIFO mode enabled status Krishna Yarlagadda
2019-09-04 4:43 ` Krishna Yarlagadda [this message]
2019-09-04 4:43 ` [PATCH V2 08/12] serial: tegra: add support to use 8 bytes trigger Krishna Yarlagadda
2019-09-04 4:43 ` [PATCH V2 09/12] serial: tegra: DT for Adjusted baud rates Krishna Yarlagadda
2019-09-04 4:43 ` [PATCH V2 10/12] serial: tegra: add support to adjust baud rate Krishna Yarlagadda
2019-09-04 4:43 ` [PATCH V2 11/12] serial: tegra: report clk rate errors Krishna Yarlagadda
2019-09-04 4:43 ` [PATCH V2 12/12] serial: tegra: Add PIO mode support Krishna Yarlagadda
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