From: kan.liang@linux.intel.com
To: peterz@infradead.org, mingo@kernel.org, linux-kernel@vger.kernel.org
Cc: ak@linux.intel.com, Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH 7/9] perf/x86/intel: Add Tiger Lake CPU support
Date: Tue, 8 Oct 2019 08:50:08 -0700
Message-ID: <1570549810-25049-8-git-send-email-kan.liang@linux.intel.com> (raw)
In-Reply-To: <1570549810-25049-1-git-send-email-kan.liang@linux.intel.com>
From: Kan Liang <kan.liang@linux.intel.com>
Tiger Lake is the followon to Ice Lake. From the perspective of Intel
core PMU, there is little changes compared with Ice Lake, e.g. small
changes in event list. But it doesn't impact on core PMU functionality.
Share the perf code with Ice Lake. The event list patch will be submitted
later separately.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/intel/core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 9d91a47..fcef678 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -5033,6 +5033,8 @@ __init int intel_pmu_init(void)
/* fall through */
case INTEL_FAM6_ICELAKE_L:
case INTEL_FAM6_ICELAKE:
+ case INTEL_FAM6_TIGERLAKE_L:
+ case INTEL_FAM6_TIGERLAKE:
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
--
2.7.4
next prev parent reply index
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-08 15:50 [PATCH 0/9] perf: Several update for Comet Lake, Ice Lake and Tiger Lake kan.liang
2019-10-08 15:50 ` [PATCH 1/9] x86/cpu: Add Comet Lake to Intel family kan.liang
2019-10-08 17:05 ` [tip: x86/urgent] x86/cpu: Add Comet Lake to the Intel CPU models header tip-bot2 for Kan Liang
2019-10-08 17:05 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 2/9] perf/x86/intel: Add Comet Lake CPU support kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 3/9] perf/x86/msr: " kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 4/9] perf/x86/cstate: " kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 5/9] perf/x86/msr: Add more CPU model number for Ice Lake kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] perf/x86/msr: Add new CPU model numbers " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 6/9] perf/x86/cstate: Update C-state counters " kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` kan.liang [this message]
2019-10-09 12:59 ` [tip: perf/urgent] perf/x86/intel: Add Tiger Lake CPU support tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 8/9] perf/x86/msr: " kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 9/9] perf/x86/cstate: " kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
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