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From: Krishna Reddy <vdumpa@nvidia.com>
To: unlisted-recipients:; (no To-header on input)
Cc: <joro@8bytes.org>, <will@kernel.org>, <robin.murphy@arm.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<iommu@lists.linux-foundation.org>,
	<linux-kernel@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<treding@nvidia.com>, <yhsu@nvidia.com>, <snikam@nvidia.com>,
	<praithatha@nvidia.com>, <talho@nvidia.com>,
	<avanbrunt@nvidia.com>, <bbiswas@nvidia.com>, <olof@lixom.net>,
	<jtukkinen@nvidia.com>, <mperttunen@nvidia.com>,
	<nicolinc@nvidia.com>, Krishna Reddy <vdumpa@nvidia.com>
Subject: [PATCH v4 6/6] arm64: tegra: enable SMMU for SDHCI and EQOS on T194
Date: Wed, 30 Oct 2019 17:07:17 -0700	[thread overview]
Message-ID: <1572480437-28449-7-git-send-email-vdumpa@nvidia.com> (raw)
In-Reply-To: <1572480437-28449-1-git-send-email-vdumpa@nvidia.com>

Enable SMMU translations for SDHCI and EQOS transactions on T194.

Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra194.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 6f81e90..bf8ed7a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -3,6 +3,7 @@
 #include <dt-bindings/gpio/tegra194-gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/mailbox/tegra186-hsp.h>
+#include <dt-bindings/memory/tegra186-mc.h>
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/power/tegra194-powergate.h>
 #include <dt-bindings/reset/tegra194-reset.h>
@@ -51,6 +52,7 @@
 			clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
 			resets = <&bpmp TEGRA194_RESET_EQOS>;
 			reset-names = "eqos";
+			iommus = <&smmu TEGRA186_SID_EQOS>;
 			status = "disabled";
 
 			snps,write-requests = <1>;
@@ -413,6 +415,7 @@
 			clock-names = "sdhci";
 			resets = <&bpmp TEGRA194_RESET_SDMMC1>;
 			reset-names = "sdhci";
+			iommus = <&smmu TEGRA186_SID_SDMMC1>;
 			nvidia,pad-autocal-pull-up-offset-3v3-timeout =
 									<0x07>;
 			nvidia,pad-autocal-pull-down-offset-3v3-timeout =
@@ -435,6 +438,7 @@
 			clock-names = "sdhci";
 			resets = <&bpmp TEGRA194_RESET_SDMMC3>;
 			reset-names = "sdhci";
+			iommus = <&smmu TEGRA186_SID_SDMMC3>;
 			nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
 			nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
 			nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
@@ -462,6 +466,7 @@
 					  <&bpmp TEGRA194_CLK_PLLC4>;
 			resets = <&bpmp TEGRA194_RESET_SDMMC4>;
 			reset-names = "sdhci";
+			iommus = <&smmu TEGRA186_SID_SDMMC4>;
 			nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
 			nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
 			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
-- 
2.7.4


  parent reply	other threads:[~2019-10-31  0:07 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-31  0:07 [PATCH v4 0/6] Nvidia Arm SMMUv2 Implementation Krishna Reddy
2019-10-31  0:07 ` [PATCH v4 1/6] iommu/arm-smmu: add NVIDIA implementation for dual ARM MMU-500 usage Krishna Reddy
2019-10-31  0:07 ` [PATCH v4 2/6] dt-bindings: arm-smmu: Add binding for Tegra194 SMMU Krishna Reddy
2019-10-31  0:07 ` [PATCH v4 3/6] iommu/arm-smmu: Add global/context fault implementation hooks Krishna Reddy
2019-10-31  0:07 ` [PATCH v4 4/6] arm64: tegra: Add Memory controller DT node on T194 Krishna Reddy
2019-10-31  0:07 ` [PATCH v4 5/6] arm64: tegra: Add DT node for T194 SMMU Krishna Reddy
2019-10-31  0:07 ` Krishna Reddy [this message]
2020-03-18 20:50 ` [PATCH v4 0/6] Nvidia Arm SMMUv2 Implementation Will Deacon

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