From: Anvesh Salveru <anvesh.s@samsung.com>
To: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org
Cc: kishon@ti.com, jingoohan1@gmail.com,
gustavo.pimentel@synopsys.com, lorenzo.pieralisi@arm.com,
andrew.murray@arm.com, bhelgaas@google.com,
pankaj.dubey@samsung.com, mark.rutland@arm.com,
robh+dt@kernel.org, Anvesh Salveru <anvesh.s@samsung.com>
Subject: [PATCH v5 2/2] PCI: dwc: add support to handle ZRX-DC Compliant PHYs
Date: Fri, 13 Dec 2019 18:17:43 +0530 [thread overview]
Message-ID: <1576241263-23817-3-git-send-email-anvesh.s@samsung.com> (raw)
In-Reply-To: <1576241263-23817-1-git-send-email-anvesh.s@samsung.com>
Many platforms use DesignWare controller but the PHY can be different in
different platforms. If the PHY is compliant is to ZRX-DC specification
it helps in low power consumption during power states.
If current data rate is 8.0 GT/s or higher and PHY is not compliant to
ZRX-DC specification, then after every 100ms link should transition to
recovery state during the low power states.
DesignWare controller provides GEN3_ZRXDC_NONCOMPL field in
GEN3_RELATED_OFF to specify about ZRX-DC compliant PHY.
Platforms with ZRX-DC compliant PHY can set phy_zrxdc_compliant variable
to specify this property to the controller.
Signed-off-by: Anvesh Salveru <anvesh.s@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
Changes w.r.t v4:
- None
drivers/pci/controller/dwc/pcie-designware.c | 6 ++++++
drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
2 files changed, 10 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 820488d..36a01b7 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -556,4 +556,10 @@ void dw_pcie_setup(struct dw_pcie *pci)
PCIE_PL_CHK_REG_CHK_REG_START;
dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
}
+
+ if (pci->phy_zrxdc_compliant) {
+ val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED);
+ val &= ~PORT_LOGIC_GEN3_ZRXDC_NONCOMPL;
+ dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val);
+ }
}
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 5accdd6..36f7579 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -60,6 +60,9 @@
#define PCIE_MSI_INTR0_MASK 0x82C
#define PCIE_MSI_INTR0_STATUS 0x830
+#define PCIE_PORT_GEN3_RELATED 0x890
+#define PORT_LOGIC_GEN3_ZRXDC_NONCOMPL BIT(0)
+
#define PCIE_ATU_VIEWPORT 0x900
#define PCIE_ATU_REGION_INBOUND BIT(31)
#define PCIE_ATU_REGION_OUTBOUND 0
@@ -249,6 +252,7 @@ struct dw_pcie {
void __iomem *atu_base;
u32 num_viewport;
u8 iatu_unroll_enabled;
+ bool phy_zrxdc_compliant;
struct pcie_port pp;
struct dw_pcie_ep ep;
const struct dw_pcie_ops *ops;
--
2.7.4
prev parent reply other threads:[~2019-12-13 20:37 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20191213124754epcas5p156ab383641794e026b15902d00fc5dc6@epcas5p1.samsung.com>
2019-12-13 12:47 ` [PATCH v5 0/2] Add support to handle ZRX-DC Compliant PHYs Anvesh Salveru
[not found] ` <CGME20191213124758epcas5p1dd57ce8a5940b81ec6988228e0db8cb9@epcas5p1.samsung.com>
2019-12-13 12:47 ` [PATCH v5 1/2] phy: core: add phy_property_present method Anvesh Salveru
[not found] ` <CGME20191213124801epcas5p43782d720da90a107f75574620cbc5232@epcas5p4.samsung.com>
2019-12-13 12:47 ` Anvesh Salveru [this message]
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