* [PATCH v10 00/12] Mediatek MT8183 scpsys support
@ 2019-12-18 8:30 Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 01/12] dt-bindings: mediatek: Add property to mt8183 smi-common Weiyi Lu
` (11 more replies)
0 siblings, 12 replies; 22+ messages in thread
From: Weiyi Lu @ 2019-12-18 8:30 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
This series is based on v5.5-rc1
changes since v9:
- add new PATCH 04 and PATCH 06 to replace by new method for all compatibles
- add new PATCH 07 to remove infracfg misc driver
- minor coding sytle fix
changes since v7:
- reword in binding document [PATCH 02/14]
- fix error return checking bug in subsys clock control [PATCH 10/14]
- add power domains properity to mfgcfg patch [PATCH 14/14] from
https://patchwork.kernel.org/patch/11126199/
changes since v6:
- remove the patch of SPDX license identifier because it's already fixed
changes since v5:
- fix documentation in [PATCH 04/14]
- remove useless variable checking and reuse API of clock control in [PATCH 06/14]
- coding style fix of bus protection control in [PATCH 08/14]
- fix naming of new added data in [PATCH 09/14]
- small refactor of multiple step bus protection control in [PATCH 10/14]
changes since v4:
- add property to mt8183 smi-common
- seperate refactor patches and new add function
- add power controller device node
Weiyi Lu (12):
dt-bindings: mediatek: Add property to mt8183 smi-common
dt-bindings: soc: Add MT8183 power dt-bindings
soc: mediatek: Add basic_clk_name to scp_power_data
soc: mediatek: Use basic_clk_name for all compatibles
soc: mediatek: Add multiple step bus protection control
soc: mediatek: Use bp_table for all compatibles
soc: mediatek: Remove infracfg misc driver support
soc: mediatek: Add subsys clock control for bus protection
soc: mediatek: Add extra sram control
soc: mediatek: Add MT8183 scpsys support
arm64: dts: Add power controller device node of MT8183
arm64: dts: Add power-domains properity to mfgcfg
.../memory-controllers/mediatek,smi-common.txt | 2 +-
.../devicetree/bindings/soc/mediatek/scpsys.txt | 20 +-
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 63 +++
drivers/soc/mediatek/Kconfig | 10 -
drivers/soc/mediatek/Makefile | 3 +-
drivers/soc/mediatek/mtk-infracfg.c | 79 ---
drivers/soc/mediatek/mtk-scpsys-ext.c | 99 ++++
drivers/soc/mediatek/mtk-scpsys.c | 579 +++++++++++++++------
include/dt-bindings/power/mt8183-power.h | 26 +
include/linux/soc/mediatek/infracfg.h | 39 --
include/linux/soc/mediatek/scpsys-ext.h | 39 ++
11 files changed, 679 insertions(+), 280 deletions(-)
delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c
create mode 100644 drivers/soc/mediatek/mtk-scpsys-ext.c
create mode 100644 include/dt-bindings/power/mt8183-power.h
delete mode 100644 include/linux/soc/mediatek/infracfg.h
create mode 100644 include/linux/soc/mediatek/scpsys-ext.h
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v10 01/12] dt-bindings: mediatek: Add property to mt8183 smi-common
2019-12-18 8:30 [PATCH v10 00/12] Mediatek MT8183 scpsys support Weiyi Lu
@ 2019-12-18 8:30 ` Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 02/12] dt-bindings: soc: Add MT8183 power dt-bindings Weiyi Lu
` (10 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Weiyi Lu @ 2019-12-18 8:30 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
For scpsys driver using regmap based syscon driver API.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
.../devicetree/bindings/memory-controllers/mediatek,smi-common.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
index b478ade..01744ec 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
@@ -20,7 +20,7 @@ Required properties:
"mediatek,mt2712-smi-common"
"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
"mediatek,mt8173-smi-common"
- "mediatek,mt8183-smi-common"
+ "mediatek,mt8183-smi-common", "syscon"
- reg : the register and size of the SMI block.
- power-domains : a phandle to the power domain of this local arbiter.
- clocks : Must contain an entry for each entry in clock-names.
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v10 02/12] dt-bindings: soc: Add MT8183 power dt-bindings
2019-12-18 8:30 [PATCH v10 00/12] Mediatek MT8183 scpsys support Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 01/12] dt-bindings: mediatek: Add property to mt8183 smi-common Weiyi Lu
@ 2019-12-18 8:30 ` Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 03/12] soc: mediatek: Add basic_clk_name to scp_power_data Weiyi Lu
` (9 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Weiyi Lu @ 2019-12-18 8:30 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
Add power dt-bindings of MT8183 and introduces "BASIC" and
"SUBSYS" clock types in binding document.
The "BASIC" type is compatible to the original power control with
clock name [a-z]+[0-9]*, e.g. mm, vpu1.
The "SUBSYS" type is used for bus protection control with clock
name [a-z]+-[0-9]+, e.g. isp-0, cam-1.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
.../devicetree/bindings/soc/mediatek/scpsys.txt | 20 ++++++++++++++---
include/dt-bindings/power/mt8183-power.h | 26 ++++++++++++++++++++++
2 files changed, 43 insertions(+), 3 deletions(-)
create mode 100644 include/dt-bindings/power/mt8183-power.h
diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index 8f469d8..8e0e1ed 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -14,6 +14,7 @@ power/power-domain.yaml. It provides the power domains defined in
- include/dt-bindings/power/mt2701-power.h
- include/dt-bindings/power/mt2712-power.h
- include/dt-bindings/power/mt7622-power.h
+- include/dt-bindings/power/mt8183-power.h
Required properties:
- compatible: Should be one of:
@@ -25,18 +26,31 @@ Required properties:
- "mediatek,mt7623a-scpsys": For MT7623A SoC
- "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys": For MT7629 SoC
- "mediatek,mt8173-scpsys"
+ - "mediatek,mt8183-scpsys"
- #power-domain-cells: Must be 1
- reg: Address range of the SCPSYS unit
- infracfg: must contain a phandle to the infracfg controller
-- clock, clock-names: clocks according to the common clock binding.
- These are clocks which hardware needs to be
- enabled before enabling certain power domains.
+- clock, clock-names: Clocks according to the common clock binding.
+ Some SoCs have to groups of clocks.
+ BASIC clocks need to be enabled before enabling the
+ corresponding power domain.
+ SUBSYS clocks need to be enabled before releasing the
+ bus protection.
Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
Required clocks for MT6797: "mm", "mfg", "vdec"
Required clocks for MT7622 or MT7629: "hif_sel"
Required clocks for MT7623A: "ethif"
Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
+ Required clocks for MT8183: BASIC: "audio", "mfg", "mm", "cam", "isp",
+ "vpu", "vpu1", "vpu2", "vpu3"
+ SUBSYS: "mm-0", "mm-1", "mm-2", "mm-3",
+ "mm-4", "mm-5", "mm-6", "mm-7",
+ "mm-8", "mm-9", "isp-0", "isp-1",
+ "cam-0", "cam-1", "cam-2", "cam-3",
+ "cam-4", "cam-5", "cam-6", "vpu-0",
+ "vpu-1", "vpu-2", "vpu-3", "vpu-4",
+ "vpu-5"
Optional properties:
- vdec-supply: Power supply for the vdec power domain
diff --git a/include/dt-bindings/power/mt8183-power.h b/include/dt-bindings/power/mt8183-power.h
new file mode 100644
index 0000000..5c0c8c7
--- /dev/null
+++ b/include/dt-bindings/power/mt8183-power.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
+#define _DT_BINDINGS_POWER_MT8183_POWER_H
+
+#define MT8183_POWER_DOMAIN_AUDIO 0
+#define MT8183_POWER_DOMAIN_CONN 1
+#define MT8183_POWER_DOMAIN_MFG_ASYNC 2
+#define MT8183_POWER_DOMAIN_MFG 3
+#define MT8183_POWER_DOMAIN_MFG_CORE0 4
+#define MT8183_POWER_DOMAIN_MFG_CORE1 5
+#define MT8183_POWER_DOMAIN_MFG_2D 6
+#define MT8183_POWER_DOMAIN_DISP 7
+#define MT8183_POWER_DOMAIN_CAM 8
+#define MT8183_POWER_DOMAIN_ISP 9
+#define MT8183_POWER_DOMAIN_VDEC 10
+#define MT8183_POWER_DOMAIN_VENC 11
+#define MT8183_POWER_DOMAIN_VPU_TOP 12
+#define MT8183_POWER_DOMAIN_VPU_CORE0 13
+#define MT8183_POWER_DOMAIN_VPU_CORE1 14
+
+#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v10 03/12] soc: mediatek: Add basic_clk_name to scp_power_data
2019-12-18 8:30 [PATCH v10 00/12] Mediatek MT8183 scpsys support Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 01/12] dt-bindings: mediatek: Add property to mt8183 smi-common Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 02/12] dt-bindings: soc: Add MT8183 power dt-bindings Weiyi Lu
@ 2019-12-18 8:30 ` Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 04/12] soc: mediatek: Use basic_clk_name for all compatibles Weiyi Lu
` (8 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Weiyi Lu @ 2019-12-18 8:30 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
Try to stop extending the clk_id or clk_names if there are
more and more new BASIC clocks. To get its own clocks by the
basic_clk_name of each power domain.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 29 +++++++++++++++++++++--------
1 file changed, 21 insertions(+), 8 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index f669d37..9343277 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -117,6 +117,8 @@ enum clk_id {
* @sram_pdn_ack_bits: The mask for sram power control acked bits.
* @bus_prot_mask: The mask for single step bus protection.
* @clk_id: The basic clocks required by this power domain.
+ * @basic_clk_name: provide the same purpose with field "clk_id"
+ * by declaring basic clock prefix name rather than clk_id.
* @caps: The flag for active wake-up action.
*/
struct scp_domain_data {
@@ -127,6 +129,7 @@ struct scp_domain_data {
u32 sram_pdn_ack_bits;
u32 bus_prot_mask;
enum clk_id clk_id[MAX_CLKS];
+ const char *basic_clk_name[MAX_CLKS];
u8 caps;
};
@@ -493,16 +496,26 @@ static struct scp *init_scp(struct platform_device *pdev,
scpd->data = data;
- for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
- struct clk *c = clk[data->clk_id[j]];
+ if (data->clk_id[0]) {
+ WARN_ON(data->basic_clk_name[0]);
- if (IS_ERR(c)) {
- dev_err(&pdev->dev, "%s: clk unavailable\n",
- data->name);
- return ERR_CAST(c);
- }
+ for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
+ struct clk *c = clk[data->clk_id[j]];
+
+ if (IS_ERR(c)) {
+ dev_err(&pdev->dev,
+ "%s: clk unavailable\n",
+ data->name);
+ return ERR_CAST(c);
+ }
- scpd->clk[j] = c;
+ scpd->clk[j] = c;
+ }
+ } else if (data->basic_clk_name[0]) {
+ for (j = 0; j < MAX_CLKS &&
+ data->basic_clk_name[j]; j++)
+ scpd->clk[j] = devm_clk_get(&pdev->dev,
+ data->basic_clk_name[j]);
}
genpd->name = data->name;
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v10 04/12] soc: mediatek: Use basic_clk_name for all compatibles
2019-12-18 8:30 [PATCH v10 00/12] Mediatek MT8183 scpsys support Weiyi Lu
` (2 preceding siblings ...)
2019-12-18 8:30 ` [PATCH v10 03/12] soc: mediatek: Add basic_clk_name to scp_power_data Weiyi Lu
@ 2019-12-18 8:30 ` Weiyi Lu
2019-12-19 3:48 ` Nicolas Boichat
2019-12-18 8:30 ` [PATCH v10 05/12] soc: mediatek: Add multiple step bus protection control Weiyi Lu
` (7 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Weiyi Lu @ 2019-12-18 8:30 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
Use basic_clk_name strings for all compatibles, instead of
mixing clk_id and clk_name.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 149 +++++++++++---------------------------
1 file changed, 44 insertions(+), 105 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 9343277..db35a28 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -78,34 +78,6 @@
#define PWR_STATUS_HIF1 BIT(26) /* MT7622 */
#define PWR_STATUS_WB BIT(27) /* MT7622 */
-enum clk_id {
- CLK_NONE,
- CLK_MM,
- CLK_MFG,
- CLK_VENC,
- CLK_VENC_LT,
- CLK_ETHIF,
- CLK_VDEC,
- CLK_HIFSEL,
- CLK_JPGDEC,
- CLK_AUDIO,
- CLK_MAX,
-};
-
-static const char * const clk_names[] = {
- NULL,
- "mm",
- "mfg",
- "venc",
- "venc_lt",
- "ethif",
- "vdec",
- "hif_sel",
- "jpgdec",
- "audio",
- NULL,
-};
-
#define MAX_CLKS 3
/**
@@ -116,9 +88,7 @@ enum clk_id {
* @sram_pdn_bits: The mask for sram power control bits.
* @sram_pdn_ack_bits: The mask for sram power control acked bits.
* @bus_prot_mask: The mask for single step bus protection.
- * @clk_id: The basic clocks required by this power domain.
- * @basic_clk_name: provide the same purpose with field "clk_id"
- * by declaring basic clock prefix name rather than clk_id.
+ * @basic_clk_name: The basic clocks required by this power domain.
* @caps: The flag for active wake-up action.
*/
struct scp_domain_data {
@@ -128,7 +98,6 @@ struct scp_domain_data {
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
u32 bus_prot_mask;
- enum clk_id clk_id[MAX_CLKS];
const char *basic_clk_name[MAX_CLKS];
u8 caps;
};
@@ -414,12 +383,23 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
return ret;
}
-static void init_clks(struct platform_device *pdev, struct clk **clk)
+static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
+ const char * const *name)
{
int i;
- for (i = CLK_NONE + 1; i < CLK_MAX; i++)
- clk[i] = devm_clk_get(&pdev->dev, clk_names[i]);
+ for (i = 0; i < MAX_CLKS && name[i]; i++) {
+ clk[i] = devm_clk_get(&pdev->dev, name[i]);
+
+ if (IS_ERR(clk[i])) {
+ dev_err(&pdev->dev,
+ "get basic clk %s fail %ld\n",
+ name[i], PTR_ERR(clk[i]));
+ return PTR_ERR(clk[i]);
+ }
+ }
+
+ return 0;
}
static struct scp *init_scp(struct platform_device *pdev,
@@ -429,9 +409,8 @@ static struct scp *init_scp(struct platform_device *pdev,
{
struct genpd_onecell_data *pd_data;
struct resource *res;
- int i, j;
+ int i, ret;
struct scp *scp;
- struct clk *clk[CLK_MAX];
scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
if (!scp)
@@ -484,8 +463,6 @@ static struct scp *init_scp(struct platform_device *pdev,
pd_data->num_domains = num;
- init_clks(pdev, clk);
-
for (i = 0; i < num; i++) {
struct scp_domain *scpd = &scp->domains[i];
struct generic_pm_domain *genpd = &scpd->genpd;
@@ -496,27 +473,9 @@ static struct scp *init_scp(struct platform_device *pdev,
scpd->data = data;
- if (data->clk_id[0]) {
- WARN_ON(data->basic_clk_name[0]);
-
- for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
- struct clk *c = clk[data->clk_id[j]];
-
- if (IS_ERR(c)) {
- dev_err(&pdev->dev,
- "%s: clk unavailable\n",
- data->name);
- return ERR_CAST(c);
- }
-
- scpd->clk[j] = c;
- }
- } else if (data->basic_clk_name[0]) {
- for (j = 0; j < MAX_CLKS &&
- data->basic_clk_name[j]; j++)
- scpd->clk[j] = devm_clk_get(&pdev->dev,
- data->basic_clk_name[j]);
- }
+ ret = init_basic_clks(pdev, scpd->clk, data->basic_clk_name);
+ if (ret)
+ return ERR_PTR(ret);
genpd->name = data->name;
genpd->power_off = scpsys_power_off;
@@ -573,7 +532,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_CONN_PWR_CON,
.bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
MT2701_TOP_AXI_PROT_EN_CONN_S,
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_DISP] = {
@@ -581,7 +539,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.sta_mask = PWR_STATUS_DISP,
.ctl_offs = SPM_DIS_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
- .clk_id = {CLK_MM},
+ .basic_clk_name = {"mm"},
.bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0,
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -591,7 +549,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_MFG_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {CLK_MFG},
+ .basic_clk_name = {"mfg"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_VDEC] = {
@@ -600,7 +558,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_VDE_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {CLK_MM},
+ .basic_clk_name = {"mm"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_ISP] = {
@@ -609,7 +567,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_ISP_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
- .clk_id = {CLK_MM},
+ .basic_clk_name = {"mm"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_BDP] = {
@@ -617,7 +575,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.sta_mask = PWR_STATUS_BDP,
.ctl_offs = SPM_BDP_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_ETH] = {
@@ -626,7 +583,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_ETH_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_ETHIF},
+ .basic_clk_name = {"ethif"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_HIF] = {
@@ -635,14 +592,13 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_HIF_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_ETHIF},
+ .basic_clk_name = {"ethif"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_IFR_MSC] = {
.name = "ifr_msc",
.sta_mask = PWR_STATUS_IFR_MSC,
.ctl_offs = SPM_IFR_MSC_PWR_CON,
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
};
@@ -657,7 +613,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_DIS_PWR_CON,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {CLK_MM},
+ .basic_clk_name = {"mm"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_VDEC] = {
@@ -666,7 +622,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_VDE_PWR_CON,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {CLK_MM, CLK_VDEC},
+ .basic_clk_name = {"mm", "vdec"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_VENC] = {
@@ -675,7 +631,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_VEN_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_MM, CLK_VENC, CLK_JPGDEC},
+ .basic_clk_name = {"mm", "venc", "jpgdec"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_ISP] = {
@@ -684,7 +640,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_ISP_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
- .clk_id = {CLK_MM},
+ .basic_clk_name = {"mm"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_AUDIO] = {
@@ -693,7 +649,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_AUDIO_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_AUDIO},
+ .basic_clk_name = {"audio"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_USB] = {
@@ -702,7 +658,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_USB_PWR_CON,
.sram_pdn_bits = GENMASK(10, 8),
.sram_pdn_ack_bits = GENMASK(14, 12),
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_USB2] = {
@@ -711,7 +666,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_USB2_PWR_CON,
.sram_pdn_bits = GENMASK(10, 8),
.sram_pdn_ack_bits = GENMASK(14, 12),
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_MFG] = {
@@ -720,7 +674,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_MFG_PWR_CON,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(16, 16),
- .clk_id = {CLK_MFG},
+ .basic_clk_name = {"mfg"},
.bus_prot_mask = BIT(14) | BIT(21) | BIT(23),
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -730,7 +684,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x02c0,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(16, 16),
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_MFG_SC2] = {
@@ -739,7 +692,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x02c4,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(16, 16),
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_MFG_SC3] = {
@@ -748,7 +700,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x01f8,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(16, 16),
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
};
@@ -773,7 +724,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x300,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {CLK_VDEC},
+ .basic_clk_name = {"vdec"},
},
[MT6797_POWER_DOMAIN_VENC] = {
.name = "venc",
@@ -781,7 +732,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x304,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_NONE},
},
[MT6797_POWER_DOMAIN_ISP] = {
.name = "isp",
@@ -789,7 +739,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x308,
.sram_pdn_bits = GENMASK(9, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
- .clk_id = {CLK_NONE},
},
[MT6797_POWER_DOMAIN_MM] = {
.name = "mm",
@@ -797,7 +746,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x30C,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {CLK_MM},
+ .basic_clk_name = {"mm"},
.bus_prot_mask = (BIT(1) | BIT(2)),
},
[MT6797_POWER_DOMAIN_AUDIO] = {
@@ -806,7 +755,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x314,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_NONE},
},
[MT6797_POWER_DOMAIN_MFG_ASYNC] = {
.name = "mfg_async",
@@ -814,7 +762,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x334,
.sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0,
- .clk_id = {CLK_MFG},
+ .basic_clk_name = {"mfg"},
},
[MT6797_POWER_DOMAIN_MJC] = {
.name = "mjc",
@@ -822,7 +770,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = 0x310,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {CLK_NONE},
},
};
@@ -847,7 +794,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_ETHSYS_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_NONE},
.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS,
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -857,7 +803,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_HIF0_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_HIFSEL},
+ .basic_clk_name = {"hif_sel"},
.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0,
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -867,7 +813,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_HIF1_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_HIFSEL},
+ .basic_clk_name = {"hif_sel"},
.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1,
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
@@ -877,7 +823,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_WB_PWR_CON,
.sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0,
- .clk_id = {CLK_NONE},
.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
.caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM,
},
@@ -894,7 +839,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_CONN_PWR_CON,
.bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
MT2701_TOP_AXI_PROT_EN_CONN_S,
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT7623A_POWER_DOMAIN_ETH] = {
@@ -903,7 +847,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_ETH_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_ETHIF},
+ .basic_clk_name = {"ethif"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT7623A_POWER_DOMAIN_HIF] = {
@@ -912,14 +856,13 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_HIF_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_ETHIF},
+ .basic_clk_name = {"ethif"},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT7623A_POWER_DOMAIN_IFR_MSC] = {
.name = "ifr_msc",
.sta_mask = PWR_STATUS_IFR_MSC,
.ctl_offs = SPM_IFR_MSC_PWR_CON,
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
};
@@ -935,7 +878,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_VDE_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {CLK_MM},
+ .basic_clk_name = {"mm"},
},
[MT8173_POWER_DOMAIN_VENC] = {
.name = "venc",
@@ -943,7 +886,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_VEN_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_MM, CLK_VENC},
+ .basic_clk_name = {"mm", "venc"},
},
[MT8173_POWER_DOMAIN_ISP] = {
.name = "isp",
@@ -951,7 +894,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_ISP_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
- .clk_id = {CLK_MM},
+ .basic_clk_name = {"mm"},
},
[MT8173_POWER_DOMAIN_MM] = {
.name = "mm",
@@ -959,7 +902,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_DIS_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
- .clk_id = {CLK_MM},
+ .basic_clk_name = {"mm"},
.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
MT8173_TOP_AXI_PROT_EN_MM_M1,
},
@@ -969,7 +912,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_VEN2_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_MM, CLK_VENC_LT},
+ .basic_clk_name = {"mm", "venc_lt"},
},
[MT8173_POWER_DOMAIN_AUDIO] = {
.name = "audio",
@@ -977,7 +920,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_AUDIO_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_NONE},
},
[MT8173_POWER_DOMAIN_USB] = {
.name = "usb",
@@ -985,7 +927,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_USB_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .clk_id = {CLK_NONE},
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8173_POWER_DOMAIN_MFG_ASYNC] = {
@@ -994,7 +935,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = 0,
- .clk_id = {CLK_MFG},
+ .basic_clk_name = {"mfg"},
},
[MT8173_POWER_DOMAIN_MFG_2D] = {
.name = "mfg_2d",
@@ -1002,7 +943,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_MFG_2D_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
- .clk_id = {CLK_NONE},
},
[MT8173_POWER_DOMAIN_MFG] = {
.name = "mfg",
@@ -1010,7 +950,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_MFG_PWR_CON,
.sram_pdn_bits = GENMASK(13, 8),
.sram_pdn_ack_bits = GENMASK(21, 16),
- .clk_id = {CLK_NONE},
.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
MT8173_TOP_AXI_PROT_EN_MFG_M0 |
MT8173_TOP_AXI_PROT_EN_MFG_M1 |
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v10 05/12] soc: mediatek: Add multiple step bus protection control
2019-12-18 8:30 [PATCH v10 00/12] Mediatek MT8183 scpsys support Weiyi Lu
` (3 preceding siblings ...)
2019-12-18 8:30 ` [PATCH v10 04/12] soc: mediatek: Use basic_clk_name for all compatibles Weiyi Lu
@ 2019-12-18 8:30 ` Weiyi Lu
2019-12-19 3:51 ` Nicolas Boichat
2019-12-18 8:30 ` [PATCH v10 06/12] soc: mediatek: Use bp_table for all compatibles Weiyi Lu
` (6 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Weiyi Lu @ 2019-12-18 8:30 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
Both MT8183 & MT6765 have more control steps of bus protection
than previous project. And there add more bus protection registers
reside at infracfg & smi-common. Also add new APIs for multiple
step bus protection control with more customized arguments.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/Makefile | 2 +-
drivers/soc/mediatek/mtk-scpsys-ext.c | 99 +++++++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-scpsys.c | 39 +++++++++----
include/linux/soc/mediatek/scpsys-ext.h | 39 +++++++++++++
4 files changed, 168 insertions(+), 11 deletions(-)
create mode 100644 drivers/soc/mediatek/mtk-scpsys-ext.c
create mode 100644 include/linux/soc/mediatek/scpsys-ext.h
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index b017330..b442be9 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
-obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
+obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
diff --git a/drivers/soc/mediatek/mtk-scpsys-ext.c b/drivers/soc/mediatek/mtk-scpsys-ext.c
new file mode 100644
index 0000000..8150d4f
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-scpsys-ext.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Owen Chen <Owen.Chen@mediatek.com>
+ */
+#include <linux/ktime.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/soc/mediatek/scpsys-ext.h>
+
+#define MTK_POLL_DELAY_US 10
+#define MTK_POLL_TIMEOUT USEC_PER_SEC
+
+static int set_bus_protection(struct regmap *map, u32 mask, u32 ack_mask,
+ u32 reg_set, u32 reg_sta, u32 reg_en)
+{
+ u32 val;
+
+ if (reg_set)
+ regmap_write(map, reg_set, mask);
+ else
+ regmap_update_bits(map, reg_en, mask, mask);
+
+ return regmap_read_poll_timeout(map, reg_sta,
+ val, (val & ack_mask) == ack_mask,
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+}
+
+static int clear_bus_protection(struct regmap *map, u32 mask, u32 ack_mask,
+ u32 reg_clr, u32 reg_sta, u32 reg_en)
+{
+ u32 val;
+
+ if (reg_clr)
+ regmap_write(map, reg_clr, mask);
+ else
+ regmap_update_bits(map, reg_en, mask, 0);
+
+ return regmap_read_poll_timeout(map, reg_sta,
+ val, !(val & ack_mask),
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+}
+
+int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
+ struct regmap *infracfg, struct regmap *smi_common)
+{
+ int i;
+
+ for (i = 0; i < MAX_STEPS; i++) {
+ struct regmap *map = NULL;
+ int ret;
+
+ if (bp_table[i].type == INVALID_TYPE)
+ break;
+ else if (bp_table[i].type == IFR_TYPE)
+ map = infracfg;
+ else if (bp_table[i].type == SMI_TYPE)
+ map = smi_common;
+
+ ret = set_bus_protection(map,
+ bp_table[i].mask, bp_table[i].mask,
+ bp_table[i].set_ofs, bp_table[i].sta_ofs,
+ bp_table[i].en_ofs);
+
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
+ struct regmap *infracfg, struct regmap *smi_common)
+{
+ int i;
+
+ for (i = MAX_STEPS - 1; i >= 0; i--) {
+ struct regmap *map = NULL;
+ int ret;
+
+ if (bp_table[i].type == INVALID_TYPE)
+ continue;
+ else if (bp_table[i].type == IFR_TYPE)
+ map = infracfg;
+ else if (bp_table[i].type == SMI_TYPE)
+ map = smi_common;
+
+ ret = clear_bus_protection(map,
+ bp_table[i].mask, bp_table[i].clr_ack_mask,
+ bp_table[i].clr_ofs, bp_table[i].sta_ofs,
+ bp_table[i].en_ofs);
+
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index db35a28..5699d9f 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -12,6 +12,7 @@
#include <linux/pm_domain.h>
#include <linux/regulator/consumer.h>
#include <linux/soc/mediatek/infracfg.h>
+#include <linux/soc/mediatek/scpsys-ext.h>
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/power/mt2712-power.h>
@@ -90,6 +91,7 @@
* @bus_prot_mask: The mask for single step bus protection.
* @basic_clk_name: The basic clocks required by this power domain.
* @caps: The flag for active wake-up action.
+ * @bp_table: The mask table for multiple step bus protection.
*/
struct scp_domain_data {
const char *name;
@@ -100,6 +102,7 @@ struct scp_domain_data {
u32 bus_prot_mask;
const char *basic_clk_name[MAX_CLKS];
u8 caps;
+ struct bus_prot bp_table[MAX_STEPS];
};
struct scp;
@@ -123,6 +126,7 @@ struct scp {
struct device *dev;
void __iomem *base;
struct regmap *infracfg;
+ struct regmap *smi_common;
struct scp_ctrl_reg ctrl_reg;
bool bus_prot_reg_update;
};
@@ -252,24 +256,28 @@ static int scpsys_bus_protect_enable(struct scp_domain *scpd)
{
struct scp *scp = scpd->scp;
- if (!scpd->data->bus_prot_mask)
- return 0;
+ if (scpd->data->bus_prot_mask) {
+ return mtk_infracfg_set_bus_protection(scp->infracfg,
+ scpd->data->bus_prot_mask,
+ scp->bus_prot_reg_update);
+ }
- return mtk_infracfg_set_bus_protection(scp->infracfg,
- scpd->data->bus_prot_mask,
- scp->bus_prot_reg_update);
+ return mtk_scpsys_ext_set_bus_protection(scpd->data->bp_table,
+ scp->infracfg, scp->smi_common);
}
static int scpsys_bus_protect_disable(struct scp_domain *scpd)
{
struct scp *scp = scpd->scp;
- if (!scpd->data->bus_prot_mask)
- return 0;
+ if (scpd->data->bus_prot_mask) {
+ return mtk_infracfg_clear_bus_protection(scp->infracfg,
+ scpd->data->bus_prot_mask,
+ scp->bus_prot_reg_update);
+ }
- return mtk_infracfg_clear_bus_protection(scp->infracfg,
- scpd->data->bus_prot_mask,
- scp->bus_prot_reg_update);
+ return mtk_scpsys_ext_clear_bus_protection(scpd->data->bp_table,
+ scp->infracfg, scp->smi_common);
}
static int scpsys_power_on(struct generic_pm_domain *genpd)
@@ -448,6 +456,17 @@ static struct scp *init_scp(struct platform_device *pdev,
return ERR_CAST(scp->infracfg);
}
+ scp->smi_common = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "smi_comm");
+
+ if (scp->smi_common == ERR_PTR(-ENODEV)) {
+ scp->smi_common = NULL;
+ } else if (IS_ERR(scp->smi_common)) {
+ dev_err(&pdev->dev, "Cannot find smi_common controller: %ld\n",
+ PTR_ERR(scp->smi_common));
+ return ERR_CAST(scp->smi_common);
+ }
+
for (i = 0; i < num; i++) {
struct scp_domain *scpd = &scp->domains[i];
const struct scp_domain_data *data = &scp_domain_data[i];
diff --git a/include/linux/soc/mediatek/scpsys-ext.h b/include/linux/soc/mediatek/scpsys-ext.h
new file mode 100644
index 0000000..3e5b84d
--- /dev/null
+++ b/include/linux/soc/mediatek/scpsys-ext.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __SOC_MEDIATEK_SCPSYS_EXT_H
+#define __SOC_MEDIATEK_SCPSYS_EXT_H
+
+#define MAX_STEPS 4
+
+#define BUS_PROT(_type, _set_ofs, _clr_ofs, \
+ _en_ofs, _sta_ofs, _mask, _clr_ack_mask) { \
+ .type = _type, \
+ .set_ofs = _set_ofs, \
+ .clr_ofs = _clr_ofs, \
+ .en_ofs = _en_ofs, \
+ .sta_ofs = _sta_ofs, \
+ .mask = _mask, \
+ .clr_ack_mask = _clr_ack_mask, \
+ }
+
+enum regmap_type {
+ INVALID_TYPE = 0,
+ IFR_TYPE,
+ SMI_TYPE,
+};
+
+struct bus_prot {
+ enum regmap_type type;
+ u32 set_ofs;
+ u32 clr_ofs;
+ u32 en_ofs;
+ u32 sta_ofs;
+ u32 mask;
+ u32 clr_ack_mask;
+};
+
+int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
+ struct regmap *infracfg, struct regmap *smi_common);
+int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
+ struct regmap *infracfg, struct regmap *smi_common);
+
+#endif /* __SOC_MEDIATEK_SCPSYS_EXT_H */
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v10 06/12] soc: mediatek: Use bp_table for all compatibles
2019-12-18 8:30 [PATCH v10 00/12] Mediatek MT8183 scpsys support Weiyi Lu
` (4 preceding siblings ...)
2019-12-18 8:30 ` [PATCH v10 05/12] soc: mediatek: Add multiple step bus protection control Weiyi Lu
@ 2019-12-18 8:30 ` Weiyi Lu
2019-12-19 3:54 ` Nicolas Boichat
2019-12-18 8:30 ` [PATCH v10 07/12] soc: mediatek: Remove infracfg misc driver support Weiyi Lu
` (5 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Weiyi Lu @ 2019-12-18 8:30 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
Only use bp_table for bus protection of all compatibles,
instead of mixing bus_prot_mask and bus_prot_reg_update.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 94 ++++++++++++++++++++-------------------
1 file changed, 48 insertions(+), 46 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 5699d9f..c438c53 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -11,7 +11,6 @@
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/regulator/consumer.h>
-#include <linux/soc/mediatek/infracfg.h>
#include <linux/soc/mediatek/scpsys-ext.h>
#include <dt-bindings/power/mt2701-power.h>
@@ -88,7 +87,6 @@
* @ctl_offs: The offset for main power control register.
* @sram_pdn_bits: The mask for sram power control bits.
* @sram_pdn_ack_bits: The mask for sram power control acked bits.
- * @bus_prot_mask: The mask for single step bus protection.
* @basic_clk_name: The basic clocks required by this power domain.
* @caps: The flag for active wake-up action.
* @bp_table: The mask table for multiple step bus protection.
@@ -99,7 +97,6 @@ struct scp_domain_data {
int ctl_offs;
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
- u32 bus_prot_mask;
const char *basic_clk_name[MAX_CLKS];
u8 caps;
struct bus_prot bp_table[MAX_STEPS];
@@ -128,7 +125,6 @@ struct scp {
struct regmap *infracfg;
struct regmap *smi_common;
struct scp_ctrl_reg ctrl_reg;
- bool bus_prot_reg_update;
};
struct scp_subdomain {
@@ -142,7 +138,6 @@ struct scp_soc_data {
const struct scp_subdomain *subdomains;
int num_subdomains;
const struct scp_ctrl_reg regs;
- bool bus_prot_reg_update;
};
static int scpsys_domain_is_on(struct scp_domain *scpd)
@@ -256,12 +251,6 @@ static int scpsys_bus_protect_enable(struct scp_domain *scpd)
{
struct scp *scp = scpd->scp;
- if (scpd->data->bus_prot_mask) {
- return mtk_infracfg_set_bus_protection(scp->infracfg,
- scpd->data->bus_prot_mask,
- scp->bus_prot_reg_update);
- }
-
return mtk_scpsys_ext_set_bus_protection(scpd->data->bp_table,
scp->infracfg, scp->smi_common);
}
@@ -270,12 +259,6 @@ static int scpsys_bus_protect_disable(struct scp_domain *scpd)
{
struct scp *scp = scpd->scp;
- if (scpd->data->bus_prot_mask) {
- return mtk_infracfg_clear_bus_protection(scp->infracfg,
- scpd->data->bus_prot_mask,
- scp->bus_prot_reg_update);
- }
-
return mtk_scpsys_ext_clear_bus_protection(scpd->data->bp_table,
scp->infracfg, scp->smi_common);
}
@@ -412,8 +395,7 @@ static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
static struct scp *init_scp(struct platform_device *pdev,
const struct scp_domain_data *scp_domain_data, int num,
- const struct scp_ctrl_reg *scp_ctrl_reg,
- bool bus_prot_reg_update)
+ const struct scp_ctrl_reg *scp_ctrl_reg)
{
struct genpd_onecell_data *pd_data;
struct resource *res;
@@ -427,8 +409,6 @@ static struct scp *init_scp(struct platform_device *pdev,
scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs;
scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs;
- scp->bus_prot_reg_update = bus_prot_reg_update;
-
scp->dev = &pdev->dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -549,8 +529,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.name = "conn",
.sta_mask = PWR_STATUS_CONN,
.ctl_offs = SPM_CONN_PWR_CON,
- .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
- MT2701_TOP_AXI_PROT_EN_CONN_S,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ BIT(2) | BIT(8), BIT(2) | BIT(8)),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_DISP] = {
@@ -559,7 +541,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_DIS_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.basic_clk_name = {"mm"},
- .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ BIT(1), BIT(1)),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_MFG] = {
@@ -694,7 +679,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(16, 16),
.basic_clk_name = {"mfg"},
- .bus_prot_mask = BIT(14) | BIT(21) | BIT(23),
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x260, 0x264, 0x220, 0x228,
+ BIT(14) | BIT(21) | BIT(23),
+ BIT(14) | BIT(21) | BIT(23)),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_MFG_SC1] = {
@@ -766,7 +755,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.basic_clk_name = {"mm"},
- .bus_prot_mask = (BIT(1) | BIT(2)),
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ BIT(1) | BIT(2), BIT(1) | BIT(2)),
+ },
},
[MT6797_POWER_DOMAIN_AUDIO] = {
.name = "audio",
@@ -813,7 +805,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_ETHSYS_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ BIT(3) | BIT(17), BIT(3) | BIT(17)),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT7622_POWER_DOMAIN_HIF0] = {
@@ -823,7 +818,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.basic_clk_name = {"hif_sel"},
- .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ BIT(24) | BIT(25), BIT(24) | BIT(25)),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT7622_POWER_DOMAIN_HIF1] = {
@@ -833,7 +831,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.basic_clk_name = {"hif_sel"},
- .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ GENMASK(28, 26), GENMASK(28, 26)),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT7622_POWER_DOMAIN_WB] = {
@@ -842,7 +843,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_WB_PWR_CON,
.sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0,
- .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ BIT(2) | GENMASK(8, 6), BIT(2) | GENMASK(8, 6)),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM,
},
};
@@ -856,8 +860,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.name = "conn",
.sta_mask = PWR_STATUS_CONN,
.ctl_offs = SPM_CONN_PWR_CON,
- .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
- MT2701_TOP_AXI_PROT_EN_CONN_S,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ BIT(2) | BIT(8), BIT(2) | BIT(8)),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT7623A_POWER_DOMAIN_ETH] = {
@@ -922,8 +928,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.basic_clk_name = {"mm"},
- .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
- MT8173_TOP_AXI_PROT_EN_MM_M1,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ BIT(1) | BIT(2), BIT(1) | BIT(2)),
+ },
},
[MT8173_POWER_DOMAIN_VENC_LT] = {
.name = "venc_lt",
@@ -969,10 +977,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_MFG_PWR_CON,
.sram_pdn_bits = GENMASK(13, 8),
.sram_pdn_ack_bits = GENMASK(21, 16),
- .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
- MT8173_TOP_AXI_PROT_EN_MFG_M0 |
- MT8173_TOP_AXI_PROT_EN_MFG_M1 |
- MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ BIT(14) | GENMASK(23, 21),
+ BIT(14) | GENMASK(23, 21)),
+ },
},
};
@@ -988,7 +997,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
},
- .bus_prot_reg_update = true,
};
static const struct scp_soc_data mt2712_data = {
@@ -1000,7 +1008,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
},
- .bus_prot_reg_update = false,
};
static const struct scp_soc_data mt6797_data = {
@@ -1012,7 +1019,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.pwr_sta_offs = SPM_PWR_STATUS_MT6797,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797
},
- .bus_prot_reg_update = true,
};
static const struct scp_soc_data mt7622_data = {
@@ -1022,7 +1028,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
},
- .bus_prot_reg_update = true,
};
static const struct scp_soc_data mt7623a_data = {
@@ -1032,7 +1037,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
},
- .bus_prot_reg_update = true,
};
static const struct scp_soc_data mt8173_data = {
@@ -1044,7 +1048,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
},
- .bus_prot_reg_update = true,
};
/*
@@ -1085,8 +1088,7 @@ static int scpsys_probe(struct platform_device *pdev)
soc = of_device_get_match_data(&pdev->dev);
- scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs,
- soc->bus_prot_reg_update);
+ scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs);
if (IS_ERR(scp))
return PTR_ERR(scp);
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v10 07/12] soc: mediatek: Remove infracfg misc driver support
2019-12-18 8:30 [PATCH v10 00/12] Mediatek MT8183 scpsys support Weiyi Lu
` (5 preceding siblings ...)
2019-12-18 8:30 ` [PATCH v10 06/12] soc: mediatek: Use bp_table for all compatibles Weiyi Lu
@ 2019-12-18 8:30 ` Weiyi Lu
2019-12-19 3:56 ` Nicolas Boichat
2019-12-18 8:30 ` [PATCH v10 08/12] soc: mediatek: Add subsys clock control for bus protection Weiyi Lu
` (4 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Weiyi Lu @ 2019-12-18 8:30 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
In previous patches, we introduce scpsys-ext driver that covers
the functions which infracfg misc driver provided.
And then replace bus_prot_mask with bp_table of all compatibles.
Now, we're going to remove infracfg misc drvier which is no longer
being used.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/Kconfig | 10 -----
drivers/soc/mediatek/Makefile | 3 +-
drivers/soc/mediatek/mtk-infracfg.c | 79 -----------------------------------
include/linux/soc/mediatek/infracfg.h | 39 -----------------
4 files changed, 1 insertion(+), 130 deletions(-)
delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c
delete mode 100644 include/linux/soc/mediatek/infracfg.h
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index 2114b56..f837b3c 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -10,21 +10,12 @@ config MTK_CMDQ
depends on ARCH_MEDIATEK || COMPILE_TEST
select MAILBOX
select MTK_CMDQ_MBOX
- select MTK_INFRACFG
help
Say yes here to add support for the MediaTek Command Queue (CMDQ)
driver. The CMDQ is used to help read/write registers with critical
time limitation, such as updating display configuration during the
vblank.
-config MTK_INFRACFG
- bool "MediaTek INFRACFG Support"
- select REGMAP
- help
- Say yes here to add support for the MediaTek INFRACFG controller. The
- INFRACFG controller contains various infrastructure registers not
- directly associated to any device.
-
config MTK_PMIC_WRAP
tristate "MediaTek PMIC Wrapper Support"
depends on RESET_CONTROLLER
@@ -38,7 +29,6 @@ config MTK_SCPSYS
bool "MediaTek SCPSYS Support"
default ARCH_MEDIATEK
select REGMAP
- select MTK_INFRACFG
select PM_GENERIC_DOMAINS if PM
help
Say yes here to add support for the MediaTek SCPSYS power domain
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index b442be9..7bf7e88 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,5 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
-obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
-obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
+obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o mtk-scpsys-ext.o
diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c
deleted file mode 100644
index 341c7ac..0000000
--- a/drivers/soc/mediatek/mtk-infracfg.c
+++ /dev/null
@@ -1,79 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
- */
-
-#include <linux/export.h>
-#include <linux/jiffies.h>
-#include <linux/regmap.h>
-#include <linux/soc/mediatek/infracfg.h>
-#include <asm/processor.h>
-
-#define MTK_POLL_DELAY_US 10
-#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ))
-
-#define INFRA_TOPAXI_PROTECTEN 0x0220
-#define INFRA_TOPAXI_PROTECTSTA1 0x0228
-#define INFRA_TOPAXI_PROTECTEN_SET 0x0260
-#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264
-
-/**
- * mtk_infracfg_set_bus_protection - enable bus protection
- * @regmap: The infracfg regmap
- * @mask: The mask containing the protection bits to be enabled.
- * @reg_update: The boolean flag determines to set the protection bits
- * by regmap_update_bits with enable register(PROTECTEN) or
- * by regmap_write with set register(PROTECTEN_SET).
- *
- * This function enables the bus protection bits for disabled power
- * domains so that the system does not hang when some unit accesses the
- * bus while in power down.
- */
-int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
- bool reg_update)
-{
- u32 val;
- int ret;
-
- if (reg_update)
- regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask,
- mask);
- else
- regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask);
-
- ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
- val, (val & mask) == mask,
- MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
-
- return ret;
-}
-
-/**
- * mtk_infracfg_clear_bus_protection - disable bus protection
- * @regmap: The infracfg regmap
- * @mask: The mask containing the protection bits to be disabled.
- * @reg_update: The boolean flag determines to clear the protection bits
- * by regmap_update_bits with enable register(PROTECTEN) or
- * by regmap_write with clear register(PROTECTEN_CLR).
- *
- * This function disables the bus protection bits previously enabled with
- * mtk_infracfg_set_bus_protection.
- */
-
-int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
- bool reg_update)
-{
- int ret;
- u32 val;
-
- if (reg_update)
- regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0);
- else
- regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask);
-
- ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
- val, !(val & mask),
- MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
-
- return ret;
-}
diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
deleted file mode 100644
index fd25f01..0000000
--- a/include/linux/soc/mediatek/infracfg.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __SOC_MEDIATEK_INFRACFG_H
-#define __SOC_MEDIATEK_INFRACFG_H
-
-#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0)
-#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
-#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
-#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6)
-#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9)
-#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11)
-#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12)
-#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13)
-#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
-#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15)
-#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16)
-#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17)
-#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18)
-#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19)
-#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20)
-#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
-#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
-#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
-
-#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
-#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
-#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)
-
-#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17))
-#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25))
-#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \
- BIT(28))
-#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
- BIT(7) | BIT(8))
-
-int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
- bool reg_update);
-int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
- bool reg_update);
-#endif /* __SOC_MEDIATEK_INFRACFG_H */
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v10 08/12] soc: mediatek: Add subsys clock control for bus protection
2019-12-18 8:30 [PATCH v10 00/12] Mediatek MT8183 scpsys support Weiyi Lu
` (6 preceding siblings ...)
2019-12-18 8:30 ` [PATCH v10 07/12] soc: mediatek: Remove infracfg misc driver support Weiyi Lu
@ 2019-12-18 8:30 ` Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 09/12] soc: mediatek: Add extra sram control Weiyi Lu
` (3 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Weiyi Lu @ 2019-12-18 8:30 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
Add subsys CG control flow before/after the bus protect control
due to bus protection need SMI bus relative CGs enabled to feedback
its ack.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
---
drivers/soc/mediatek/mtk-scpsys.c | 72 +++++++++++++++++++++++++++++++++++++--
1 file changed, 70 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index c438c53..9f06f17 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -79,6 +79,7 @@
#define PWR_STATUS_WB BIT(27) /* MT7622 */
#define MAX_CLKS 3
+#define MAX_SUBSYS_CLKS 10
/**
* struct scp_domain_data - scp domain data for power on/off flow
@@ -88,6 +89,8 @@
* @sram_pdn_bits: The mask for sram power control bits.
* @sram_pdn_ack_bits: The mask for sram power control acked bits.
* @basic_clk_name: The basic clocks required by this power domain.
+ * @subsys_clk_prefix: The prefix name of the clocks need to be enabled
+ * before releasing bus protection.
* @caps: The flag for active wake-up action.
* @bp_table: The mask table for multiple step bus protection.
*/
@@ -98,6 +101,7 @@ struct scp_domain_data {
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
const char *basic_clk_name[MAX_CLKS];
+ const char *subsys_clk_prefix;
u8 caps;
struct bus_prot bp_table[MAX_STEPS];
};
@@ -108,6 +112,7 @@ struct scp_domain {
struct generic_pm_domain genpd;
struct scp *scp;
struct clk *clk[MAX_CLKS];
+ struct clk *subsys_clk[MAX_SUBSYS_CLKS];
const struct scp_domain_data *data;
struct regulator *supply;
};
@@ -301,16 +306,22 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
val |= PWR_RST_B_BIT;
writel(val, ctl_addr);
- ret = scpsys_sram_enable(scpd, ctl_addr);
+ ret = scpsys_clk_enable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
if (ret < 0)
goto err_pwr_ack;
+ ret = scpsys_sram_enable(scpd, ctl_addr);
+ if (ret < 0)
+ goto err_sram;
+
ret = scpsys_bus_protect_disable(scpd);
if (ret < 0)
- goto err_pwr_ack;
+ goto err_sram;
return 0;
+err_sram:
+ scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
err_pwr_ack:
scpsys_clk_disable(scpd->clk, MAX_CLKS);
err_clk:
@@ -337,6 +348,8 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
if (ret < 0)
goto out;
+ scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
+
/* subsys power off */
val = readl(ctl_addr);
val |= PWR_ISO_BIT;
@@ -374,6 +387,48 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
return ret;
}
+static int init_subsys_clks(struct platform_device *pdev,
+ const char *prefix, struct clk **clk)
+{
+ struct device_node *node = pdev->dev.of_node;
+ u32 prefix_len, sub_clk_cnt = 0;
+ struct property *prop;
+ const char *clk_name;
+
+ if (!node) {
+ dev_err(&pdev->dev, "Cannot find scpsys node: %ld\n",
+ PTR_ERR(node));
+ return PTR_ERR(node);
+ }
+
+ prefix_len = strlen(prefix);
+
+ of_property_for_each_string(node, "clock-names", prop, clk_name) {
+ if (!strncmp(clk_name, prefix, prefix_len) &&
+ (clk_name[prefix_len] == '-')) {
+ if (sub_clk_cnt >= MAX_SUBSYS_CLKS) {
+ dev_err(&pdev->dev,
+ "subsys clk out of range %d\n",
+ sub_clk_cnt);
+ return -ENOMEM;
+ }
+
+ clk[sub_clk_cnt] = devm_clk_get(&pdev->dev,
+ clk_name);
+
+ if (IS_ERR(clk[sub_clk_cnt])) {
+ dev_err(&pdev->dev,
+ "Subsys clk get fail %ld\n",
+ PTR_ERR(clk[sub_clk_cnt]));
+ return PTR_ERR(clk[sub_clk_cnt]);
+ }
+ sub_clk_cnt++;
+ }
+ }
+
+ return sub_clk_cnt;
+}
+
static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
const char * const *name)
{
@@ -466,6 +521,7 @@ static struct scp *init_scp(struct platform_device *pdev,
struct scp_domain *scpd = &scp->domains[i];
struct generic_pm_domain *genpd = &scpd->genpd;
const struct scp_domain_data *data = &scp_domain_data[i];
+ int clk_cnt;
pd_data->domains[i] = genpd;
scpd->scp = scp;
@@ -476,6 +532,18 @@ static struct scp *init_scp(struct platform_device *pdev,
if (ret)
return ERR_PTR(ret);
+ if (data->subsys_clk_prefix) {
+ clk_cnt = init_subsys_clks(pdev,
+ data->subsys_clk_prefix,
+ scpd->subsys_clk);
+ if (clk_cnt < 0) {
+ dev_err(&pdev->dev,
+ "%s: subsys clk unavailable\n",
+ data->name);
+ return ERR_PTR(clk_cnt);
+ }
+ }
+
genpd->name = data->name;
genpd->power_off = scpsys_power_off;
genpd->power_on = scpsys_power_on;
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v10 09/12] soc: mediatek: Add extra sram control
2019-12-18 8:30 [PATCH v10 00/12] Mediatek MT8183 scpsys support Weiyi Lu
` (7 preceding siblings ...)
2019-12-18 8:30 ` [PATCH v10 08/12] soc: mediatek: Add subsys clock control for bus protection Weiyi Lu
@ 2019-12-18 8:30 ` Weiyi Lu
2019-12-19 3:57 ` Nicolas Boichat
2019-12-18 8:30 ` [PATCH v10 10/12] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
` (2 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Weiyi Lu @ 2019-12-18 8:30 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
For some power domains like vpu_core on MT8183 whose sram need to
do clock and internal isolation while power on/off sram.
We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we
need to do the extra sram isolation control or not.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 24 ++++++++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 9f06f17..e010fb3 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -56,6 +56,8 @@
#define PWR_ON_BIT BIT(2)
#define PWR_ON_2ND_BIT BIT(3)
#define PWR_CLK_DIS_BIT BIT(4)
+#define PWR_SRAM_CLKISO_BIT BIT(5)
+#define PWR_SRAM_ISOINT_B_BIT BIT(6)
#define PWR_STATUS_CONN BIT(1)
#define PWR_STATUS_DISP BIT(3)
@@ -86,6 +88,8 @@
* @name: The domain name.
* @sta_mask: The mask for power on/off status bit.
* @ctl_offs: The offset for main power control register.
+ * @sram_iso_ctrl: The flag to judge if the power domain need to do
+ * the extra sram isolation control.
* @sram_pdn_bits: The mask for sram power control bits.
* @sram_pdn_ack_bits: The mask for sram power control acked bits.
* @basic_clk_name: The basic clocks required by this power domain.
@@ -98,6 +102,7 @@ struct scp_domain_data {
const char *name;
u32 sta_mask;
int ctl_offs;
+ bool sram_iso_ctrl;
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
const char *basic_clk_name[MAX_CLKS];
@@ -233,6 +238,14 @@ static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr)
return ret;
}
+ if (scpd->data->sram_iso_ctrl) {
+ val = readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT;
+ writel(val, ctl_addr);
+ udelay(1);
+ val &= ~PWR_SRAM_CLKISO_BIT;
+ writel(val, ctl_addr);
+ }
+
return 0;
}
@@ -242,8 +255,15 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr)
u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
int tmp;
- val = readl(ctl_addr);
- val |= scpd->data->sram_pdn_bits;
+ if (scpd->data->sram_iso_ctrl) {
+ val = readl(ctl_addr) | PWR_SRAM_CLKISO_BIT;
+ writel(val, ctl_addr);
+ val &= ~PWR_SRAM_ISOINT_B_BIT;
+ writel(val, ctl_addr);
+ udelay(1);
+ }
+
+ val = readl(ctl_addr) | scpd->data->sram_pdn_bits;
writel(val, ctl_addr);
/* Either wait until SRAM_PDN_ACK all 1 or 0 */
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v10 10/12] soc: mediatek: Add MT8183 scpsys support
2019-12-18 8:30 [PATCH v10 00/12] Mediatek MT8183 scpsys support Weiyi Lu
` (8 preceding siblings ...)
2019-12-18 8:30 ` [PATCH v10 09/12] soc: mediatek: Add extra sram control Weiyi Lu
@ 2019-12-18 8:30 ` Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 11/12] arm64: dts: Add power controller device node of MT8183 Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 12/12] arm64: dts: Add power-domains properity to mfgcfg Weiyi Lu
11 siblings, 0 replies; 22+ messages in thread
From: Weiyi Lu @ 2019-12-18 8:30 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
Add scpsys driver for MT8183
And minor fix to add a comma at the end
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
---
drivers/soc/mediatek/mtk-scpsys.c | 238 +++++++++++++++++++++++++++++++++++++-
1 file changed, 232 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index e010fb3..0d6ef2c 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -19,6 +19,7 @@
#include <dt-bindings/power/mt7622-power.h>
#include <dt-bindings/power/mt7623a-power.h>
#include <dt-bindings/power/mt8173-power.h>
+#include <dt-bindings/power/mt8183-power.h>
#define MTK_POLL_DELAY_US 10
#define MTK_POLL_TIMEOUT USEC_PER_SEC
@@ -1078,12 +1079,223 @@ static void mtk_register_power_domains(struct platform_device *pdev,
{MT8173_POWER_DOMAIN_MFG_2D, MT8173_POWER_DOMAIN_MFG},
};
+/*
+ * MT8183 power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt8183[] = {
+ [MT8183_POWER_DOMAIN_AUDIO] = {
+ .name = "audio",
+ .sta_mask = PWR_STATUS_AUDIO,
+ .ctl_offs = 0x0314,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .basic_clk_name = {"audio", "audio1", "audio2"},
+ },
+ [MT8183_POWER_DOMAIN_CONN] = {
+ .name = "conn",
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = 0x032c,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ BIT(13) | BIT(14), BIT(13) | BIT(14)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_MFG_ASYNC] = {
+ .name = "mfg_async",
+ .sta_mask = PWR_STATUS_MFG_ASYNC,
+ .ctl_offs = 0x0334,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .basic_clk_name = {"mfg"},
+ },
+ [MT8183_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = 0x0338,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8183_POWER_DOMAIN_MFG_CORE0] = {
+ .name = "mfg_core0",
+ .sta_mask = BIT(7),
+ .ctl_offs = 0x034c,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8183_POWER_DOMAIN_MFG_CORE1] = {
+ .name = "mfg_core1",
+ .sta_mask = BIT(20),
+ .ctl_offs = 0x0310,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8183_POWER_DOMAIN_MFG_2D] = {
+ .name = "mfg_2d",
+ .sta_mask = PWR_STATUS_MFG_2D,
+ .ctl_offs = 0x0348,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258,
+ BIT(19) | BIT(20) | BIT(21),
+ BIT(19) | BIT(20) | BIT(21)),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ BIT(21) | BIT(22), BIT(21) | BIT(22)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_DISP] = {
+ .name = "disp",
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = 0x030c,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .basic_clk_name = {"mm"},
+ .subsys_clk_prefix = "mm",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258,
+ BIT(16) | BIT(17), BIT(16) | BIT(17)),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ BIT(10) | BIT(11), BIT(10) | BIT(11)),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ GENMASK(7, 0), GENMASK(7, 0)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_CAM] = {
+ .name = "cam",
+ .sta_mask = BIT(25),
+ .ctl_offs = 0x0344,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_name = {"cam"},
+ .subsys_clk_prefix = "cam",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ BIT(4) | BIT(5) | BIT(9) | BIT(13),
+ BIT(4) | BIT(5) | BIT(9) | BIT(13)),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ BIT(28), BIT(28)),
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ BIT(11), 0),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ BIT(3) | BIT(4), BIT(3) | BIT(4)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_ISP] = {
+ .name = "isp",
+ .sta_mask = PWR_STATUS_ISP,
+ .ctl_offs = 0x0308,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_name = {"isp"},
+ .subsys_clk_prefix = "isp",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ BIT(3) | BIT(8), BIT(3) | BIT(8)),
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ BIT(10), 0),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ BIT(2), BIT(2)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VDEC] = {
+ .name = "vdec",
+ .sta_mask = BIT(31),
+ .ctl_offs = 0x0300,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_table = {
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ BIT(7), BIT(7)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VENC] = {
+ .name = "venc",
+ .sta_mask = PWR_STATUS_VENC,
+ .ctl_offs = 0x0304,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bp_table = {
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ BIT(1), BIT(1)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VPU_TOP] = {
+ .name = "vpu_top",
+ .sta_mask = BIT(26),
+ .ctl_offs = 0x0324,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .basic_clk_name = {"vpu", "vpu1"},
+ .subsys_clk_prefix = "vpu",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ GENMASK(9, 6) | BIT(12),
+ GENMASK(9, 6) | BIT(12)),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ BIT(27), BIT(27)),
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ BIT(10) | BIT(11), BIT(10) | BIT(11)),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ BIT(5) | BIT(6), BIT(5) | BIT(6)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VPU_CORE0] = {
+ .name = "vpu_core0",
+ .sta_mask = BIT(27),
+ .ctl_offs = 0x33c,
+ .sram_iso_ctrl = true,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_name = {"vpu2"},
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ BIT(6), BIT(6)),
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ BIT(0) | BIT(2) | BIT(4),
+ BIT(0) | BIT(2) | BIT(4)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VPU_CORE1] = {
+ .name = "vpu_core1",
+ .sta_mask = BIT(28),
+ .ctl_offs = 0x0340,
+ .sram_iso_ctrl = true,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_name = {"vpu3"},
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ BIT(7), BIT(7)),
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ BIT(1) | BIT(3) | BIT(5),
+ BIT(1) | BIT(3) | BIT(5)),
+ },
+ },
+};
+
+static const struct scp_subdomain scp_subdomain_mt8183[] = {
+ {MT8183_POWER_DOMAIN_MFG_ASYNC, MT8183_POWER_DOMAIN_MFG},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_2D},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE0},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE1},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_CAM},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_ISP},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VDEC},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VENC},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VPU_TOP},
+ {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE0},
+ {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE1},
+};
+
static const struct scp_soc_data mt2701_data = {
.domains = scp_domain_data_mt2701,
.num_domains = ARRAY_SIZE(scp_domain_data_mt2701),
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS,
- .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
},
};
@@ -1094,7 +1306,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.num_subdomains = ARRAY_SIZE(scp_subdomain_mt2712),
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS,
- .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
},
};
@@ -1105,7 +1317,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.num_subdomains = ARRAY_SIZE(scp_subdomain_mt6797),
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS_MT6797,
- .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797,
},
};
@@ -1114,7 +1326,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.num_domains = ARRAY_SIZE(scp_domain_data_mt7622),
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS,
- .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
},
};
@@ -1123,7 +1335,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.num_domains = ARRAY_SIZE(scp_domain_data_mt7623a),
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS,
- .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
},
};
@@ -1134,10 +1346,21 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.num_subdomains = ARRAY_SIZE(scp_subdomain_mt8173),
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS,
- .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
},
};
+static const struct scp_soc_data mt8183_data = {
+ .domains = scp_domain_data_mt8183,
+ .num_domains = ARRAY_SIZE(scp_domain_data_mt8183),
+ .subdomains = scp_subdomain_mt8183,
+ .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8183),
+ .regs = {
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ }
+};
+
/*
* scpsys driver init
*/
@@ -1162,6 +1385,9 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.compatible = "mediatek,mt8173-scpsys",
.data = &mt8173_data,
}, {
+ .compatible = "mediatek,mt8183-scpsys",
+ .data = &mt8183_data,
+ }, {
/* sentinel */
}
};
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v10 11/12] arm64: dts: Add power controller device node of MT8183
2019-12-18 8:30 [PATCH v10 00/12] Mediatek MT8183 scpsys support Weiyi Lu
` (9 preceding siblings ...)
2019-12-18 8:30 ` [PATCH v10 10/12] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
@ 2019-12-18 8:30 ` Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 12/12] arm64: dts: Add power-domains properity to mfgcfg Weiyi Lu
11 siblings, 0 replies; 22+ messages in thread
From: Weiyi Lu @ 2019-12-18 8:30 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
Add power controller node and smi-common node for MT8183
In scpsys node, it contains clocks and regmapping of
infracfg and smi-common for bus protection.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 62 ++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 10b3247..91217e4f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/mt8183-power.h>
#include "mt8183-pinfunc.h"
/ {
@@ -253,6 +254,62 @@
#interrupt-cells = <2>;
};
+ scpsys: syscon@10006000 {
+ compatible = "mediatek,mt8183-scpsys", "syscon";
+ #power-domain-cells = <1>;
+ reg = <0 0x10006000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
+ <&infracfg CLK_INFRA_AUDIO>,
+ <&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
+ <&topckgen CLK_TOP_MUX_MFG>,
+ <&topckgen CLK_TOP_MUX_MM>,
+ <&topckgen CLK_TOP_MUX_CAM>,
+ <&topckgen CLK_TOP_MUX_IMG>,
+ <&topckgen CLK_TOP_MUX_IPU_IF>,
+ <&topckgen CLK_TOP_MUX_DSP>,
+ <&topckgen CLK_TOP_MUX_DSP1>,
+ <&topckgen CLK_TOP_MUX_DSP2>,
+ <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB1>,
+ <&mmsys CLK_MM_GALS_COMM0>,
+ <&mmsys CLK_MM_GALS_COMM1>,
+ <&mmsys CLK_MM_GALS_CCU2MM>,
+ <&mmsys CLK_MM_GALS_IPU12MM>,
+ <&mmsys CLK_MM_GALS_IMG2MM>,
+ <&mmsys CLK_MM_GALS_CAM2MM>,
+ <&mmsys CLK_MM_GALS_IPU2MM>,
+ <&imgsys CLK_IMG_LARB5>,
+ <&imgsys CLK_IMG_LARB2>,
+ <&camsys CLK_CAM_LARB6>,
+ <&camsys CLK_CAM_LARB3>,
+ <&camsys CLK_CAM_SENINF>,
+ <&camsys CLK_CAM_CAMSV0>,
+ <&camsys CLK_CAM_CAMSV1>,
+ <&camsys CLK_CAM_CAMSV2>,
+ <&camsys CLK_CAM_CCU>,
+ <&ipu_conn CLK_IPU_CONN_IPU>,
+ <&ipu_conn CLK_IPU_CONN_AHB>,
+ <&ipu_conn CLK_IPU_CONN_AXI>,
+ <&ipu_conn CLK_IPU_CONN_ISP>,
+ <&ipu_conn CLK_IPU_CONN_CAM_ADL>,
+ <&ipu_conn CLK_IPU_CONN_IMG_ADL>;
+ clock-names = "audio", "audio1", "audio2",
+ "mfg", "mm", "cam",
+ "isp", "vpu", "vpu1",
+ "vpu2", "vpu3", "mm-0",
+ "mm-1", "mm-2", "mm-3",
+ "mm-4", "mm-5", "mm-6",
+ "mm-7", "mm-8", "mm-9",
+ "isp-0", "isp-1", "cam-0",
+ "cam-1", "cam-2", "cam-3",
+ "cam-4", "cam-5", "cam-6",
+ "vpu-0", "vpu-1", "vpu-2",
+ "vpu-3", "vpu-4", "vpu-5";
+ infracfg = <&infracfg>;
+ smi_comm = <&smi_common>;
+ };
+
apmixedsys: syscon@1000c000 {
compatible = "mediatek,mt8183-apmixedsys", "syscon";
reg = <0 0x1000c000 0 0x1000>;
@@ -594,6 +651,11 @@
#clock-cells = <1>;
};
+ smi_common: smi@14019000 {
+ compatible = "mediatek,mt8183-smi-common", "syscon";
+ reg = <0 0x14019000 0 0x1000>;
+ };
+
imgsys: syscon@15020000 {
compatible = "mediatek,mt8183-imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v10 12/12] arm64: dts: Add power-domains properity to mfgcfg
2019-12-18 8:30 [PATCH v10 00/12] Mediatek MT8183 scpsys support Weiyi Lu
` (10 preceding siblings ...)
2019-12-18 8:30 ` [PATCH v10 11/12] arm64: dts: Add power controller device node of MT8183 Weiyi Lu
@ 2019-12-18 8:30 ` Weiyi Lu
11 siblings, 0 replies; 22+ messages in thread
From: Weiyi Lu @ 2019-12-18 8:30 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, Weiyi Lu
mfgcfg clock is under MFG_ASYNC power domain
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 91217e4f..40145dc 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -643,6 +643,7 @@
compatible = "mediatek,mt8183-mfgcfg", "syscon";
reg = <0 0x13000000 0 0x1000>;
#clock-cells = <1>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_ASYNC>;
};
mmsys: syscon@14000000 {
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v10 04/12] soc: mediatek: Use basic_clk_name for all compatibles
2019-12-18 8:30 ` [PATCH v10 04/12] soc: mediatek: Use basic_clk_name for all compatibles Weiyi Lu
@ 2019-12-19 3:48 ` Nicolas Boichat
2019-12-20 3:29 ` Weiyi Lu
0 siblings, 1 reply; 22+ messages in thread
From: Nicolas Boichat @ 2019-12-19 3:48 UTC (permalink / raw)
To: Weiyi Lu
Cc: Matthias Brugger, Rob Herring, Sascha Hauer, James Liao,
Fan Chen, linux-arm Mailing List, lkml,
moderated list:ARM/Mediatek SoC support, srv_heupstream
On Wed, Dec 18, 2019 at 4:31 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
>
> Use basic_clk_name strings for all compatibles, instead of
> mixing clk_id and clk_name.
This looks good, but I'd just squash it into 03/16 of the series.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 149 +++++++++++---------------------------
> 1 file changed, 44 insertions(+), 105 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> index 9343277..db35a28 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -78,34 +78,6 @@
> #define PWR_STATUS_HIF1 BIT(26) /* MT7622 */
> #define PWR_STATUS_WB BIT(27) /* MT7622 */
>
> -enum clk_id {
> - CLK_NONE,
> - CLK_MM,
> - CLK_MFG,
> - CLK_VENC,
> - CLK_VENC_LT,
> - CLK_ETHIF,
> - CLK_VDEC,
> - CLK_HIFSEL,
> - CLK_JPGDEC,
> - CLK_AUDIO,
> - CLK_MAX,
> -};
> -
> -static const char * const clk_names[] = {
> - NULL,
> - "mm",
> - "mfg",
> - "venc",
> - "venc_lt",
> - "ethif",
> - "vdec",
> - "hif_sel",
> - "jpgdec",
> - "audio",
> - NULL,
> -};
> -
> #define MAX_CLKS 3
>
> /**
> @@ -116,9 +88,7 @@ enum clk_id {
> * @sram_pdn_bits: The mask for sram power control bits.
> * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> * @bus_prot_mask: The mask for single step bus protection.
> - * @clk_id: The basic clocks required by this power domain.
> - * @basic_clk_name: provide the same purpose with field "clk_id"
> - * by declaring basic clock prefix name rather than clk_id.
> + * @basic_clk_name: The basic clocks required by this power domain.
> * @caps: The flag for active wake-up action.
> */
> struct scp_domain_data {
> @@ -128,7 +98,6 @@ struct scp_domain_data {
> u32 sram_pdn_bits;
> u32 sram_pdn_ack_bits;
> u32 bus_prot_mask;
> - enum clk_id clk_id[MAX_CLKS];
> const char *basic_clk_name[MAX_CLKS];
> u8 caps;
> };
> @@ -414,12 +383,23 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> return ret;
> }
>
> -static void init_clks(struct platform_device *pdev, struct clk **clk)
> +static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
> + const char * const *name)
> {
> int i;
>
> - for (i = CLK_NONE + 1; i < CLK_MAX; i++)
> - clk[i] = devm_clk_get(&pdev->dev, clk_names[i]);
> + for (i = 0; i < MAX_CLKS && name[i]; i++) {
> + clk[i] = devm_clk_get(&pdev->dev, name[i]);
> +
> + if (IS_ERR(clk[i])) {
> + dev_err(&pdev->dev,
> + "get basic clk %s fail %ld\n",
> + name[i], PTR_ERR(clk[i]));
> + return PTR_ERR(clk[i]);
> + }
> + }
> +
> + return 0;
> }
>
> static struct scp *init_scp(struct platform_device *pdev,
> @@ -429,9 +409,8 @@ static struct scp *init_scp(struct platform_device *pdev,
> {
> struct genpd_onecell_data *pd_data;
> struct resource *res;
> - int i, j;
> + int i, ret;
> struct scp *scp;
> - struct clk *clk[CLK_MAX];
>
> scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
> if (!scp)
> @@ -484,8 +463,6 @@ static struct scp *init_scp(struct platform_device *pdev,
>
> pd_data->num_domains = num;
>
> - init_clks(pdev, clk);
> -
> for (i = 0; i < num; i++) {
> struct scp_domain *scpd = &scp->domains[i];
> struct generic_pm_domain *genpd = &scpd->genpd;
> @@ -496,27 +473,9 @@ static struct scp *init_scp(struct platform_device *pdev,
>
> scpd->data = data;
>
> - if (data->clk_id[0]) {
> - WARN_ON(data->basic_clk_name[0]);
> -
> - for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
> - struct clk *c = clk[data->clk_id[j]];
> -
> - if (IS_ERR(c)) {
> - dev_err(&pdev->dev,
> - "%s: clk unavailable\n",
> - data->name);
> - return ERR_CAST(c);
> - }
> -
> - scpd->clk[j] = c;
> - }
> - } else if (data->basic_clk_name[0]) {
> - for (j = 0; j < MAX_CLKS &&
> - data->basic_clk_name[j]; j++)
> - scpd->clk[j] = devm_clk_get(&pdev->dev,
> - data->basic_clk_name[j]);
> - }
> + ret = init_basic_clks(pdev, scpd->clk, data->basic_clk_name);
> + if (ret)
> + return ERR_PTR(ret);
>
> genpd->name = data->name;
> genpd->power_off = scpsys_power_off;
> @@ -573,7 +532,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_CONN_PWR_CON,
> .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
> MT2701_TOP_AXI_PROT_EN_CONN_S,
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2701_POWER_DOMAIN_DISP] = {
> @@ -581,7 +539,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .sta_mask = PWR_STATUS_DISP,
> .ctl_offs = SPM_DIS_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> - .clk_id = {CLK_MM},
> + .basic_clk_name = {"mm"},
> .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0,
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> @@ -591,7 +549,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_MFG_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> - .clk_id = {CLK_MFG},
> + .basic_clk_name = {"mfg"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2701_POWER_DOMAIN_VDEC] = {
> @@ -600,7 +558,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_VDE_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> - .clk_id = {CLK_MM},
> + .basic_clk_name = {"mm"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2701_POWER_DOMAIN_ISP] = {
> @@ -609,7 +567,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_ISP_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(13, 12),
> - .clk_id = {CLK_MM},
> + .basic_clk_name = {"mm"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2701_POWER_DOMAIN_BDP] = {
> @@ -617,7 +575,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .sta_mask = PWR_STATUS_BDP,
> .ctl_offs = SPM_BDP_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2701_POWER_DOMAIN_ETH] = {
> @@ -626,7 +583,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_ETH_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_ETHIF},
> + .basic_clk_name = {"ethif"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2701_POWER_DOMAIN_HIF] = {
> @@ -635,14 +592,13 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_HIF_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_ETHIF},
> + .basic_clk_name = {"ethif"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2701_POWER_DOMAIN_IFR_MSC] = {
> .name = "ifr_msc",
> .sta_mask = PWR_STATUS_IFR_MSC,
> .ctl_offs = SPM_IFR_MSC_PWR_CON,
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> };
> @@ -657,7 +613,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_DIS_PWR_CON,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> - .clk_id = {CLK_MM},
> + .basic_clk_name = {"mm"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2712_POWER_DOMAIN_VDEC] = {
> @@ -666,7 +622,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_VDE_PWR_CON,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> - .clk_id = {CLK_MM, CLK_VDEC},
> + .basic_clk_name = {"mm", "vdec"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2712_POWER_DOMAIN_VENC] = {
> @@ -675,7 +631,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_VEN_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_MM, CLK_VENC, CLK_JPGDEC},
> + .basic_clk_name = {"mm", "venc", "jpgdec"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2712_POWER_DOMAIN_ISP] = {
> @@ -684,7 +640,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_ISP_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(13, 12),
> - .clk_id = {CLK_MM},
> + .basic_clk_name = {"mm"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2712_POWER_DOMAIN_AUDIO] = {
> @@ -693,7 +649,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_AUDIO_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_AUDIO},
> + .basic_clk_name = {"audio"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2712_POWER_DOMAIN_USB] = {
> @@ -702,7 +658,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_USB_PWR_CON,
> .sram_pdn_bits = GENMASK(10, 8),
> .sram_pdn_ack_bits = GENMASK(14, 12),
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2712_POWER_DOMAIN_USB2] = {
> @@ -711,7 +666,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_USB2_PWR_CON,
> .sram_pdn_bits = GENMASK(10, 8),
> .sram_pdn_ack_bits = GENMASK(14, 12),
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2712_POWER_DOMAIN_MFG] = {
> @@ -720,7 +674,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_MFG_PWR_CON,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(16, 16),
> - .clk_id = {CLK_MFG},
> + .basic_clk_name = {"mfg"},
> .bus_prot_mask = BIT(14) | BIT(21) | BIT(23),
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> @@ -730,7 +684,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x02c0,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(16, 16),
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2712_POWER_DOMAIN_MFG_SC2] = {
> @@ -739,7 +692,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x02c4,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(16, 16),
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT2712_POWER_DOMAIN_MFG_SC3] = {
> @@ -748,7 +700,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x01f8,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(16, 16),
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> };
> @@ -773,7 +724,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x300,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> - .clk_id = {CLK_VDEC},
> + .basic_clk_name = {"vdec"},
> },
> [MT6797_POWER_DOMAIN_VENC] = {
> .name = "venc",
> @@ -781,7 +732,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x304,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_NONE},
> },
> [MT6797_POWER_DOMAIN_ISP] = {
> .name = "isp",
> @@ -789,7 +739,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x308,
> .sram_pdn_bits = GENMASK(9, 8),
> .sram_pdn_ack_bits = GENMASK(13, 12),
> - .clk_id = {CLK_NONE},
> },
> [MT6797_POWER_DOMAIN_MM] = {
> .name = "mm",
> @@ -797,7 +746,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x30C,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> - .clk_id = {CLK_MM},
> + .basic_clk_name = {"mm"},
> .bus_prot_mask = (BIT(1) | BIT(2)),
> },
> [MT6797_POWER_DOMAIN_AUDIO] = {
> @@ -806,7 +755,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x314,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_NONE},
> },
> [MT6797_POWER_DOMAIN_MFG_ASYNC] = {
> .name = "mfg_async",
> @@ -814,7 +762,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x334,
> .sram_pdn_bits = 0,
> .sram_pdn_ack_bits = 0,
> - .clk_id = {CLK_MFG},
> + .basic_clk_name = {"mfg"},
> },
> [MT6797_POWER_DOMAIN_MJC] = {
> .name = "mjc",
> @@ -822,7 +770,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = 0x310,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> - .clk_id = {CLK_NONE},
> },
> };
>
> @@ -847,7 +794,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_ETHSYS_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_NONE},
> .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS,
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> @@ -857,7 +803,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_HIF0_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_HIFSEL},
> + .basic_clk_name = {"hif_sel"},
> .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0,
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> @@ -867,7 +813,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_HIF1_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_HIFSEL},
> + .basic_clk_name = {"hif_sel"},
> .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1,
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> @@ -877,7 +823,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_WB_PWR_CON,
> .sram_pdn_bits = 0,
> .sram_pdn_ack_bits = 0,
> - .clk_id = {CLK_NONE},
> .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
> .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM,
> },
> @@ -894,7 +839,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_CONN_PWR_CON,
> .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
> MT2701_TOP_AXI_PROT_EN_CONN_S,
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT7623A_POWER_DOMAIN_ETH] = {
> @@ -903,7 +847,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_ETH_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_ETHIF},
> + .basic_clk_name = {"ethif"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT7623A_POWER_DOMAIN_HIF] = {
> @@ -912,14 +856,13 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_HIF_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_ETHIF},
> + .basic_clk_name = {"ethif"},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT7623A_POWER_DOMAIN_IFR_MSC] = {
> .name = "ifr_msc",
> .sta_mask = PWR_STATUS_IFR_MSC,
> .ctl_offs = SPM_IFR_MSC_PWR_CON,
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> };
> @@ -935,7 +878,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_VDE_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> - .clk_id = {CLK_MM},
> + .basic_clk_name = {"mm"},
> },
> [MT8173_POWER_DOMAIN_VENC] = {
> .name = "venc",
> @@ -943,7 +886,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_VEN_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_MM, CLK_VENC},
> + .basic_clk_name = {"mm", "venc"},
> },
> [MT8173_POWER_DOMAIN_ISP] = {
> .name = "isp",
> @@ -951,7 +894,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_ISP_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(13, 12),
> - .clk_id = {CLK_MM},
> + .basic_clk_name = {"mm"},
> },
> [MT8173_POWER_DOMAIN_MM] = {
> .name = "mm",
> @@ -959,7 +902,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_DIS_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> - .clk_id = {CLK_MM},
> + .basic_clk_name = {"mm"},
> .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
> MT8173_TOP_AXI_PROT_EN_MM_M1,
> },
> @@ -969,7 +912,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_VEN2_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_MM, CLK_VENC_LT},
> + .basic_clk_name = {"mm", "venc_lt"},
> },
> [MT8173_POWER_DOMAIN_AUDIO] = {
> .name = "audio",
> @@ -977,7 +920,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_AUDIO_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_NONE},
> },
> [MT8173_POWER_DOMAIN_USB] = {
> .name = "usb",
> @@ -985,7 +927,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_USB_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> - .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
> @@ -994,7 +935,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = 0,
> - .clk_id = {CLK_MFG},
> + .basic_clk_name = {"mfg"},
> },
> [MT8173_POWER_DOMAIN_MFG_2D] = {
> .name = "mfg_2d",
> @@ -1002,7 +943,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_MFG_2D_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(13, 12),
> - .clk_id = {CLK_NONE},
> },
> [MT8173_POWER_DOMAIN_MFG] = {
> .name = "mfg",
> @@ -1010,7 +950,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .ctl_offs = SPM_MFG_PWR_CON,
> .sram_pdn_bits = GENMASK(13, 8),
> .sram_pdn_ack_bits = GENMASK(21, 16),
> - .clk_id = {CLK_NONE},
> .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
> MT8173_TOP_AXI_PROT_EN_MFG_M0 |
> MT8173_TOP_AXI_PROT_EN_MFG_M1 |
> --
> 1.8.1.1.dirty
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v10 05/12] soc: mediatek: Add multiple step bus protection control
2019-12-18 8:30 ` [PATCH v10 05/12] soc: mediatek: Add multiple step bus protection control Weiyi Lu
@ 2019-12-19 3:51 ` Nicolas Boichat
2019-12-20 3:30 ` Weiyi Lu
0 siblings, 1 reply; 22+ messages in thread
From: Nicolas Boichat @ 2019-12-19 3:51 UTC (permalink / raw)
To: Weiyi Lu
Cc: Matthias Brugger, Rob Herring, Sascha Hauer, James Liao,
Fan Chen, linux-arm Mailing List, lkml,
moderated list:ARM/Mediatek SoC support, srv_heupstream
On Wed, Dec 18, 2019 at 4:31 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
>
> Both MT8183 & MT6765 have more control steps of bus protection
> than previous project. And there add more bus protection registers
> reside at infracfg & smi-common. Also add new APIs for multiple
> step bus protection control with more customized arguments.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
...
> diff --git a/include/linux/soc/mediatek/scpsys-ext.h b/include/linux/soc/mediatek/scpsys-ext.h
Will this include file be used by anything other than
drivers/soc/mediatek/scpsys*.c? If so I think you should keep it in
drivers/soc/mediatek/ instead.
I also still had a comment in v9 about clr_mask, otherwise this looks ok.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v10 06/12] soc: mediatek: Use bp_table for all compatibles
2019-12-18 8:30 ` [PATCH v10 06/12] soc: mediatek: Use bp_table for all compatibles Weiyi Lu
@ 2019-12-19 3:54 ` Nicolas Boichat
2019-12-20 3:30 ` Weiyi Lu
0 siblings, 1 reply; 22+ messages in thread
From: Nicolas Boichat @ 2019-12-19 3:54 UTC (permalink / raw)
To: Weiyi Lu
Cc: Matthias Brugger, Rob Herring, Sascha Hauer, James Liao,
Fan Chen, linux-arm Mailing List, lkml,
moderated list:ARM/Mediatek SoC support, srv_heupstream
On Wed, Dec 18, 2019 at 4:31 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
>
> Only use bp_table for bus protection of all compatibles,
> instead of mixing bus_prot_mask and bus_prot_reg_update.
ditto, I'd just squash in the previous patch.
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 94 ++++++++++++++++++++-------------------
> 1 file changed, 48 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> index 5699d9f..c438c53 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -11,7 +11,6 @@
> #include <linux/platform_device.h>
> #include <linux/pm_domain.h>
> #include <linux/regulator/consumer.h>
> -#include <linux/soc/mediatek/infracfg.h>
> #include <linux/soc/mediatek/scpsys-ext.h>
>
> #include <dt-bindings/power/mt2701-power.h>
> @@ -88,7 +87,6 @@
> * @ctl_offs: The offset for main power control register.
> * @sram_pdn_bits: The mask for sram power control bits.
> * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> - * @bus_prot_mask: The mask for single step bus protection.
> * @basic_clk_name: The basic clocks required by this power domain.
> * @caps: The flag for active wake-up action.
> * @bp_table: The mask table for multiple step bus protection.
> @@ -99,7 +97,6 @@ struct scp_domain_data {
> int ctl_offs;
> u32 sram_pdn_bits;
> u32 sram_pdn_ack_bits;
> - u32 bus_prot_mask;
> const char *basic_clk_name[MAX_CLKS];
> u8 caps;
> struct bus_prot bp_table[MAX_STEPS];
> @@ -128,7 +125,6 @@ struct scp {
> struct regmap *infracfg;
> struct regmap *smi_common;
> struct scp_ctrl_reg ctrl_reg;
> - bool bus_prot_reg_update;
> };
>
> struct scp_subdomain {
> @@ -142,7 +138,6 @@ struct scp_soc_data {
> const struct scp_subdomain *subdomains;
> int num_subdomains;
> const struct scp_ctrl_reg regs;
> - bool bus_prot_reg_update;
> };
>
> static int scpsys_domain_is_on(struct scp_domain *scpd)
> @@ -256,12 +251,6 @@ static int scpsys_bus_protect_enable(struct scp_domain *scpd)
> {
> struct scp *scp = scpd->scp;
>
> - if (scpd->data->bus_prot_mask) {
> - return mtk_infracfg_set_bus_protection(scp->infracfg,
> - scpd->data->bus_prot_mask,
> - scp->bus_prot_reg_update);
> - }
> -
> return mtk_scpsys_ext_set_bus_protection(scpd->data->bp_table,
> scp->infracfg, scp->smi_common);
> }
> @@ -270,12 +259,6 @@ static int scpsys_bus_protect_disable(struct scp_domain *scpd)
> {
> struct scp *scp = scpd->scp;
>
> - if (scpd->data->bus_prot_mask) {
> - return mtk_infracfg_clear_bus_protection(scp->infracfg,
> - scpd->data->bus_prot_mask,
> - scp->bus_prot_reg_update);
> - }
> -
> return mtk_scpsys_ext_clear_bus_protection(scpd->data->bp_table,
> scp->infracfg, scp->smi_common);
> }
> @@ -412,8 +395,7 @@ static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
>
> static struct scp *init_scp(struct platform_device *pdev,
> const struct scp_domain_data *scp_domain_data, int num,
> - const struct scp_ctrl_reg *scp_ctrl_reg,
> - bool bus_prot_reg_update)
> + const struct scp_ctrl_reg *scp_ctrl_reg)
> {
> struct genpd_onecell_data *pd_data;
> struct resource *res;
> @@ -427,8 +409,6 @@ static struct scp *init_scp(struct platform_device *pdev,
> scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs;
> scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs;
>
> - scp->bus_prot_reg_update = bus_prot_reg_update;
> -
> scp->dev = &pdev->dev;
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> @@ -549,8 +529,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> .name = "conn",
> .sta_mask = PWR_STATUS_CONN,
> .ctl_offs = SPM_CONN_PWR_CON,
> - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
> - MT2701_TOP_AXI_PROT_EN_CONN_S,
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> + BIT(2) | BIT(8), BIT(2) | BIT(8)),
> + },
I'm a bit sad we lose the information about the BIT meaning.
Of course this looks ugly and verbose:
BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
MT2701_TOP_AXI_PROT_EN_CONN_M |
MT2701_TOP_AXI_PROT_EN_CONN_S,
MT2701_TOP_AXI_PROT_EN_CONN_M |
MT2701_TOP_AXI_PROT_EN_CONN_S),
But if you make "check_clr_mask" a boolean, you wouldn't have to
repeat the mask twice and you could keep the nice register bit
definitions.
[snip, many similar occurences below]
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v10 07/12] soc: mediatek: Remove infracfg misc driver support
2019-12-18 8:30 ` [PATCH v10 07/12] soc: mediatek: Remove infracfg misc driver support Weiyi Lu
@ 2019-12-19 3:56 ` Nicolas Boichat
2019-12-20 3:31 ` Weiyi Lu
0 siblings, 1 reply; 22+ messages in thread
From: Nicolas Boichat @ 2019-12-19 3:56 UTC (permalink / raw)
To: Weiyi Lu
Cc: Matthias Brugger, Rob Herring, Sascha Hauer, James Liao,
Fan Chen, linux-arm Mailing List, lkml,
moderated list:ARM/Mediatek SoC support, srv_heupstream
On Wed, Dec 18, 2019 at 4:31 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
>
> In previous patches, we introduce scpsys-ext driver that covers
> the functions which infracfg misc driver provided.
> And then replace bus_prot_mask with bp_table of all compatibles.
> Now, we're going to remove infracfg misc drvier which is no longer
> being used.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
> drivers/soc/mediatek/Kconfig | 10 -----
> drivers/soc/mediatek/Makefile | 3 +-
> drivers/soc/mediatek/mtk-infracfg.c | 79 -----------------------------------
> include/linux/soc/mediatek/infracfg.h | 39 -----------------
> 4 files changed, 1 insertion(+), 130 deletions(-)
> delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c
> delete mode 100644 include/linux/soc/mediatek/infracfg.h
>
> diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> index 2114b56..f837b3c 100644
> --- a/drivers/soc/mediatek/Kconfig
> +++ b/drivers/soc/mediatek/Kconfig
> @@ -10,21 +10,12 @@ config MTK_CMDQ
> depends on ARCH_MEDIATEK || COMPILE_TEST
> select MAILBOX
> select MTK_CMDQ_MBOX
> - select MTK_INFRACFG
> help
> Say yes here to add support for the MediaTek Command Queue (CMDQ)
> driver. The CMDQ is used to help read/write registers with critical
> time limitation, such as updating display configuration during the
> vblank.
>
> -config MTK_INFRACFG
> - bool "MediaTek INFRACFG Support"
> - select REGMAP
> - help
> - Say yes here to add support for the MediaTek INFRACFG controller. The
> - INFRACFG controller contains various infrastructure registers not
> - directly associated to any device.
> -
> config MTK_PMIC_WRAP
> tristate "MediaTek PMIC Wrapper Support"
> depends on RESET_CONTROLLER
> @@ -38,7 +29,6 @@ config MTK_SCPSYS
> bool "MediaTek SCPSYS Support"
> default ARCH_MEDIATEK
> select REGMAP
> - select MTK_INFRACFG
> select PM_GENERIC_DOMAINS if PM
> help
> Say yes here to add support for the MediaTek SCPSYS power domain
> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> index b442be9..7bf7e88 100644
> --- a/drivers/soc/mediatek/Makefile
> +++ b/drivers/soc/mediatek/Makefile
> @@ -1,5 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0-only
> obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
> -obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
> obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> -obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> +obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o mtk-scpsys-ext.o
> diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c
> deleted file mode 100644
> index 341c7ac..0000000
> --- a/drivers/soc/mediatek/mtk-infracfg.c
> +++ /dev/null
> @@ -1,79 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
> - */
> -
> -#include <linux/export.h>
> -#include <linux/jiffies.h>
> -#include <linux/regmap.h>
> -#include <linux/soc/mediatek/infracfg.h>
> -#include <asm/processor.h>
> -
> -#define MTK_POLL_DELAY_US 10
> -#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ))
> -
> -#define INFRA_TOPAXI_PROTECTEN 0x0220
> -#define INFRA_TOPAXI_PROTECTSTA1 0x0228
> -#define INFRA_TOPAXI_PROTECTEN_SET 0x0260
> -#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264
> -
> -/**
> - * mtk_infracfg_set_bus_protection - enable bus protection
> - * @regmap: The infracfg regmap
> - * @mask: The mask containing the protection bits to be enabled.
> - * @reg_update: The boolean flag determines to set the protection bits
> - * by regmap_update_bits with enable register(PROTECTEN) or
> - * by regmap_write with set register(PROTECTEN_SET).
> - *
> - * This function enables the bus protection bits for disabled power
> - * domains so that the system does not hang when some unit accesses the
> - * bus while in power down.
> - */
> -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
> - bool reg_update)
> -{
> - u32 val;
> - int ret;
> -
> - if (reg_update)
> - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask,
> - mask);
> - else
> - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask);
> -
> - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
> - val, (val & mask) == mask,
> - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> -
> - return ret;
> -}
> -
> -/**
> - * mtk_infracfg_clear_bus_protection - disable bus protection
> - * @regmap: The infracfg regmap
> - * @mask: The mask containing the protection bits to be disabled.
> - * @reg_update: The boolean flag determines to clear the protection bits
> - * by regmap_update_bits with enable register(PROTECTEN) or
> - * by regmap_write with clear register(PROTECTEN_CLR).
> - *
> - * This function disables the bus protection bits previously enabled with
> - * mtk_infracfg_set_bus_protection.
> - */
> -
> -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
> - bool reg_update)
> -{
> - int ret;
> - u32 val;
> -
> - if (reg_update)
> - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0);
> - else
> - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask);
> -
> - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
> - val, !(val & mask),
> - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> -
> - return ret;
> -}
> diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
> deleted file mode 100644
> index fd25f01..0000000
> --- a/include/linux/soc/mediatek/infracfg.h
> +++ /dev/null
> @@ -1,39 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -#ifndef __SOC_MEDIATEK_INFRACFG_H
> -#define __SOC_MEDIATEK_INFRACFG_H
> -
> -#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0)
> -#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
> -#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
> -#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6)
> -#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9)
> -#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11)
> -#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12)
> -#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13)
> -#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
> -#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15)
> -#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16)
> -#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17)
> -#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18)
> -#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19)
> -#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20)
> -#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
> -#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
> -#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
> -
> -#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
> -#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
> -#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)
> -
> -#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17))
> -#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25))
> -#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \
> - BIT(28))
> -#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
> - BIT(7) | BIT(8))
It was really nice to have these all defined, can we move those to
scpsys-ext.h? (and do the same for MT8183?)
> -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
> - bool reg_update);
> -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
> - bool reg_update);
> -#endif /* __SOC_MEDIATEK_INFRACFG_H */
> --
> 1.8.1.1.dirty
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v10 09/12] soc: mediatek: Add extra sram control
2019-12-18 8:30 ` [PATCH v10 09/12] soc: mediatek: Add extra sram control Weiyi Lu
@ 2019-12-19 3:57 ` Nicolas Boichat
0 siblings, 0 replies; 22+ messages in thread
From: Nicolas Boichat @ 2019-12-19 3:57 UTC (permalink / raw)
To: Weiyi Lu
Cc: Matthias Brugger, Rob Herring, Sascha Hauer, James Liao,
Fan Chen, linux-arm Mailing List, lkml,
moderated list:ARM/Mediatek SoC support, srv_heupstream
On Wed, Dec 18, 2019 at 4:31 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
>
> For some power domains like vpu_core on MT8183 whose sram need to
> do clock and internal isolation while power on/off sram.
> We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we
> need to do the extra sram isolation control or not.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 24 ++++++++++++++++++++++--
> 1 file changed, 22 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> index 9f06f17..e010fb3 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -56,6 +56,8 @@
> #define PWR_ON_BIT BIT(2)
> #define PWR_ON_2ND_BIT BIT(3)
> #define PWR_CLK_DIS_BIT BIT(4)
> +#define PWR_SRAM_CLKISO_BIT BIT(5)
> +#define PWR_SRAM_ISOINT_B_BIT BIT(6)
>
> #define PWR_STATUS_CONN BIT(1)
> #define PWR_STATUS_DISP BIT(3)
> @@ -86,6 +88,8 @@
> * @name: The domain name.
> * @sta_mask: The mask for power on/off status bit.
> * @ctl_offs: The offset for main power control register.
> + * @sram_iso_ctrl: The flag to judge if the power domain need to do
> + * the extra sram isolation control.
> * @sram_pdn_bits: The mask for sram power control bits.
> * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> * @basic_clk_name: The basic clocks required by this power domain.
> @@ -98,6 +102,7 @@ struct scp_domain_data {
> const char *name;
> u32 sta_mask;
> int ctl_offs;
> + bool sram_iso_ctrl;
> u32 sram_pdn_bits;
> u32 sram_pdn_ack_bits;
> const char *basic_clk_name[MAX_CLKS];
> @@ -233,6 +238,14 @@ static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr)
> return ret;
> }
>
> + if (scpd->data->sram_iso_ctrl) {
> + val = readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT;
> + writel(val, ctl_addr);
> + udelay(1);
> + val &= ~PWR_SRAM_CLKISO_BIT;
> + writel(val, ctl_addr);
> + }
> +
> return 0;
> }
>
> @@ -242,8 +255,15 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr)
> u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
> int tmp;
>
> - val = readl(ctl_addr);
> - val |= scpd->data->sram_pdn_bits;
> + if (scpd->data->sram_iso_ctrl) {
> + val = readl(ctl_addr) | PWR_SRAM_CLKISO_BIT;
> + writel(val, ctl_addr);
> + val &= ~PWR_SRAM_ISOINT_B_BIT;
> + writel(val, ctl_addr);
> + udelay(1);
> + }
> +
> + val = readl(ctl_addr) | scpd->data->sram_pdn_bits;
> writel(val, ctl_addr);
>
> /* Either wait until SRAM_PDN_ACK all 1 or 0 */
> --
> 1.8.1.1.dirty
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v10 04/12] soc: mediatek: Use basic_clk_name for all compatibles
2019-12-19 3:48 ` Nicolas Boichat
@ 2019-12-20 3:29 ` Weiyi Lu
0 siblings, 0 replies; 22+ messages in thread
From: Weiyi Lu @ 2019-12-20 3:29 UTC (permalink / raw)
To: Nicolas Boichat
Cc: Rob Herring, srv_heupstream, James Liao, lkml, Fan Chen,
moderated list:ARM/Mediatek SoC support, Sascha Hauer,
Matthias Brugger, linux-arm Mailing List
On Thu, 2019-12-19 at 11:48 +0800, Nicolas Boichat wrote:
> On Wed, Dec 18, 2019 at 4:31 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
> >
> > Use basic_clk_name strings for all compatibles, instead of
> > mixing clk_id and clk_name.
>
> This looks good, but I'd just squash it into 03/16 of the series.
>
OK, will update in next version.
> >
> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > ---
> > drivers/soc/mediatek/mtk-scpsys.c | 149 +++++++++++---------------------------
> > 1 file changed, 44 insertions(+), 105 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> > index 9343277..db35a28 100644
> > --- a/drivers/soc/mediatek/mtk-scpsys.c
> > +++ b/drivers/soc/mediatek/mtk-scpsys.c
> > @@ -78,34 +78,6 @@
> > #define PWR_STATUS_HIF1 BIT(26) /* MT7622 */
> > #define PWR_STATUS_WB BIT(27) /* MT7622 */
> >
> > -enum clk_id {
> > - CLK_NONE,
> > - CLK_MM,
> > - CLK_MFG,
> > - CLK_VENC,
> > - CLK_VENC_LT,
> > - CLK_ETHIF,
> > - CLK_VDEC,
> > - CLK_HIFSEL,
> > - CLK_JPGDEC,
> > - CLK_AUDIO,
> > - CLK_MAX,
> > -};
> > -
> > -static const char * const clk_names[] = {
> > - NULL,
> > - "mm",
> > - "mfg",
> > - "venc",
> > - "venc_lt",
> > - "ethif",
> > - "vdec",
> > - "hif_sel",
> > - "jpgdec",
> > - "audio",
> > - NULL,
> > -};
> > -
> > #define MAX_CLKS 3
> >
> > /**
> > @@ -116,9 +88,7 @@ enum clk_id {
> > * @sram_pdn_bits: The mask for sram power control bits.
> > * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> > * @bus_prot_mask: The mask for single step bus protection.
> > - * @clk_id: The basic clocks required by this power domain.
> > - * @basic_clk_name: provide the same purpose with field "clk_id"
> > - * by declaring basic clock prefix name rather than clk_id.
> > + * @basic_clk_name: The basic clocks required by this power domain.
> > * @caps: The flag for active wake-up action.
> > */
> > struct scp_domain_data {
> > @@ -128,7 +98,6 @@ struct scp_domain_data {
> > u32 sram_pdn_bits;
> > u32 sram_pdn_ack_bits;
> > u32 bus_prot_mask;
> > - enum clk_id clk_id[MAX_CLKS];
> > const char *basic_clk_name[MAX_CLKS];
> > u8 caps;
> > };
> > @@ -414,12 +383,23 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> > return ret;
> > }
> >
> > -static void init_clks(struct platform_device *pdev, struct clk **clk)
> > +static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
> > + const char * const *name)
> > {
> > int i;
> >
> > - for (i = CLK_NONE + 1; i < CLK_MAX; i++)
> > - clk[i] = devm_clk_get(&pdev->dev, clk_names[i]);
> > + for (i = 0; i < MAX_CLKS && name[i]; i++) {
> > + clk[i] = devm_clk_get(&pdev->dev, name[i]);
> > +
> > + if (IS_ERR(clk[i])) {
> > + dev_err(&pdev->dev,
> > + "get basic clk %s fail %ld\n",
> > + name[i], PTR_ERR(clk[i]));
> > + return PTR_ERR(clk[i]);
> > + }
> > + }
> > +
> > + return 0;
> > }
> >
> > static struct scp *init_scp(struct platform_device *pdev,
> > @@ -429,9 +409,8 @@ static struct scp *init_scp(struct platform_device *pdev,
> > {
> > struct genpd_onecell_data *pd_data;
> > struct resource *res;
> > - int i, j;
> > + int i, ret;
> > struct scp *scp;
> > - struct clk *clk[CLK_MAX];
> >
> > scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
> > if (!scp)
> > @@ -484,8 +463,6 @@ static struct scp *init_scp(struct platform_device *pdev,
> >
> > pd_data->num_domains = num;
> >
> > - init_clks(pdev, clk);
> > -
> > for (i = 0; i < num; i++) {
> > struct scp_domain *scpd = &scp->domains[i];
> > struct generic_pm_domain *genpd = &scpd->genpd;
> > @@ -496,27 +473,9 @@ static struct scp *init_scp(struct platform_device *pdev,
> >
> > scpd->data = data;
> >
> > - if (data->clk_id[0]) {
> > - WARN_ON(data->basic_clk_name[0]);
> > -
> > - for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
> > - struct clk *c = clk[data->clk_id[j]];
> > -
> > - if (IS_ERR(c)) {
> > - dev_err(&pdev->dev,
> > - "%s: clk unavailable\n",
> > - data->name);
> > - return ERR_CAST(c);
> > - }
> > -
> > - scpd->clk[j] = c;
> > - }
> > - } else if (data->basic_clk_name[0]) {
> > - for (j = 0; j < MAX_CLKS &&
> > - data->basic_clk_name[j]; j++)
> > - scpd->clk[j] = devm_clk_get(&pdev->dev,
> > - data->basic_clk_name[j]);
> > - }
> > + ret = init_basic_clks(pdev, scpd->clk, data->basic_clk_name);
> > + if (ret)
> > + return ERR_PTR(ret);
> >
> > genpd->name = data->name;
> > genpd->power_off = scpsys_power_off;
> > @@ -573,7 +532,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_CONN_PWR_CON,
> > .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
> > MT2701_TOP_AXI_PROT_EN_CONN_S,
> > - .clk_id = {CLK_NONE},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT2701_POWER_DOMAIN_DISP] = {
> > @@ -581,7 +539,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .sta_mask = PWR_STATUS_DISP,
> > .ctl_offs = SPM_DIS_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > - .clk_id = {CLK_MM},
> > + .basic_clk_name = {"mm"},
> > .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0,
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > @@ -591,7 +549,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_MFG_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(12, 12),
> > - .clk_id = {CLK_MFG},
> > + .basic_clk_name = {"mfg"},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT2701_POWER_DOMAIN_VDEC] = {
> > @@ -600,7 +558,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_VDE_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(12, 12),
> > - .clk_id = {CLK_MM},
> > + .basic_clk_name = {"mm"},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT2701_POWER_DOMAIN_ISP] = {
> > @@ -609,7 +567,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_ISP_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(13, 12),
> > - .clk_id = {CLK_MM},
> > + .basic_clk_name = {"mm"},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT2701_POWER_DOMAIN_BDP] = {
> > @@ -617,7 +575,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .sta_mask = PWR_STATUS_BDP,
> > .ctl_offs = SPM_BDP_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > - .clk_id = {CLK_NONE},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT2701_POWER_DOMAIN_ETH] = {
> > @@ -626,7 +583,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_ETH_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(15, 12),
> > - .clk_id = {CLK_ETHIF},
> > + .basic_clk_name = {"ethif"},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT2701_POWER_DOMAIN_HIF] = {
> > @@ -635,14 +592,13 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_HIF_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(15, 12),
> > - .clk_id = {CLK_ETHIF},
> > + .basic_clk_name = {"ethif"},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT2701_POWER_DOMAIN_IFR_MSC] = {
> > .name = "ifr_msc",
> > .sta_mask = PWR_STATUS_IFR_MSC,
> > .ctl_offs = SPM_IFR_MSC_PWR_CON,
> > - .clk_id = {CLK_NONE},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > };
> > @@ -657,7 +613,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_DIS_PWR_CON,
> > .sram_pdn_bits = GENMASK(8, 8),
> > .sram_pdn_ack_bits = GENMASK(12, 12),
> > - .clk_id = {CLK_MM},
> > + .basic_clk_name = {"mm"},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT2712_POWER_DOMAIN_VDEC] = {
> > @@ -666,7 +622,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_VDE_PWR_CON,
> > .sram_pdn_bits = GENMASK(8, 8),
> > .sram_pdn_ack_bits = GENMASK(12, 12),
> > - .clk_id = {CLK_MM, CLK_VDEC},
> > + .basic_clk_name = {"mm", "vdec"},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT2712_POWER_DOMAIN_VENC] = {
> > @@ -675,7 +631,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_VEN_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(15, 12),
> > - .clk_id = {CLK_MM, CLK_VENC, CLK_JPGDEC},
> > + .basic_clk_name = {"mm", "venc", "jpgdec"},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT2712_POWER_DOMAIN_ISP] = {
> > @@ -684,7 +640,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_ISP_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(13, 12),
> > - .clk_id = {CLK_MM},
> > + .basic_clk_name = {"mm"},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT2712_POWER_DOMAIN_AUDIO] = {
> > @@ -693,7 +649,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_AUDIO_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(15, 12),
> > - .clk_id = {CLK_AUDIO},
> > + .basic_clk_name = {"audio"},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT2712_POWER_DOMAIN_USB] = {
> > @@ -702,7 +658,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_USB_PWR_CON,
> > .sram_pdn_bits = GENMASK(10, 8),
> > .sram_pdn_ack_bits = GENMASK(14, 12),
> > - .clk_id = {CLK_NONE},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT2712_POWER_DOMAIN_USB2] = {
> > @@ -711,7 +666,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_USB2_PWR_CON,
> > .sram_pdn_bits = GENMASK(10, 8),
> > .sram_pdn_ack_bits = GENMASK(14, 12),
> > - .clk_id = {CLK_NONE},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT2712_POWER_DOMAIN_MFG] = {
> > @@ -720,7 +674,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_MFG_PWR_CON,
> > .sram_pdn_bits = GENMASK(8, 8),
> > .sram_pdn_ack_bits = GENMASK(16, 16),
> > - .clk_id = {CLK_MFG},
> > + .basic_clk_name = {"mfg"},
> > .bus_prot_mask = BIT(14) | BIT(21) | BIT(23),
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > @@ -730,7 +684,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = 0x02c0,
> > .sram_pdn_bits = GENMASK(8, 8),
> > .sram_pdn_ack_bits = GENMASK(16, 16),
> > - .clk_id = {CLK_NONE},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT2712_POWER_DOMAIN_MFG_SC2] = {
> > @@ -739,7 +692,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = 0x02c4,
> > .sram_pdn_bits = GENMASK(8, 8),
> > .sram_pdn_ack_bits = GENMASK(16, 16),
> > - .clk_id = {CLK_NONE},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT2712_POWER_DOMAIN_MFG_SC3] = {
> > @@ -748,7 +700,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = 0x01f8,
> > .sram_pdn_bits = GENMASK(8, 8),
> > .sram_pdn_ack_bits = GENMASK(16, 16),
> > - .clk_id = {CLK_NONE},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > };
> > @@ -773,7 +724,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = 0x300,
> > .sram_pdn_bits = GENMASK(8, 8),
> > .sram_pdn_ack_bits = GENMASK(12, 12),
> > - .clk_id = {CLK_VDEC},
> > + .basic_clk_name = {"vdec"},
> > },
> > [MT6797_POWER_DOMAIN_VENC] = {
> > .name = "venc",
> > @@ -781,7 +732,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = 0x304,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(15, 12),
> > - .clk_id = {CLK_NONE},
> > },
> > [MT6797_POWER_DOMAIN_ISP] = {
> > .name = "isp",
> > @@ -789,7 +739,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = 0x308,
> > .sram_pdn_bits = GENMASK(9, 8),
> > .sram_pdn_ack_bits = GENMASK(13, 12),
> > - .clk_id = {CLK_NONE},
> > },
> > [MT6797_POWER_DOMAIN_MM] = {
> > .name = "mm",
> > @@ -797,7 +746,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = 0x30C,
> > .sram_pdn_bits = GENMASK(8, 8),
> > .sram_pdn_ack_bits = GENMASK(12, 12),
> > - .clk_id = {CLK_MM},
> > + .basic_clk_name = {"mm"},
> > .bus_prot_mask = (BIT(1) | BIT(2)),
> > },
> > [MT6797_POWER_DOMAIN_AUDIO] = {
> > @@ -806,7 +755,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = 0x314,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(15, 12),
> > - .clk_id = {CLK_NONE},
> > },
> > [MT6797_POWER_DOMAIN_MFG_ASYNC] = {
> > .name = "mfg_async",
> > @@ -814,7 +762,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = 0x334,
> > .sram_pdn_bits = 0,
> > .sram_pdn_ack_bits = 0,
> > - .clk_id = {CLK_MFG},
> > + .basic_clk_name = {"mfg"},
> > },
> > [MT6797_POWER_DOMAIN_MJC] = {
> > .name = "mjc",
> > @@ -822,7 +770,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = 0x310,
> > .sram_pdn_bits = GENMASK(8, 8),
> > .sram_pdn_ack_bits = GENMASK(12, 12),
> > - .clk_id = {CLK_NONE},
> > },
> > };
> >
> > @@ -847,7 +794,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_ETHSYS_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(15, 12),
> > - .clk_id = {CLK_NONE},
> > .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS,
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > @@ -857,7 +803,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_HIF0_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(15, 12),
> > - .clk_id = {CLK_HIFSEL},
> > + .basic_clk_name = {"hif_sel"},
> > .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0,
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > @@ -867,7 +813,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_HIF1_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(15, 12),
> > - .clk_id = {CLK_HIFSEL},
> > + .basic_clk_name = {"hif_sel"},
> > .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1,
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > @@ -877,7 +823,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_WB_PWR_CON,
> > .sram_pdn_bits = 0,
> > .sram_pdn_ack_bits = 0,
> > - .clk_id = {CLK_NONE},
> > .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
> > .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM,
> > },
> > @@ -894,7 +839,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_CONN_PWR_CON,
> > .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
> > MT2701_TOP_AXI_PROT_EN_CONN_S,
> > - .clk_id = {CLK_NONE},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT7623A_POWER_DOMAIN_ETH] = {
> > @@ -903,7 +847,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_ETH_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(15, 12),
> > - .clk_id = {CLK_ETHIF},
> > + .basic_clk_name = {"ethif"},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT7623A_POWER_DOMAIN_HIF] = {
> > @@ -912,14 +856,13 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_HIF_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(15, 12),
> > - .clk_id = {CLK_ETHIF},
> > + .basic_clk_name = {"ethif"},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT7623A_POWER_DOMAIN_IFR_MSC] = {
> > .name = "ifr_msc",
> > .sta_mask = PWR_STATUS_IFR_MSC,
> > .ctl_offs = SPM_IFR_MSC_PWR_CON,
> > - .clk_id = {CLK_NONE},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > };
> > @@ -935,7 +878,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_VDE_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(12, 12),
> > - .clk_id = {CLK_MM},
> > + .basic_clk_name = {"mm"},
> > },
> > [MT8173_POWER_DOMAIN_VENC] = {
> > .name = "venc",
> > @@ -943,7 +886,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_VEN_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(15, 12),
> > - .clk_id = {CLK_MM, CLK_VENC},
> > + .basic_clk_name = {"mm", "venc"},
> > },
> > [MT8173_POWER_DOMAIN_ISP] = {
> > .name = "isp",
> > @@ -951,7 +894,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_ISP_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(13, 12),
> > - .clk_id = {CLK_MM},
> > + .basic_clk_name = {"mm"},
> > },
> > [MT8173_POWER_DOMAIN_MM] = {
> > .name = "mm",
> > @@ -959,7 +902,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_DIS_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(12, 12),
> > - .clk_id = {CLK_MM},
> > + .basic_clk_name = {"mm"},
> > .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
> > MT8173_TOP_AXI_PROT_EN_MM_M1,
> > },
> > @@ -969,7 +912,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_VEN2_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(15, 12),
> > - .clk_id = {CLK_MM, CLK_VENC_LT},
> > + .basic_clk_name = {"mm", "venc_lt"},
> > },
> > [MT8173_POWER_DOMAIN_AUDIO] = {
> > .name = "audio",
> > @@ -977,7 +920,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_AUDIO_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(15, 12),
> > - .clk_id = {CLK_NONE},
> > },
> > [MT8173_POWER_DOMAIN_USB] = {
> > .name = "usb",
> > @@ -985,7 +927,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_USB_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(15, 12),
> > - .clk_id = {CLK_NONE},
> > .caps = MTK_SCPD_ACTIVE_WAKEUP,
> > },
> > [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
> > @@ -994,7 +935,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = 0,
> > - .clk_id = {CLK_MFG},
> > + .basic_clk_name = {"mfg"},
> > },
> > [MT8173_POWER_DOMAIN_MFG_2D] = {
> > .name = "mfg_2d",
> > @@ -1002,7 +943,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_MFG_2D_PWR_CON,
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(13, 12),
> > - .clk_id = {CLK_NONE},
> > },
> > [MT8173_POWER_DOMAIN_MFG] = {
> > .name = "mfg",
> > @@ -1010,7 +950,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .ctl_offs = SPM_MFG_PWR_CON,
> > .sram_pdn_bits = GENMASK(13, 8),
> > .sram_pdn_ack_bits = GENMASK(21, 16),
> > - .clk_id = {CLK_NONE},
> > .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
> > MT8173_TOP_AXI_PROT_EN_MFG_M0 |
> > MT8173_TOP_AXI_PROT_EN_MFG_M1 |
> > --
> > 1.8.1.1.dirty
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v10 05/12] soc: mediatek: Add multiple step bus protection control
2019-12-19 3:51 ` Nicolas Boichat
@ 2019-12-20 3:30 ` Weiyi Lu
0 siblings, 0 replies; 22+ messages in thread
From: Weiyi Lu @ 2019-12-20 3:30 UTC (permalink / raw)
To: Nicolas Boichat
Cc: Matthias Brugger, Rob Herring, Sascha Hauer, James Liao,
Fan Chen, linux-arm Mailing List, lkml,
moderated list:ARM/Mediatek SoC support, srv_heupstream
On Thu, 2019-12-19 at 11:51 +0800, Nicolas Boichat wrote:
> On Wed, Dec 18, 2019 at 4:31 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
> >
> > Both MT8183 & MT6765 have more control steps of bus protection
> > than previous project. And there add more bus protection registers
> > reside at infracfg & smi-common. Also add new APIs for multiple
> > step bus protection control with more customized arguments.
> >
> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ...
> > diff --git a/include/linux/soc/mediatek/scpsys-ext.h b/include/linux/soc/mediatek/scpsys-ext.h
>
> Will this include file be used by anything other than
> drivers/soc/mediatek/scpsys*.c? If so I think you should keep it in
> drivers/soc/mediatek/ instead.
>
No. And I'll move it under drivers/soc/mediatek/
> I also still had a comment in v9 about clr_mask, otherwise this looks ok.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v10 06/12] soc: mediatek: Use bp_table for all compatibles
2019-12-19 3:54 ` Nicolas Boichat
@ 2019-12-20 3:30 ` Weiyi Lu
0 siblings, 0 replies; 22+ messages in thread
From: Weiyi Lu @ 2019-12-20 3:30 UTC (permalink / raw)
To: Nicolas Boichat
Cc: Matthias Brugger, Rob Herring, Sascha Hauer, James Liao,
Fan Chen, linux-arm Mailing List, lkml,
moderated list:ARM/Mediatek SoC support, srv_heupstream
On Thu, 2019-12-19 at 11:54 +0800, Nicolas Boichat wrote:
> On Wed, Dec 18, 2019 at 4:31 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
> >
> > Only use bp_table for bus protection of all compatibles,
> > instead of mixing bus_prot_mask and bus_prot_reg_update.
>
> ditto, I'd just squash in the previous patch.
>
OK, I'll update in next version.
> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > ---
> > drivers/soc/mediatek/mtk-scpsys.c | 94 ++++++++++++++++++++-------------------
> > 1 file changed, 48 insertions(+), 46 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> > index 5699d9f..c438c53 100644
> > --- a/drivers/soc/mediatek/mtk-scpsys.c
> > +++ b/drivers/soc/mediatek/mtk-scpsys.c
> > @@ -11,7 +11,6 @@
> > #include <linux/platform_device.h>
> > #include <linux/pm_domain.h>
> > #include <linux/regulator/consumer.h>
> > -#include <linux/soc/mediatek/infracfg.h>
> > #include <linux/soc/mediatek/scpsys-ext.h>
> >
> > #include <dt-bindings/power/mt2701-power.h>
> > @@ -88,7 +87,6 @@
> > * @ctl_offs: The offset for main power control register.
> > * @sram_pdn_bits: The mask for sram power control bits.
> > * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> > - * @bus_prot_mask: The mask for single step bus protection.
> > * @basic_clk_name: The basic clocks required by this power domain.
> > * @caps: The flag for active wake-up action.
> > * @bp_table: The mask table for multiple step bus protection.
> > @@ -99,7 +97,6 @@ struct scp_domain_data {
> > int ctl_offs;
> > u32 sram_pdn_bits;
> > u32 sram_pdn_ack_bits;
> > - u32 bus_prot_mask;
> > const char *basic_clk_name[MAX_CLKS];
> > u8 caps;
> > struct bus_prot bp_table[MAX_STEPS];
> > @@ -128,7 +125,6 @@ struct scp {
> > struct regmap *infracfg;
> > struct regmap *smi_common;
> > struct scp_ctrl_reg ctrl_reg;
> > - bool bus_prot_reg_update;
> > };
> >
> > struct scp_subdomain {
> > @@ -142,7 +138,6 @@ struct scp_soc_data {
> > const struct scp_subdomain *subdomains;
> > int num_subdomains;
> > const struct scp_ctrl_reg regs;
> > - bool bus_prot_reg_update;
> > };
> >
> > static int scpsys_domain_is_on(struct scp_domain *scpd)
> > @@ -256,12 +251,6 @@ static int scpsys_bus_protect_enable(struct scp_domain *scpd)
> > {
> > struct scp *scp = scpd->scp;
> >
> > - if (scpd->data->bus_prot_mask) {
> > - return mtk_infracfg_set_bus_protection(scp->infracfg,
> > - scpd->data->bus_prot_mask,
> > - scp->bus_prot_reg_update);
> > - }
> > -
> > return mtk_scpsys_ext_set_bus_protection(scpd->data->bp_table,
> > scp->infracfg, scp->smi_common);
> > }
> > @@ -270,12 +259,6 @@ static int scpsys_bus_protect_disable(struct scp_domain *scpd)
> > {
> > struct scp *scp = scpd->scp;
> >
> > - if (scpd->data->bus_prot_mask) {
> > - return mtk_infracfg_clear_bus_protection(scp->infracfg,
> > - scpd->data->bus_prot_mask,
> > - scp->bus_prot_reg_update);
> > - }
> > -
> > return mtk_scpsys_ext_clear_bus_protection(scpd->data->bp_table,
> > scp->infracfg, scp->smi_common);
> > }
> > @@ -412,8 +395,7 @@ static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
> >
> > static struct scp *init_scp(struct platform_device *pdev,
> > const struct scp_domain_data *scp_domain_data, int num,
> > - const struct scp_ctrl_reg *scp_ctrl_reg,
> > - bool bus_prot_reg_update)
> > + const struct scp_ctrl_reg *scp_ctrl_reg)
> > {
> > struct genpd_onecell_data *pd_data;
> > struct resource *res;
> > @@ -427,8 +409,6 @@ static struct scp *init_scp(struct platform_device *pdev,
> > scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs;
> > scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs;
> >
> > - scp->bus_prot_reg_update = bus_prot_reg_update;
> > -
> > scp->dev = &pdev->dev;
> >
> > res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > @@ -549,8 +529,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> > .name = "conn",
> > .sta_mask = PWR_STATUS_CONN,
> > .ctl_offs = SPM_CONN_PWR_CON,
> > - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
> > - MT2701_TOP_AXI_PROT_EN_CONN_S,
> > + .bp_table = {
> > + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> > + BIT(2) | BIT(8), BIT(2) | BIT(8)),
> > + },
>
> I'm a bit sad we lose the information about the BIT meaning.
>
I'll keep those information in next version.
> Of course this looks ugly and verbose:
> BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
> MT2701_TOP_AXI_PROT_EN_CONN_M |
> MT2701_TOP_AXI_PROT_EN_CONN_S,
> MT2701_TOP_AXI_PROT_EN_CONN_M |
> MT2701_TOP_AXI_PROT_EN_CONN_S),
>
> But if you make "check_clr_mask" a boolean, you wouldn't have to
> repeat the mask twice and you could keep the nice register bit
> definitions.
>
Thanks for the suggestion, I'll add "ignore_clr_ack" for it in next
version.
> [snip, many similar occurences below]
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v10 07/12] soc: mediatek: Remove infracfg misc driver support
2019-12-19 3:56 ` Nicolas Boichat
@ 2019-12-20 3:31 ` Weiyi Lu
0 siblings, 0 replies; 22+ messages in thread
From: Weiyi Lu @ 2019-12-20 3:31 UTC (permalink / raw)
To: Nicolas Boichat
Cc: Matthias Brugger, Rob Herring, Sascha Hauer, James Liao,
Fan Chen, linux-arm Mailing List, lkml,
moderated list:ARM/Mediatek SoC support, srv_heupstream
On Thu, 2019-12-19 at 11:56 +0800, Nicolas Boichat wrote:
> On Wed, Dec 18, 2019 at 4:31 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
> >
> > In previous patches, we introduce scpsys-ext driver that covers
> > the functions which infracfg misc driver provided.
> > And then replace bus_prot_mask with bp_table of all compatibles.
> > Now, we're going to remove infracfg misc drvier which is no longer
> > being used.
> >
> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > ---
> > drivers/soc/mediatek/Kconfig | 10 -----
> > drivers/soc/mediatek/Makefile | 3 +-
> > drivers/soc/mediatek/mtk-infracfg.c | 79 -----------------------------------
> > include/linux/soc/mediatek/infracfg.h | 39 -----------------
> > 4 files changed, 1 insertion(+), 130 deletions(-)
> > delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c
> > delete mode 100644 include/linux/soc/mediatek/infracfg.h
> >
> > diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> > index 2114b56..f837b3c 100644
> > --- a/drivers/soc/mediatek/Kconfig
> > +++ b/drivers/soc/mediatek/Kconfig
> > @@ -10,21 +10,12 @@ config MTK_CMDQ
> > depends on ARCH_MEDIATEK || COMPILE_TEST
> > select MAILBOX
> > select MTK_CMDQ_MBOX
> > - select MTK_INFRACFG
> > help
> > Say yes here to add support for the MediaTek Command Queue (CMDQ)
> > driver. The CMDQ is used to help read/write registers with critical
> > time limitation, such as updating display configuration during the
> > vblank.
> >
> > -config MTK_INFRACFG
> > - bool "MediaTek INFRACFG Support"
> > - select REGMAP
> > - help
> > - Say yes here to add support for the MediaTek INFRACFG controller. The
> > - INFRACFG controller contains various infrastructure registers not
> > - directly associated to any device.
> > -
> > config MTK_PMIC_WRAP
> > tristate "MediaTek PMIC Wrapper Support"
> > depends on RESET_CONTROLLER
> > @@ -38,7 +29,6 @@ config MTK_SCPSYS
> > bool "MediaTek SCPSYS Support"
> > default ARCH_MEDIATEK
> > select REGMAP
> > - select MTK_INFRACFG
> > select PM_GENERIC_DOMAINS if PM
> > help
> > Say yes here to add support for the MediaTek SCPSYS power domain
> > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> > index b442be9..7bf7e88 100644
> > --- a/drivers/soc/mediatek/Makefile
> > +++ b/drivers/soc/mediatek/Makefile
> > @@ -1,5 +1,4 @@
> > # SPDX-License-Identifier: GPL-2.0-only
> > obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
> > -obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
> > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> > -obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> > +obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o mtk-scpsys-ext.o
> > diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c
> > deleted file mode 100644
> > index 341c7ac..0000000
> > --- a/drivers/soc/mediatek/mtk-infracfg.c
> > +++ /dev/null
> > @@ -1,79 +0,0 @@
> > -// SPDX-License-Identifier: GPL-2.0-only
> > -/*
> > - * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
> > - */
> > -
> > -#include <linux/export.h>
> > -#include <linux/jiffies.h>
> > -#include <linux/regmap.h>
> > -#include <linux/soc/mediatek/infracfg.h>
> > -#include <asm/processor.h>
> > -
> > -#define MTK_POLL_DELAY_US 10
> > -#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ))
> > -
> > -#define INFRA_TOPAXI_PROTECTEN 0x0220
> > -#define INFRA_TOPAXI_PROTECTSTA1 0x0228
> > -#define INFRA_TOPAXI_PROTECTEN_SET 0x0260
> > -#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264
> > -
> > -/**
> > - * mtk_infracfg_set_bus_protection - enable bus protection
> > - * @regmap: The infracfg regmap
> > - * @mask: The mask containing the protection bits to be enabled.
> > - * @reg_update: The boolean flag determines to set the protection bits
> > - * by regmap_update_bits with enable register(PROTECTEN) or
> > - * by regmap_write with set register(PROTECTEN_SET).
> > - *
> > - * This function enables the bus protection bits for disabled power
> > - * domains so that the system does not hang when some unit accesses the
> > - * bus while in power down.
> > - */
> > -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
> > - bool reg_update)
> > -{
> > - u32 val;
> > - int ret;
> > -
> > - if (reg_update)
> > - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask,
> > - mask);
> > - else
> > - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask);
> > -
> > - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
> > - val, (val & mask) == mask,
> > - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> > -
> > - return ret;
> > -}
> > -
> > -/**
> > - * mtk_infracfg_clear_bus_protection - disable bus protection
> > - * @regmap: The infracfg regmap
> > - * @mask: The mask containing the protection bits to be disabled.
> > - * @reg_update: The boolean flag determines to clear the protection bits
> > - * by regmap_update_bits with enable register(PROTECTEN) or
> > - * by regmap_write with clear register(PROTECTEN_CLR).
> > - *
> > - * This function disables the bus protection bits previously enabled with
> > - * mtk_infracfg_set_bus_protection.
> > - */
> > -
> > -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
> > - bool reg_update)
> > -{
> > - int ret;
> > - u32 val;
> > -
> > - if (reg_update)
> > - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0);
> > - else
> > - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask);
> > -
> > - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
> > - val, !(val & mask),
> > - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> > -
> > - return ret;
> > -}
> > diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
> > deleted file mode 100644
> > index fd25f01..0000000
> > --- a/include/linux/soc/mediatek/infracfg.h
> > +++ /dev/null
> > @@ -1,39 +0,0 @@
> > -/* SPDX-License-Identifier: GPL-2.0 */
> > -#ifndef __SOC_MEDIATEK_INFRACFG_H
> > -#define __SOC_MEDIATEK_INFRACFG_H
> > -
> > -#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0)
> > -#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
> > -#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
> > -#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6)
> > -#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9)
> > -#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11)
> > -#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12)
> > -#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13)
> > -#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
> > -#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15)
> > -#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16)
> > -#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17)
> > -#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18)
> > -#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19)
> > -#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20)
> > -#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
> > -#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
> > -#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
> > -
> > -#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
> > -#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
> > -#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)
> > -
> > -#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17))
> > -#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25))
> > -#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \
> > - BIT(28))
> > -#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
> > - BIT(7) | BIT(8))
>
> It was really nice to have these all defined, can we move those to
> scpsys-ext.h? (and do the same for MT8183?)
>
Sure. And I'll do the same for MT8183 in next version.
> > -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
> > - bool reg_update);
> > -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
> > - bool reg_update);
> > -#endif /* __SOC_MEDIATEK_INFRACFG_H */
> > --
> > 1.8.1.1.dirty
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2019-12-20 3:31 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-18 8:30 [PATCH v10 00/12] Mediatek MT8183 scpsys support Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 01/12] dt-bindings: mediatek: Add property to mt8183 smi-common Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 02/12] dt-bindings: soc: Add MT8183 power dt-bindings Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 03/12] soc: mediatek: Add basic_clk_name to scp_power_data Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 04/12] soc: mediatek: Use basic_clk_name for all compatibles Weiyi Lu
2019-12-19 3:48 ` Nicolas Boichat
2019-12-20 3:29 ` Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 05/12] soc: mediatek: Add multiple step bus protection control Weiyi Lu
2019-12-19 3:51 ` Nicolas Boichat
2019-12-20 3:30 ` Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 06/12] soc: mediatek: Use bp_table for all compatibles Weiyi Lu
2019-12-19 3:54 ` Nicolas Boichat
2019-12-20 3:30 ` Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 07/12] soc: mediatek: Remove infracfg misc driver support Weiyi Lu
2019-12-19 3:56 ` Nicolas Boichat
2019-12-20 3:31 ` Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 08/12] soc: mediatek: Add subsys clock control for bus protection Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 09/12] soc: mediatek: Add extra sram control Weiyi Lu
2019-12-19 3:57 ` Nicolas Boichat
2019-12-18 8:30 ` [PATCH v10 10/12] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 11/12] arm64: dts: Add power controller device node of MT8183 Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 12/12] arm64: dts: Add power-domains properity to mfgcfg Weiyi Lu
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