From: Yash Shah <yash.shah@sifive.com>
To: robh+dt@kernel.org, mark.rutland@arm.com,
paul.walmsley@sifive.com, palmer@dabbelt.com
Cc: aou@eecs.berkeley.edu, bmeng.cn@gmail.com, green.wan@sifive.com,
allison@lohutok.net, alexios.zavras@intel.com,
gregkh@linuxfoundation.org, tglx@linutronix.de, bp@suse.de,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, sachin.ghadi@sifive.com,
Yash Shah <yash.shah@sifive.com>
Subject: [PATCH v2 0/2] L2 ccache DT and cacheinfo support to read no. of L2 cache ways enabled
Date: Fri, 3 Jan 2020 09:43:19 +0530 [thread overview]
Message-ID: <1578024801-39039-1-git-send-email-yash.shah@sifive.com> (raw)
The patchset includes the patch to implement a private attribute named
"number_of_ways_enabled" in the cacheinfo framework. Reading this
attribute returns the number of L2 cache ways enabled at runtime,
The patchset also include the patch to add DT node for SiFive L2 cache
controller.
This patchset is based on Linux v5.5-rc3 and tested on HiFive Unleashed
board.
Changes in v2:
- Rebase the series on v5.5-rc3
- Remove the reserved-memory node from DT
Yash Shah (2):
riscv: dts: Add DT support for SiFive L2 cache controller
riscv: cacheinfo: Add support to determine no. of L2 cache way enabled
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 15 +++++++++++++++
arch/riscv/include/asm/sifive_l2_cache.h | 2 ++
arch/riscv/kernel/cacheinfo.c | 31 ++++++++++++++++++++++++++++++
drivers/soc/sifive/sifive_l2_cache.c | 5 +++++
4 files changed, 53 insertions(+)
--
2.7.4
next reply other threads:[~2020-01-03 4:13 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-03 4:13 Yash Shah [this message]
2020-01-03 4:13 ` [PATCH v2 1/2] riscv: dts: Add DT support for SiFive L2 cache controller Yash Shah
2020-01-04 0:57 ` Paul Walmsley
2020-01-03 4:13 ` [PATCH v2 2/2] riscv: cacheinfo: Add support to determine no. of L2 cache way enabled Yash Shah
2020-01-06 9:10 ` Anup Patel
2020-01-07 3:55 ` Yash Shah
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