From: Yuti Amonkar <yamonkar@cadence.com>
To: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<kishon@ti.com>, <robh+dt@kernel.org>, <mark.rutland@arm.com>,
<maxime@cerno.tech>
Cc: <jsarha@ti.com>, <tomi.valkeinen@ti.com>, <praneeth@ti.com>,
<mparab@cadence.com>, <sjakhade@cadence.com>,
<yamonkar@cadence.com>
Subject: [PATCH v3 05/14] phy: cadence-torrent: Add wrapper for DPTX register access
Date: Wed, 22 Jan 2020 11:45:09 +0100 [thread overview]
Message-ID: <1579689918-7181-6-git-send-email-yamonkar@cadence.com> (raw)
In-Reply-To: <1579689918-7181-1-git-send-email-yamonkar@cadence.com>
From: Swapnil Jakhade <sjakhade@cadence.com>
Add wrapper functions to read, write DisplayPort specific PHY registers to
improve code readability.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
drivers/phy/cadence/phy-cadence-torrent.c | 71 ++++++++++++++++++++++---------
1 file changed, 50 insertions(+), 21 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 59c85d8..5c7c185 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -140,13 +140,31 @@ static void cdns_torrent_phy_write(struct cdns_torrent_phy *cdns_phy,
writel(val, cdns_phy->sd_base + offset);
}
+/* DPTX mmr access functions */
+
+static void cdns_torrent_dp_write(struct cdns_torrent_phy *cdns_phy,
+ u32 offset, u32 val)
+{
+ writel(val, cdns_phy->base + offset);
+}
+
+static u32 cdns_torrent_dp_read(struct cdns_torrent_phy *cdns_phy, u32 offset)
+{
+ return readl(cdns_phy->base + offset);
+}
+
+#define cdns_torrent_dp_read_poll_timeout(cdns_phy, offset, val, cond, \
+ delay_us, timeout_us) \
+ readl_poll_timeout((cdns_phy)->base + (offset), \
+ val, cond, delay_us, timeout_us)
+
static int cdns_torrent_dp_init(struct phy *phy)
{
unsigned char lane_bits;
struct cdns_torrent_phy *cdns_phy = phy_get_drvdata(phy);
- writel(0x0003, cdns_phy->base + PHY_AUX_CTRL); /* enable AUX */
+ cdns_torrent_dp_write(cdns_phy, PHY_AUX_CTRL, 0x0003); /* enable AUX */
/* PHY PMA registers configuration function */
cdns_torrent_dp_pma_cfg(cdns_phy);
@@ -195,11 +213,11 @@ static int cdns_torrent_dp_init(struct phy *phy)
* used lanes
*/
lane_bits = (1 << cdns_phy->num_lanes) - 1;
- writel(((0xF & ~lane_bits) << 4) | (0xF & lane_bits),
- cdns_phy->base + PHY_RESET);
+ cdns_torrent_dp_write(cdns_phy, PHY_RESET,
+ ((0xF & ~lane_bits) << 4) | (0xF & lane_bits));
/* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
- writel(0x0001, cdns_phy->base + PHY_PMA_XCVR_PLLCLK_EN);
+ cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
/* PHY PMA registers configuration functions */
cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy);
@@ -219,8 +237,8 @@ void cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
unsigned int reg;
int ret;
- ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_CMN_READY, reg,
- reg & 1, 0, 500);
+ ret = cdns_torrent_dp_read_poll_timeout(cdns_phy, PHY_PMA_CMN_READY,
+ reg, reg & 1, 0, 500);
if (ret == -ETIMEDOUT)
dev_err(cdns_phy->dev,
"timeout waiting for PMA common ready\n");
@@ -391,8 +409,10 @@ static void cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy)
* waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
* master lane
*/
- ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_PLLCLK_EN_ACK,
- read_val, read_val & 1, 0, POLL_TIMEOUT_US);
+ ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
+ PHY_PMA_XCVR_PLLCLK_EN_ACK,
+ read_val, read_val & 1, 0,
+ POLL_TIMEOUT_US);
if (ret == -ETIMEDOUT)
dev_err(cdns_phy->dev,
"timeout waiting for link PLL clock enable ack\n");
@@ -417,28 +437,35 @@ static void cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy)
break;
}
- writel(write_val1, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ);
+ cdns_torrent_dp_write(cdns_phy,
+ PHY_PMA_XCVR_POWER_STATE_REQ, write_val1);
+
+ ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
+ PHY_PMA_XCVR_POWER_STATE_ACK,
+ read_val,
+ (read_val & mask) == write_val1,
+ 0, POLL_TIMEOUT_US);
- ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_ACK,
- read_val, (read_val & mask) == write_val1, 0,
- POLL_TIMEOUT_US);
if (ret == -ETIMEDOUT)
dev_err(cdns_phy->dev,
"timeout waiting for link power state ack\n");
- writel(0, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ);
+ cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ, 0);
ndelay(100);
- writel(write_val2, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ);
+ cdns_torrent_dp_write(cdns_phy,
+ PHY_PMA_XCVR_POWER_STATE_REQ, write_val2);
- ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_ACK,
- read_val, (read_val & mask) == write_val2, 0,
- POLL_TIMEOUT_US);
+ ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
+ PHY_PMA_XCVR_POWER_STATE_ACK,
+ read_val,
+ (read_val & mask) == write_val2,
+ 0, POLL_TIMEOUT_US);
if (ret == -ETIMEDOUT)
dev_err(cdns_phy->dev,
"timeout waiting for link power state ack\n");
- writel(0, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ);
+ cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ, 0);
ndelay(100);
}
@@ -450,9 +477,11 @@ static void cdns_dp_phy_write_field(struct cdns_torrent_phy *cdns_phy,
{
unsigned int read_val;
- read_val = readl(cdns_phy->base + offset);
- writel(((val << start_bit) | (read_val & ~(((1 << num_bits) - 1) <<
- start_bit))), cdns_phy->base + offset);
+ read_val = cdns_torrent_dp_read(cdns_phy, offset);
+ cdns_torrent_dp_write(cdns_phy, offset,
+ ((val << start_bit) |
+ (read_val & ~(((1 << num_bits) - 1) <<
+ start_bit))));
}
static int cdns_torrent_phy_probe(struct platform_device *pdev)
--
2.4.5
next prev parent reply other threads:[~2020-01-22 10:45 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-22 10:45 [PATCH v3 00/14] PHY: Update Cadence Torrent PHY driver with reconfiguration Yuti Amonkar
2020-01-22 10:45 ` [PATCH v3 01/14] dt-bindings: phy: Convert Cadence MHDP PHY bindings to YAML Yuti Amonkar
2020-01-27 16:25 ` Rob Herring
2020-01-22 10:45 ` [PATCH v3 02/14] phy: cadence-dp: Rename to phy-cadence-torrent Yuti Amonkar
2020-01-22 10:45 ` [PATCH v3 03/14] phy: cadence-torrent: Adopt Torrent nomenclature Yuti Amonkar
2020-01-22 10:45 ` [PATCH v3 04/14] phy: cadence-torrent: Add wrapper for PHY register access Yuti Amonkar
2020-01-22 10:45 ` Yuti Amonkar [this message]
2020-01-22 10:45 ` [PATCH v3 06/14] phy: cadence-torrent: Refactor code for reusability Yuti Amonkar
2020-01-22 10:45 ` [PATCH v3 07/14] phy: cadence-torrent: Add 19.2 MHz reference clock support Yuti Amonkar
2020-01-22 10:45 ` [PATCH v3 08/14] phy: cadence-torrent: Implement PHY configure APIs Yuti Amonkar
2020-01-22 10:45 ` [PATCH v3 09/14] phy: cadence-torrent: Use regmap to read and write Torrent PHY registers Yuti Amonkar
2020-01-22 10:45 ` [PATCH v3 10/14] phy: cadence-torrent: Use regmap to read and write DPTX " Yuti Amonkar
2020-01-22 10:45 ` [PATCH v3 11/14] dt-bindings: phy: phy-cadence-torrent: Add platform dependent compatible string Yuti Amonkar
2020-01-22 10:45 ` [PATCH v3 12/14] phy: cadence-torrent: Add platform dependent initialization structure Yuti Amonkar
2020-01-22 10:45 ` [PATCH v3 13/14] dt-bindings: phy: phy-cadence-torrent: Add subnode bindings Yuti Amonkar
2020-01-27 16:42 ` Rob Herring
2020-01-28 10:04 ` Jyri Sarha
2020-01-28 15:40 ` Rob Herring
2020-01-27 16:45 ` Rob Herring
2020-01-22 10:45 ` [PATCH v3 14/14] phy: cadence-torrent: Add support for " Yuti Amonkar
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