From: Can Guo <cang@codeaurora.org>
To: asutoshd@codeaurora.org, nguyenb@codeaurora.org,
hongwus@codeaurora.org, rnayak@codeaurora.org,
linux-scsi@vger.kernel.org, kernel-team@android.com,
saravanak@google.com, salyzyn@google.com, cang@codeaurora.org
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Alim Akhtar <alim.akhtar@samsung.com>,
Avri Altman <avri.altman@wdc.com>,
"James E.J. Bottomley" <jejb@linux.ibm.com>,
"Martin K. Petersen" <martin.petersen@oracle.com>,
linux-arm-msm@vger.kernel.org (open list:ARM/QUALCOMM SUPPORT),
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v5 7/8] scsi: ufs-qcom: Delay specific time before gate ref clk
Date: Mon, 3 Feb 2020 01:17:49 -0800 [thread overview]
Message-ID: <1580721472-10784-8-git-send-email-cang@codeaurora.org> (raw)
In-Reply-To: <1580721472-10784-1-git-send-email-cang@codeaurora.org>
After enter hibern8, as UFS JEDEC ver 3.0 requires, a specific gating wait
time is required before disable the device reference clock. If it is not
specified, use the old delay.
Signed-off-by: Can Guo <cang@codeaurora.org>
Reviewed-by: Asutosh Das <asutoshd@codeaurora.org>
---
drivers/scsi/ufs/ufs-qcom.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c
index 85d7c17..3b5b2d9 100644
--- a/drivers/scsi/ufs/ufs-qcom.c
+++ b/drivers/scsi/ufs/ufs-qcom.c
@@ -833,6 +833,8 @@ static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
{
+ unsigned long gating_wait;
+
if (host->dev_ref_clk_ctrl_mmio &&
(enable ^ host->is_dev_ref_clk_enabled)) {
u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
@@ -845,11 +847,16 @@ static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
/*
* If we are here to disable this clock it might be immediately
* after entering into hibern8 in which case we need to make
- * sure that device ref_clk is active at least 1us after the
+ * sure that device ref_clk is active for specific time after
* hibern8 enter.
*/
- if (!enable)
- udelay(1);
+ if (!enable) {
+ gating_wait = host->hba->dev_info.clk_gating_wait_us;
+ if (!gating_wait)
+ udelay(1);
+ else
+ usleep_range(gating_wait, gating_wait + 10);
+ }
writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2020-02-03 9:18 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1580721472-10784-1-git-send-email-cang@codeaurora.org>
2020-02-03 9:17 ` [PATCH v5 1/8] scsi: ufs: Flush exception event before suspend Can Guo
2020-02-03 21:31 ` [EXT] " Bean Huo (beanhuo)
2020-02-03 9:17 ` [PATCH v5 2/8] scsi: ufs: set load before setting voltage in regulators Can Guo
2020-02-03 21:41 ` [EXT] " Bean Huo (beanhuo)
2020-02-04 6:16 ` Stanley Chu
2020-02-03 9:17 ` [PATCH v5 3/8] scsi: ufs: Remove the check before call setup clock notify vops Can Guo
2020-02-03 22:14 ` [EXT] " Bean Huo (beanhuo)
2020-02-04 6:16 ` Stanley Chu
2020-02-03 9:17 ` [PATCH v5 4/8] scsi: ufs-qcom: Adjust bus bandwidth voting and unvoting Can Guo
2020-02-05 2:17 ` Asutosh Das (asd)
2020-02-03 9:17 ` [PATCH v5 5/8] scsi: ufs: Fix ufshcd_hold() caused scheduling while atomic Can Guo
2020-02-03 22:07 ` [EXT] " Bean Huo (beanhuo)
2020-02-04 6:26 ` Stanley Chu
2020-02-03 9:17 ` [PATCH v5 6/8] scsi: ufs: Add dev ref clock gating wait time support Can Guo
2020-02-04 15:26 ` [EXT] " Bean Huo (beanhuo)
2020-02-05 2:50 ` Stanley Chu
2020-02-05 4:52 ` Can Guo
2020-02-06 0:55 ` Stanley Chu
2020-02-06 2:39 ` Can Guo
2020-02-03 9:17 ` Can Guo [this message]
2020-02-05 7:20 ` [PATCH v5 7/8] scsi: ufs-qcom: Delay specific time before gate ref clk hongwus
2020-02-03 9:17 ` [PATCH v5 8/8] scsi: ufs: Select INITIAL adapt for HS Gear4 Can Guo
2020-02-04 15:26 ` [EXT] " Bean Huo (beanhuo)
2020-02-05 7:38 ` hongwus
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