From: peng.fan@nxp.com
To: shawnguo@kernel.org, s.hauer@pengutronix.de, sboyd@kernel.org,
abel.vesa@nxp.com, aisheng.dong@nxp.com, leonard.crestez@nxp.com
Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
ping.bai@nxp.com, Anson.Huang@nxp.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
Peng Fan <peng.fan@nxp.com>
Subject: [PATCH 5/7] clk: imx: imx7ulp: add IMX7ULP_CLK_ARM_FREQ clk
Date: Tue, 4 Feb 2020 21:34:35 +0800 [thread overview]
Message-ID: <1580823277-13644-6-git-send-email-peng.fan@nxp.com> (raw)
In-Reply-To: <1580823277-13644-1-git-send-email-peng.fan@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
Add IMX7ULP_CLK_ARM_FREQ clk entry for cpufreq usage.
The cpu in device tree needs use this index as clock.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-imx7ulp.c | 15 ++++++++++++++-
include/dt-bindings/clock/imx7ulp-clock.h | 3 ++-
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
index 0620d6c8c072..daa770432bc8 100644
--- a/drivers/clk/imx/clk-imx7ulp.c
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -56,6 +56,7 @@ static const int pcc3_uart_clk_ids[] __initconst = {
static struct clk **pcc2_uart_clks[ARRAY_SIZE(pcc2_uart_clk_ids) + 1] __initdata;
static struct clk **pcc3_uart_clks[ARRAY_SIZE(pcc3_uart_clk_ids) + 1] __initdata;
+static struct clk_hw **hws_scg1;
static void __init imx7ulp_clk_scg1_init(struct device_node *np)
{
struct clk_hw_onecell_data *clk_data;
@@ -139,6 +140,8 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np)
imx_check_clk_hws(hws, clk_data->num);
+ hws_scg1 = hws;
+
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
}
CLK_OF_DECLARE(imx7ulp_clk_scg1, "fsl,imx7ulp-scg1", imx7ulp_clk_scg1_init);
@@ -270,7 +273,17 @@ static void __init imx7ulp_clk_smc1_init(struct device_node *np)
base = of_iomap(np, 0);
WARN_ON(!base);
- hws[IMX7ULP_CLK_ARM] = imx_clk_hw_mux_flags("arm", base + 0x10, 8, 2, arm_sels, ARRAY_SIZE(arm_sels), CLK_IS_CRITICAL);
+ hws[IMX7ULP_CLK_ARM] = imx_clk_hw_mux_flags("arm", base + 0x10, 8, 2, arm_sels, ARRAY_SIZE(arm_sels), 0);
+
+ hws[IMX7ULP_CLK_ARM_FREQ] = imx_clk_hw_cpuv2("arm_freq", "arm",
+ hws[IMX7ULP_CLK_ARM],
+ hws_scg1[IMX7ULP_CLK_CORE_DIV],
+ hws_scg1[IMX7ULP_CLK_HSRUN_CORE_DIV],
+ hws_scg1[IMX7ULP_CLK_SYS_SEL],
+ hws_scg1[IMX7ULP_CLK_HSRUN_SYS_SEL],
+ hws_scg1[IMX7ULP_CLK_SPLL_SEL],
+ hws_scg1[IMX7ULP_CLK_SPLL_PFD0],
+ hws_scg1[IMX7ULP_CLK_FIRC], CLK_IS_CRITICAL, 0);
imx_check_clk_hws(hws, clk_data->num);
diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h
index 38145bdcd975..ecd832dd1c9c 100644
--- a/include/dt-bindings/clock/imx7ulp-clock.h
+++ b/include/dt-bindings/clock/imx7ulp-clock.h
@@ -110,7 +110,8 @@
/* SMC1 */
#define IMX7ULP_CLK_ARM 0
+#define IMX7ULP_CLK_ARM_FREQ 1
-#define IMX7ULP_CLK_SMC1_END 1
+#define IMX7ULP_CLK_SMC1_END 2
#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
--
2.16.4
next prev parent reply other threads:[~2020-02-04 13:41 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-04 13:34 [PATCH 0/7] ARM: imx: imx7ulp: add cpufreq support peng.fan
2020-02-04 13:34 ` [PATCH 1/7] clk: imx: Fix division by zero warning on pfdv2 peng.fan
2020-02-04 13:34 ` [PATCH 2/7] clk: imx: pfdv2: switch to use determine_rate peng.fan
2020-02-04 13:34 ` [PATCH 3/7] clk: imx: pfdv2: determine best parent rate peng.fan
2020-02-04 13:34 ` [PATCH 4/7] clk: imx: add imx_hw_clk_cpuv2 for i.MX7ULP peng.fan
2020-02-10 22:38 ` Stephen Boyd
2020-02-11 1:24 ` Peng Fan
2020-02-04 13:34 ` peng.fan [this message]
2020-02-04 13:34 ` [PATCH 6/7] ARM: imx: imx7ulp: support HSRUN mode peng.fan
2020-02-04 13:50 ` Fabio Estevam
2020-02-05 2:59 ` Peng Fan
2020-02-04 13:34 ` [PATCH 7/7] ARM: imx: imx7ulp: create cpufreq device peng.fan
2020-02-04 13:45 ` [PATCH 0/7] ARM: imx: imx7ulp: add cpufreq support Fabio Estevam
2020-02-05 3:07 ` Peng Fan
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