From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9706FC11D00 for ; Thu, 20 Feb 2020 08:12:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6FA8324676 for ; Thu, 20 Feb 2020 08:12:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="HCt6hTi1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726877AbgBTIMt (ORCPT ); Thu, 20 Feb 2020 03:12:49 -0500 Received: from mail26.static.mailgun.info ([104.130.122.26]:40549 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726766AbgBTIMt (ORCPT ); Thu, 20 Feb 2020 03:12:49 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1582186369; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=KSFN05C5NtOXiH34t8XT3SiOfyQlUfmASjWs5M6ZyJ8=; b=HCt6hTi1CWW3f0exEDUfkYwOGpz1ZPVU0ZJNNejxft6Pslf7h6oMmz4PHCUbHnd/k6CF9TJf RJF7Us2Lr8IDkXxE8ThVYD2hWXcGqL+2UXyJ0lK98IZyHnlGpal57/szl3jX03FH76mf03gt zJcwiuhlXYW8s1a5dDWQ0Foe/OQ= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e4e3f76.7fb80366bca8-smtp-out-n03; Thu, 20 Feb 2020 08:12:38 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id E059BC43383; Thu, 20 Feb 2020 08:12:38 +0000 (UTC) Received: from smasetty-linux.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: smasetty) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2FDB8C4479F; Thu, 20 Feb 2020 08:12:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2FDB8C4479F Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=smasetty@codeaurora.org From: Sharat Masetty To: freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, jcrouse@codeaurora.org, mka@chromium.org, dianders@chromium.org, Sharat Masetty Subject: [PATCH] dt-bindings: arm-smmu: update the list of clocks Date: Thu, 20 Feb 2020 13:42:22 +0530 Message-Id: <1582186342-3484-2-git-send-email-smasetty@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1582186342-3484-1-git-send-email-smasetty@codeaurora.org> References: <1582186342-3484-1-git-send-email-smasetty@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds a clock definition needed for powering on the GPU TBUs and the GPU TCU. Signed-off-by: Sharat Masetty --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 6515dbe..235c0df 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -28,6 +28,7 @@ properties: - enum: - qcom,msm8996-smmu-v2 - qcom,msm8998-smmu-v2 + - qcom,sc7180-smmu-v2 - qcom,sdm845-smmu-v2 - const: qcom,smmu-v2 @@ -116,6 +117,7 @@ properties: items: - const: bus - const: iface + - const: mem_iface_clk clocks: items: @@ -123,6 +125,7 @@ properties: smmu ptw - description: interface clock required to access smmu's registers through the TCU's programming interface. + - description: core clock required for the GPU SMMU TBUs and the GPU TCU power-domains: maxItems: 1 -- 1.9.1