From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82BE7C4725A for ; Tue, 5 May 2020 17:14:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5BEAB20752 for ; Tue, 5 May 2020 17:14:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=st.com header.i=@st.com header.b="vFlERtmK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730635AbgEEROj (ORCPT ); Tue, 5 May 2020 13:14:39 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:56556 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729315AbgEEROh (ORCPT ); Tue, 5 May 2020 13:14:37 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 045Gw53F013112; Tue, 5 May 2020 19:14:17 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=MMKMMyzzzPUYk6uvJXUW0sOtOYv8aZUtFOljFKKKfZg=; b=vFlERtmK/mpE/cf9Tmd2ynhs6B9uccRcBgZ6rnKgautoq7IXNztYasVe+F/xqjSdUrrf viWmZovPZfavhxa5nJp08UrdAkmuX0WQobs49T3MfqJjLm0h3xqQpzFYbV7QkkQMUEuM M2I1GeL+7jXevtO/aR7/mYFVsateSxJq7DsVVH6pK1QaTdciwFMC7bLWXqWId/0gG7CO 6hTa74rsSHpE2qfMjQJu0MqwbJazMCTGIE0zbPF/mE9zpMeSVflKxwQzxFb3ILSe3zJd KpqxGG09Piq5+bBM5BwgnLE9NqcDZ7o88MEpdun1sREn/Kt3EfPYXDOpMUrVbT2d0xlK ig== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 30ryrj9dh9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 05 May 2020 19:14:17 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 6C15910002A; Tue, 5 May 2020 19:14:17 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag6node2.st.com [10.75.127.17]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 5BCA92B5A7A; Tue, 5 May 2020 19:14:17 +0200 (CEST) Received: from localhost (10.75.127.47) by SFHDAG6NODE2.st.com (10.75.127.17) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 5 May 2020 19:14:16 +0200 From: Christophe Kerello To: , , , , , , CC: , , , , , Christophe Kerello Subject: [PATCH v3 10/10] mtd: rawnand: stm32_fmc2: get resources from parent node Date: Tue, 5 May 2020 19:11:08 +0200 Message-ID: <1588698668-25288-11-git-send-email-christophe.kerello@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1588698668-25288-1-git-send-email-christophe.kerello@st.com> References: <1588698668-25288-1-git-send-email-christophe.kerello@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG4NODE2.st.com (10.75.127.11) To SFHDAG6NODE2.st.com (10.75.127.17) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-05-05_09:2020-05-04,2020-05-05 signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org FMC2 EBI support has been added. Common resources (registers base and clock) are now shared between the 2 drivers. It means that the common resources should now be found in the parent device when EBI node is available. Signed-off-by: Christophe Kerello --- drivers/mtd/nand/raw/Kconfig | 3 +- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 89 +++++++++++++++++++++++----------- 2 files changed, 62 insertions(+), 30 deletions(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 12b715a..28dccd5 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -419,8 +419,7 @@ config MTD_NAND_TEGRA config MTD_NAND_STM32_FMC2 tristate "Support for NAND controller on STM32MP SoCs" depends on MACH_STM32MP157 || COMPILE_TEST - select REGMAP - select REGMAP_MMIO + select MFD_SYSCON help Enables support for NAND Flash chips on SoCs containing the FMC2 NAND controller. This controller is found on STM32MP SoCs. diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index 76571da..dfab6b1 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -11,8 +11,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -204,16 +206,6 @@ #define FMC2_BCHDSR4_EBP7 GENMASK(12, 0) #define FMC2_BCHDSR4_EBP8 GENMASK(28, 16) -/* Regmap registers configuration */ -#define FMC2_MAX_REGISTER 0x3fc - -static const struct regmap_config stm32_fmc2_regmap_cfg = { - .reg_bits = 32, - .val_bits = 32, - .reg_stride = sizeof(u32), - .max_register = FMC2_MAX_REGISTER, -}; - enum stm32_fmc2_ecc { FMC2_ECC_HAM = 1, FMC2_ECC_BCH4 = 4, @@ -261,6 +253,7 @@ struct stm32_fmc2_nfc { phys_addr_t data_phys_addr[FMC2_MAX_CE]; struct clk *clk; u8 irq_state; + bool has_parent; struct dma_chan *dma_tx_ch; struct dma_chan *dma_rx_ch; @@ -1384,8 +1377,9 @@ static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc) pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT); /* Enable FMC2 controller */ - regmap_update_bits(nfc->regmap, FMC2_BCR1, - FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN); + if (!nfc->has_parent) + regmap_update_bits(nfc->regmap, FMC2_BCR1, + FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN); regmap_write(nfc->regmap, FMC2_PCR, pcr); regmap_write(nfc->regmap, FMC2_PMEM, FMC2_PMEM_DEFAULT); @@ -1815,6 +1809,53 @@ static int stm32_fmc2_nfc_parse_dt(struct stm32_fmc2_nfc *nfc) return ret; } +static int stm32_fmc2_nfc_set_regmap_clk(struct platform_device *pdev, + struct stm32_fmc2_nfc *nfc) +{ + struct device *dev = &pdev->dev; + struct resource res; + int ret; + + if (nfc->has_parent) + dev = dev->parent; + + ret = of_address_to_resource(dev->of_node, 0, &res); + if (ret) + return ret; + + nfc->io_phys_addr = res.start; + + nfc->regmap = device_node_to_regmap(dev->of_node); + if (IS_ERR(nfc->regmap)) + return PTR_ERR(nfc->regmap); + + nfc->clk = devm_clk_get(dev, NULL); + if (IS_ERR(nfc->clk)) + return PTR_ERR(nfc->clk); + + return 0; +} + +static bool stm32_fmc2_nfc_check_for_parent(struct platform_device *pdev) +{ + u32 i; + int nb_resources = 0; + + /* Count the number of resources in reg property */ + for (i = 0; i < pdev->num_resources; i++) { + struct resource *res = &pdev->resource[i]; + + if (resource_type(res) == IORESOURCE_MEM) + nb_resources++; + } + + /* Each CS needs 3 resources defined (data, cmd and addr) */ + if (nb_resources % 3) + return false; + + return true; +} + static int stm32_fmc2_nfc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1824,8 +1865,8 @@ static int stm32_fmc2_nfc_probe(struct platform_device *pdev) struct resource *res; struct mtd_info *mtd; struct nand_chip *chip; - void __iomem *mmio; int chip_cs, mem_region, ret, irq; + int num_region = 1; nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL); if (!nfc) @@ -1834,23 +1875,19 @@ static int stm32_fmc2_nfc_probe(struct platform_device *pdev) nfc->dev = dev; nand_controller_init(&nfc->base); nfc->base.ops = &stm32_fmc2_nfc_controller_ops; + nfc->has_parent = stm32_fmc2_nfc_check_for_parent(pdev); + if (nfc->has_parent) + num_region = 0; ret = stm32_fmc2_nfc_parse_dt(nfc); if (ret) return ret; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - mmio = devm_ioremap_resource(dev, res); - if (IS_ERR(mmio)) - return PTR_ERR(mmio); - - nfc->regmap = devm_regmap_init_mmio(dev, mmio, &stm32_fmc2_regmap_cfg); - if (IS_ERR(nfc->regmap)) - return PTR_ERR(nfc->regmap); - - nfc->io_phys_addr = res->start; + ret = stm32_fmc2_nfc_set_regmap_clk(pdev, nfc); + if (ret) + return ret; - for (chip_cs = 0, mem_region = 1; chip_cs < FMC2_MAX_CE; + for (chip_cs = 0, mem_region = num_region; chip_cs < FMC2_MAX_CE; chip_cs++, mem_region += 3) { if (!(nfc->cs_assigned & BIT(chip_cs))) continue; @@ -1888,10 +1925,6 @@ static int stm32_fmc2_nfc_probe(struct platform_device *pdev) init_completion(&nfc->complete); - nfc->clk = devm_clk_get(dev, NULL); - if (IS_ERR(nfc->clk)) - return PTR_ERR(nfc->clk); - ret = clk_prepare_enable(nfc->clk); if (ret) { dev_err(dev, "can not enable the clock\n"); -- 1.9.1